arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0>;
  40                         clock-frequency = <1300000000>;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a15";
  46                         reg = <1>;
  47                         clock-frequency = <1300000000>;
  48                 };
  49         };
  50
  51         gic: interrupt-controller@f1001000 {
  52                 compatible = "arm,cortex-a15-gic";
  53                 #interrupt-cells = <3>;
  54                 #address-cells = <0>;
  55                 interrupt-controller;
  56                 reg = <0 0xf1001000 0 0x1000>,
  57                         <0 0xf1002000 0 0x1000>,
  58                         <0 0xf1004000 0 0x2000>,
  59                         <0 0xf1006000 0 0x2000>;
  60                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  61         };
  62
  63         gpio0: gpio@e6050000 {
  64                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  65                 reg = <0 0xe6050000 0 0x50>;
  66                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  67                 #gpio-cells = <2>;
  68                 gpio-controller;
  69                 gpio-ranges = <&pfc 0 0 32>;
  70                 #interrupt-cells = <2>;
  71                 interrupt-controller;
  72         };
  73
  74         gpio1: gpio@e6051000 {
  75                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  76                 reg = <0 0xe6051000 0 0x50>;
  77                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  78                 #gpio-cells = <2>;
  79                 gpio-controller;
  80                 gpio-ranges = <&pfc 0 32 32>;
  81                 #interrupt-cells = <2>;
  82                 interrupt-controller;
  83         };
  84
  85         gpio2: gpio@e6052000 {
  86                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  87                 reg = <0 0xe6052000 0 0x50>;
  88                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  89                 #gpio-cells = <2>;
  90                 gpio-controller;
  91                 gpio-ranges = <&pfc 0 64 32>;
  92                 #interrupt-cells = <2>;
  93                 interrupt-controller;
  94         };
  95
  96         gpio3: gpio@e6053000 {
  97                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  98                 reg = <0 0xe6053000 0 0x50>;
  99                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 100                 #gpio-cells = <2>;
 101                 gpio-controller;
 102                 gpio-ranges = <&pfc 0 96 32>;
 103                 #interrupt-cells = <2>;
 104                 interrupt-controller;
 105         };
 106
 107         gpio4: gpio@e6054000 {
 108                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 109                 reg = <0 0xe6054000 0 0x50>;
 110                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 111                 #gpio-cells = <2>;
 112                 gpio-controller;
 113                 gpio-ranges = <&pfc 0 128 32>;
 114                 #interrupt-cells = <2>;
 115                 interrupt-controller;
 116         };
 117
 118         gpio5: gpio@e6055000 {
 119                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 120                 reg = <0 0xe6055000 0 0x50>;
 121                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 122                 #gpio-cells = <2>;
 123                 gpio-controller;
 124                 gpio-ranges = <&pfc 0 160 32>;
 125                 #interrupt-cells = <2>;
 126                 interrupt-controller;
 127         };
 128
 129         gpio6: gpio@e6055400 {
 130                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 131                 reg = <0 0xe6055400 0 0x50>;
 132                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 133                 #gpio-cells = <2>;
 134                 gpio-controller;
 135                 gpio-ranges = <&pfc 0 192 32>;
 136                 #interrupt-cells = <2>;
 137                 interrupt-controller;
 138         };
 139
 140         gpio7: gpio@e6055800 {
 141                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 142                 reg = <0 0xe6055800 0 0x50>;
 143                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 144                 #gpio-cells = <2>;
 145                 gpio-controller;
 146                 gpio-ranges = <&pfc 0 224 26>;
 147                 #interrupt-cells = <2>;
 148                 interrupt-controller;
 149         };
 150
 151         thermal@e61f0000 {
 152                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 153                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 154                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 155                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 156         };
 157
 158         timer {
 159                 compatible = "arm,armv7-timer";
 160                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 161                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 163                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 164         };
 165
 166         irqc0: interrupt-controller@e61c0000 {
 167                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 168                 #interrupt-cells = <2>;
 169                 interrupt-controller;
 170                 reg = <0 0xe61c0000 0 0x200>;
 171                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 172                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 173                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 174                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 175                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 176                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 177                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 178                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 179                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 180                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 181         };
 182
 183         i2c0: i2c@e6508000 {
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 compatible = "renesas,i2c-r8a7791";
 187                 reg = <0 0xe6508000 0 0x40>;
 188                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 190                 status = "disabled";
 191         };
 192
 193         i2c1: i2c@e6518000 {
 194                 #address-cells = <1>;
 195                 #size-cells = <0>;
 196                 compatible = "renesas,i2c-r8a7791";
 197                 reg = <0 0xe6518000 0 0x40>;
 198                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 200                 status = "disabled";
 201         };
 202
 203         i2c2: i2c@e6530000 {
 204                 #address-cells = <1>;
 205                 #size-cells = <0>;
 206                 compatible = "renesas,i2c-r8a7791";
 207                 reg = <0 0xe6530000 0 0x40>;
 208                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 209                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 210                 status = "disabled";
 211         };
 212
 213         i2c3: i2c@e6540000 {
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216                 compatible = "renesas,i2c-r8a7791";
 217                 reg = <0 0xe6540000 0 0x40>;
 218                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 220                 status = "disabled";
 221         };
 222
 223         i2c4: i2c@e6520000 {
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226                 compatible = "renesas,i2c-r8a7791";
 227                 reg = <0 0xe6520000 0 0x40>;
 228                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 230                 status = "disabled";
 231         };
 232
 233         i2c5: i2c@e6528000 {
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 compatible = "renesas,i2c-r8a7791";
 237                 reg = <0 0xe6528000 0 0x40>;
 238                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 239                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 240                 status = "disabled";
 241         };
 242
 243         pfc: pfc@e6060000 {
 244                 compatible = "renesas,pfc-r8a7791";
 245                 reg = <0 0xe6060000 0 0x250>;
 246                 #gpio-range-cells = <3>;
 247         };
 248
 249         sdhi0: sd@ee100000 {
 250                 compatible = "renesas,sdhi-r8a7791";
 251                 reg = <0 0xee100000 0 0x200>;
 252                 interrupt-parent = <&gic>;
 253                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 254                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 255                 status = "disabled";
 256         };
 257
 258         sdhi1: sd@ee140000 {
 259                 compatible = "renesas,sdhi-r8a7791";
 260                 reg = <0 0xee140000 0 0x100>;
 261                 interrupt-parent = <&gic>;
 262                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 263                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 264                 status = "disabled";
 265         };
 266
 267         sdhi2: sd@ee160000 {
 268                 compatible = "renesas,sdhi-r8a7791";
 269                 reg = <0 0xee160000 0 0x100>;
 270                 interrupt-parent = <&gic>;
 271                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 272                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 273                 status = "disabled";
 274         };
 275
 276         scifa0: serial@e6c40000 {
 277                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 278                 reg = <0 0xe6c40000 0 64>;
 279                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 281                 clock-names = "sci_ick";
 282                 status = "disabled";
 283         };
 284
 285         scifa1: serial@e6c50000 {
 286                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 287                 reg = <0 0xe6c50000 0 64>;
 288                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 289                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 290                 clock-names = "sci_ick";
 291                 status = "disabled";
 292         };
 293
 294         scifa2: serial@e6c60000 {
 295                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 296                 reg = <0 0xe6c60000 0 64>;
 297                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 298                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 299                 clock-names = "sci_ick";
 300                 status = "disabled";
 301         };
 302
 303         scifa3: serial@e6c70000 {
 304                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 305                 reg = <0 0xe6c70000 0 64>;
 306                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 307                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 308                 clock-names = "sci_ick";
 309                 status = "disabled";
 310         };
 311
 312         scifa4: serial@e6c78000 {
 313                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 314                 reg = <0 0xe6c78000 0 64>;
 315                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 316                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 317                 clock-names = "sci_ick";
 318                 status = "disabled";
 319         };
 320
 321         scifa5: serial@e6c80000 {
 322                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 323                 reg = <0 0xe6c80000 0 64>;
 324                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 325                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 326                 clock-names = "sci_ick";
 327                 status = "disabled";
 328         };
 329
 330         scifb0: serial@e6c20000 {
 331                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 332                 reg = <0 0xe6c20000 0 64>;
 333                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 334                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 335                 clock-names = "sci_ick";
 336                 status = "disabled";
 337         };
 338
 339         scifb1: serial@e6c30000 {
 340                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 341                 reg = <0 0xe6c30000 0 64>;
 342                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 344                 clock-names = "sci_ick";
 345                 status = "disabled";
 346         };
 347
 348         scifb2: serial@e6ce0000 {
 349                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 350                 reg = <0 0xe6ce0000 0 64>;
 351                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 353                 clock-names = "sci_ick";
 354                 status = "disabled";
 355         };
 356
 357         scif0: serial@e6e60000 {
 358                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 359                 reg = <0 0xe6e60000 0 64>;
 360                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 361                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 362                 clock-names = "sci_ick";
 363                 status = "disabled";
 364         };
 365
 366         scif1: serial@e6e68000 {
 367                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 368                 reg = <0 0xe6e68000 0 64>;
 369                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 370                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 371                 clock-names = "sci_ick";
 372                 status = "disabled";
 373         };
 374
 375         scif2: serial@e6e58000 {
 376                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 377                 reg = <0 0xe6e58000 0 64>;
 378                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 380                 clock-names = "sci_ick";
 381                 status = "disabled";
 382         };
 383
 384         scif3: serial@e6ea8000 {
 385                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 386                 reg = <0 0xe6ea8000 0 64>;
 387                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 389                 clock-names = "sci_ick";
 390                 status = "disabled";
 391         };
 392
 393         scif4: serial@e6ee0000 {
 394                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 395                 reg = <0 0xe6ee0000 0 64>;
 396                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 397                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 398                 clock-names = "sci_ick";
 399                 status = "disabled";
 400         };
 401
 402         scif5: serial@e6ee8000 {
 403                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 404                 reg = <0 0xe6ee8000 0 64>;
 405                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 407                 clock-names = "sci_ick";
 408                 status = "disabled";
 409         };
 410
 411         hscif0: serial@e62c0000 {
 412                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 413                 reg = <0 0xe62c0000 0 96>;
 414                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 416                 clock-names = "sci_ick";
 417                 status = "disabled";
 418         };
 419
 420         hscif1: serial@e62c8000 {
 421                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 422                 reg = <0 0xe62c8000 0 96>;
 423                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 424                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 425                 clock-names = "sci_ick";
 426                 status = "disabled";
 427         };
 428
 429         hscif2: serial@e62d0000 {
 430                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 431                 reg = <0 0xe62d0000 0 96>;
 432                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 433                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 434                 clock-names = "sci_ick";
 435                 status = "disabled";
 436         };
 437
 438         ether: ethernet@ee700000 {
 439                 compatible = "renesas,ether-r8a7791";
 440                 reg = <0 0xee700000 0 0x400>;
 441                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 443                 phy-mode = "rmii";
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 status = "disabled";
 447         };
 448
 449         sata0: sata@ee300000 {
 450                 compatible = "renesas,sata-r8a7791";
 451                 reg = <0 0xee300000 0 0x2000>;
 452                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 454                 status = "disabled";
 455         };
 456
 457         sata1: sata@ee500000 {
 458                 compatible = "renesas,sata-r8a7791";
 459                 reg = <0 0xee500000 0 0x2000>;
 460                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 461                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 462                 status = "disabled";
 463         };
 464
 465         clocks {
 466                 #address-cells = <2>;
 467                 #size-cells = <2>;
 468                 ranges;
 469
 470                 /* External root clock */
 471                 extal_clk: extal_clk {
 472                         compatible = "fixed-clock";
 473                         #clock-cells = <0>;
 474                         /* This value must be overriden by the board. */
 475                         clock-frequency = <0>;
 476                         clock-output-names = "extal";
 477                 };
 478
 479                 /* Special CPG clocks */
 480                 cpg_clocks: cpg_clocks@e6150000 {
 481                         compatible = "renesas,r8a7791-cpg-clocks",
 482                                      "renesas,rcar-gen2-cpg-clocks";
 483                         reg = <0 0xe6150000 0 0x1000>;
 484                         clocks = <&extal_clk>;
 485                         #clock-cells = <1>;
 486                         clock-output-names = "main", "pll0", "pll1", "pll3",
 487                                              "lb", "qspi", "sdh", "sd0", "z";
 488                 };
 489
 490                 /* Variable factor clocks */
 491                 sd1_clk: sd2_clk@e6150078 {
 492                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 493                         reg = <0 0xe6150078 0 4>;
 494                         clocks = <&pll1_div2_clk>;
 495                         #clock-cells = <0>;
 496                         clock-output-names = "sd1";
 497                 };
 498                 sd2_clk: sd3_clk@e615007c {
 499                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 500                         reg = <0 0xe615007c 0 4>;
 501                         clocks = <&pll1_div2_clk>;
 502                         #clock-cells = <0>;
 503                         clock-output-names = "sd2";
 504                 };
 505                 mmc0_clk: mmc0_clk@e6150240 {
 506                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 507                         reg = <0 0xe6150240 0 4>;
 508                         clocks = <&pll1_div2_clk>;
 509                         #clock-cells = <0>;
 510                         clock-output-names = "mmc0";
 511                 };
 512                 ssp_clk: ssp_clk@e6150248 {
 513                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 514                         reg = <0 0xe6150248 0 4>;
 515                         clocks = <&pll1_div2_clk>;
 516                         #clock-cells = <0>;
 517                         clock-output-names = "ssp";
 518                 };
 519                 ssprs_clk: ssprs_clk@e615024c {
 520                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 521                         reg = <0 0xe615024c 0 4>;
 522                         clocks = <&pll1_div2_clk>;
 523                         #clock-cells = <0>;
 524                         clock-output-names = "ssprs";
 525                 };
 526
 527                 /* Fixed factor clocks */
 528                 pll1_div2_clk: pll1_div2_clk {
 529                         compatible = "fixed-factor-clock";
 530                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 531                         #clock-cells = <0>;
 532                         clock-div = <2>;
 533                         clock-mult = <1>;
 534                         clock-output-names = "pll1_div2";
 535                 };
 536                 zg_clk: zg_clk {
 537                         compatible = "fixed-factor-clock";
 538                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 539                         #clock-cells = <0>;
 540                         clock-div = <3>;
 541                         clock-mult = <1>;
 542                         clock-output-names = "zg";
 543                 };
 544                 zx_clk: zx_clk {
 545                         compatible = "fixed-factor-clock";
 546                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 547                         #clock-cells = <0>;
 548                         clock-div = <3>;
 549                         clock-mult = <1>;
 550                         clock-output-names = "zx";
 551                 };
 552                 zs_clk: zs_clk {
 553                         compatible = "fixed-factor-clock";
 554                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 555                         #clock-cells = <0>;
 556                         clock-div = <6>;
 557                         clock-mult = <1>;
 558                         clock-output-names = "zs";
 559                 };
 560                 hp_clk: hp_clk {
 561                         compatible = "fixed-factor-clock";
 562                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 563                         #clock-cells = <0>;
 564                         clock-div = <12>;
 565                         clock-mult = <1>;
 566                         clock-output-names = "hp";
 567                 };
 568                 i_clk: i_clk {
 569                         compatible = "fixed-factor-clock";
 570                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 571                         #clock-cells = <0>;
 572                         clock-div = <2>;
 573                         clock-mult = <1>;
 574                         clock-output-names = "i";
 575                 };
 576                 b_clk: b_clk {
 577                         compatible = "fixed-factor-clock";
 578                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 579                         #clock-cells = <0>;
 580                         clock-div = <12>;
 581                         clock-mult = <1>;
 582                         clock-output-names = "b";
 583                 };
 584                 p_clk: p_clk {
 585                         compatible = "fixed-factor-clock";
 586                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 587                         #clock-cells = <0>;
 588                         clock-div = <24>;
 589                         clock-mult = <1>;
 590                         clock-output-names = "p";
 591                 };
 592                 cl_clk: cl_clk {
 593                         compatible = "fixed-factor-clock";
 594                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 595                         #clock-cells = <0>;
 596                         clock-div = <48>;
 597                         clock-mult = <1>;
 598                         clock-output-names = "cl";
 599                 };
 600                 m2_clk: m2_clk {
 601                         compatible = "fixed-factor-clock";
 602                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 603                         #clock-cells = <0>;
 604                         clock-div = <8>;
 605                         clock-mult = <1>;
 606                         clock-output-names = "m2";
 607                 };
 608                 imp_clk: imp_clk {
 609                         compatible = "fixed-factor-clock";
 610                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 611                         #clock-cells = <0>;
 612                         clock-div = <4>;
 613                         clock-mult = <1>;
 614                         clock-output-names = "imp";
 615                 };
 616                 rclk_clk: rclk_clk {
 617                         compatible = "fixed-factor-clock";
 618                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 619                         #clock-cells = <0>;
 620                         clock-div = <(48 * 1024)>;
 621                         clock-mult = <1>;
 622                         clock-output-names = "rclk";
 623                 };
 624                 oscclk_clk: oscclk_clk {
 625                         compatible = "fixed-factor-clock";
 626                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 627                         #clock-cells = <0>;
 628                         clock-div = <(12 * 1024)>;
 629                         clock-mult = <1>;
 630                         clock-output-names = "oscclk";
 631                 };
 632                 zb3_clk: zb3_clk {
 633                         compatible = "fixed-factor-clock";
 634                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 635                         #clock-cells = <0>;
 636                         clock-div = <4>;
 637                         clock-mult = <1>;
 638                         clock-output-names = "zb3";
 639                 };
 640                 zb3d2_clk: zb3d2_clk {
 641                         compatible = "fixed-factor-clock";
 642                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 643                         #clock-cells = <0>;
 644                         clock-div = <8>;
 645                         clock-mult = <1>;
 646                         clock-output-names = "zb3d2";
 647                 };
 648                 ddr_clk: ddr_clk {
 649                         compatible = "fixed-factor-clock";
 650                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 651                         #clock-cells = <0>;
 652                         clock-div = <8>;
 653                         clock-mult = <1>;
 654                         clock-output-names = "ddr";
 655                 };
 656                 mp_clk: mp_clk {
 657                         compatible = "fixed-factor-clock";
 658                         clocks = <&pll1_div2_clk>;
 659                         #clock-cells = <0>;
 660                         clock-div = <15>;
 661                         clock-mult = <1>;
 662                         clock-output-names = "mp";
 663                 };
 664                 cp_clk: cp_clk {
 665                         compatible = "fixed-factor-clock";
 666                         clocks = <&extal_clk>;
 667                         #clock-cells = <0>;
 668                         clock-div = <2>;
 669                         clock-mult = <1>;
 670                         clock-output-names = "cp";
 671                 };
 672
 673                 /* Gate clocks */
 674                 mstp0_clks: mstp0_clks@e6150130 {
 675                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 676                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 677                         clocks = <&mp_clk>;
 678                         #clock-cells = <1>;
 679                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 680                         clock-output-names = "msiof0";
 681                 };
 682                 mstp1_clks: mstp1_clks@e6150134 {
 683                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 684                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 685                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 686                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 687                         #clock-cells = <1>;
 688                         renesas,clock-indices = <
 689                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 690                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 691                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
 692                         >;
 693                         clock-output-names =
 694                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 695                                 "vsp1-du0", "vsp1-sy";
 696                 };
 697                 mstp2_clks: mstp2_clks@e6150138 {
 698                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 699                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 700                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 701                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 702                         #clock-cells = <1>;
 703                         renesas,clock-indices = <
 704                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 705                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 706                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 707                         >;
 708                         clock-output-names =
 709                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 710                                 "scifb1", "msiof1", "scifb2";
 711                 };
 712                 mstp3_clks: mstp3_clks@e615013c {
 713                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 714                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 715                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
 716                                 <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
 717                         #clock-cells = <1>;
 718                         renesas,clock-indices = <
 719                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
 720                                 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
 721                         >;
 722                         clock-output-names =
 723                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
 724                 };
 725                 mstp5_clks: mstp5_clks@e6150144 {
 726                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 727                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 728                         clocks = <&extal_clk>, <&p_clk>;
 729                         #clock-cells = <1>;
 730                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 731                         clock-output-names = "thermal", "pwm";
 732                 };
 733                 mstp7_clks: mstp7_clks@e615014c {
 734                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 735                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 736                         clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 737                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 738                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 739                         #clock-cells = <1>;
 740                         renesas,clock-indices = <
 741                                 R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 742                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 743                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 744                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 745                                 R8A7791_CLK_LVDS0
 746                         >;
 747                         clock-output-names =
 748                                 "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 749                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 750                 };
 751                 mstp8_clks: mstp8_clks@e6150990 {
 752                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 753                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 754                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 755                                  <&zs_clk>;
 756                         #clock-cells = <1>;
 757                         renesas,clock-indices = <
 758                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 759                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 760                         >;
 761                         clock-output-names =
 762                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 763                 };
 764                 mstp9_clks: mstp9_clks@e6150994 {
 765                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 766                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 767                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
 768                                  <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 769                                  <&p_clk>;
 770                         #clock-cells = <1>;
 771                         renesas,clock-indices = <
 772                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
 773                                 R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
 774                                 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 775                         >;
 776                         clock-output-names =
 777                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
 778                                 "i2c2", "i2c1", "i2c0";
 779                 };
 780                 mstp11_clks: mstp11_clks@e615099c {
 781                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 782                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 783                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 784                         #clock-cells = <1>;
 785                         renesas,clock-indices = <
 786                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 787                         >;
 788                         clock-output-names = "scifa3", "scifa4", "scifa5";
 789                 };
 790         };
 791
 792         spi: spi@e6b10000 {
 793                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 794                 reg = <0 0xe6b10000 0 0x2c>;
 795                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 796                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 797                 num-cs = <1>;
 798                 #address-cells = <1>;
 799                 #size-cells = <0>;
 800                 status = "disabled";
 801         };
 802 };