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ARM: dts: r8a7791: use GIC_* defines
[deliverable/linux.git] / arch / arm / boot / dts / r8a7791.dtsi
1 /*
2 * Device Tree Source for the r8a7791 SoC
3 *
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #include <dt-bindings/clock/r8a7791-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16
17 / {
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
30 i2c6 = &i2c6;
31 i2c7 = &i2c7;
32 i2c8 = &i2c8;
33 spi0 = &qspi;
34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
50 clock-frequency = <1500000000>;
51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
54
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1500000 1000000>,
57 <1312500 1000000>,
58 <1125000 1000000>,
59 < 937500 1000000>,
60 < 750000 1000000>,
61 < 375000 1000000>;
62 };
63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 clock-frequency = <1500000000>;
69 };
70 };
71
72 gic: interrupt-controller@f1001000 {
73 compatible = "arm,gic-400";
74 #interrupt-cells = <3>;
75 #address-cells = <0>;
76 interrupt-controller;
77 reg = <0 0xf1001000 0 0x1000>,
78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>;
81 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
82 };
83
84 gpio0: gpio@e6050000 {
85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
86 reg = <0 0xe6050000 0 0x50>;
87 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pfc 0 0 32>;
91 #interrupt-cells = <2>;
92 interrupt-controller;
93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
94 power-domains = <&cpg_clocks>;
95 };
96
97 gpio1: gpio@e6051000 {
98 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
99 reg = <0 0xe6051000 0 0x50>;
100 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
101 #gpio-cells = <2>;
102 gpio-controller;
103 gpio-ranges = <&pfc 0 32 26>;
104 #interrupt-cells = <2>;
105 interrupt-controller;
106 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
107 power-domains = <&cpg_clocks>;
108 };
109
110 gpio2: gpio@e6052000 {
111 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
112 reg = <0 0xe6052000 0 0x50>;
113 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
114 #gpio-cells = <2>;
115 gpio-controller;
116 gpio-ranges = <&pfc 0 64 32>;
117 #interrupt-cells = <2>;
118 interrupt-controller;
119 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
120 power-domains = <&cpg_clocks>;
121 };
122
123 gpio3: gpio@e6053000 {
124 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
125 reg = <0 0xe6053000 0 0x50>;
126 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
127 #gpio-cells = <2>;
128 gpio-controller;
129 gpio-ranges = <&pfc 0 96 32>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
132 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
133 power-domains = <&cpg_clocks>;
134 };
135
136 gpio4: gpio@e6054000 {
137 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
138 reg = <0 0xe6054000 0 0x50>;
139 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
140 #gpio-cells = <2>;
141 gpio-controller;
142 gpio-ranges = <&pfc 0 128 32>;
143 #interrupt-cells = <2>;
144 interrupt-controller;
145 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
146 power-domains = <&cpg_clocks>;
147 };
148
149 gpio5: gpio@e6055000 {
150 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
151 reg = <0 0xe6055000 0 0x50>;
152 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
153 #gpio-cells = <2>;
154 gpio-controller;
155 gpio-ranges = <&pfc 0 160 32>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
158 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
159 power-domains = <&cpg_clocks>;
160 };
161
162 gpio6: gpio@e6055400 {
163 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
164 reg = <0 0xe6055400 0 0x50>;
165 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 192 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
172 power-domains = <&cpg_clocks>;
173 };
174
175 gpio7: gpio@e6055800 {
176 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
177 reg = <0 0xe6055800 0 0x50>;
178 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
179 #gpio-cells = <2>;
180 gpio-controller;
181 gpio-ranges = <&pfc 0 224 26>;
182 #interrupt-cells = <2>;
183 interrupt-controller;
184 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
185 power-domains = <&cpg_clocks>;
186 };
187
188 thermal@e61f0000 {
189 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
190 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
191 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
193 power-domains = <&cpg_clocks>;
194 };
195
196 timer {
197 compatible = "arm,armv7-timer";
198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
202 };
203
204 cmt0: timer@ffca0000 {
205 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
206 reg = <0 0xffca0000 0 0x1004>;
207 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
210 clock-names = "fck";
211 power-domains = <&cpg_clocks>;
212
213 renesas,channels-mask = <0x60>;
214
215 status = "disabled";
216 };
217
218 cmt1: timer@e6130000 {
219 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
220 reg = <0 0xe6130000 0 0x1004>;
221 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
230 clock-names = "fck";
231 power-domains = <&cpg_clocks>;
232
233 renesas,channels-mask = <0xff>;
234
235 status = "disabled";
236 };
237
238 irqc0: interrupt-controller@e61c0000 {
239 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
240 #interrupt-cells = <2>;
241 interrupt-controller;
242 reg = <0 0xe61c0000 0 0x200>;
243 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
254 power-domains = <&cpg_clocks>;
255 };
256
257 dmac0: dma-controller@e6700000 {
258 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
259 reg = <0 0xe6700000 0 0x20000>;
260 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
261 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
262 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
263 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
264 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
265 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
266 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
267 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
268 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
269 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
271 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
272 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
273 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
274 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
275 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "error",
277 "ch0", "ch1", "ch2", "ch3",
278 "ch4", "ch5", "ch6", "ch7",
279 "ch8", "ch9", "ch10", "ch11",
280 "ch12", "ch13", "ch14";
281 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
282 clock-names = "fck";
283 power-domains = <&cpg_clocks>;
284 #dma-cells = <1>;
285 dma-channels = <15>;
286 };
287
288 dmac1: dma-controller@e6720000 {
289 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
290 reg = <0 0xe6720000 0 0x20000>;
291 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
292 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
293 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
294 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
296 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
297 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
307 interrupt-names = "error",
308 "ch0", "ch1", "ch2", "ch3",
309 "ch4", "ch5", "ch6", "ch7",
310 "ch8", "ch9", "ch10", "ch11",
311 "ch12", "ch13", "ch14";
312 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
313 clock-names = "fck";
314 power-domains = <&cpg_clocks>;
315 #dma-cells = <1>;
316 dma-channels = <15>;
317 };
318
319 audma0: dma-controller@ec700000 {
320 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
321 reg = <0 0xec700000 0 0x10000>;
322 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-names = "error",
337 "ch0", "ch1", "ch2", "ch3",
338 "ch4", "ch5", "ch6", "ch7",
339 "ch8", "ch9", "ch10", "ch11",
340 "ch12";
341 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
342 clock-names = "fck";
343 power-domains = <&cpg_clocks>;
344 #dma-cells = <1>;
345 dma-channels = <13>;
346 };
347
348 audma1: dma-controller@ec720000 {
349 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
350 reg = <0 0xec720000 0 0x10000>;
351 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "error",
366 "ch0", "ch1", "ch2", "ch3",
367 "ch4", "ch5", "ch6", "ch7",
368 "ch8", "ch9", "ch10", "ch11",
369 "ch12";
370 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
371 clock-names = "fck";
372 power-domains = <&cpg_clocks>;
373 #dma-cells = <1>;
374 dma-channels = <13>;
375 };
376
377 usb_dmac0: dma-controller@e65a0000 {
378 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
379 reg = <0 0xe65a0000 0 0x100>;
380 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "ch0", "ch1";
383 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
384 power-domains = <&cpg_clocks>;
385 #dma-cells = <1>;
386 dma-channels = <2>;
387 };
388
389 usb_dmac1: dma-controller@e65b0000 {
390 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
391 reg = <0 0xe65b0000 0 0x100>;
392 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
394 interrupt-names = "ch0", "ch1";
395 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
396 power-domains = <&cpg_clocks>;
397 #dma-cells = <1>;
398 dma-channels = <2>;
399 };
400
401 /* The memory map in the User's Manual maps the cores to bus numbers */
402 i2c0: i2c@e6508000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 compatible = "renesas,i2c-r8a7791";
406 reg = <0 0xe6508000 0 0x40>;
407 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
409 power-domains = <&cpg_clocks>;
410 i2c-scl-internal-delay-ns = <6>;
411 status = "disabled";
412 };
413
414 i2c1: i2c@e6518000 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "renesas,i2c-r8a7791";
418 reg = <0 0xe6518000 0 0x40>;
419 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
421 power-domains = <&cpg_clocks>;
422 i2c-scl-internal-delay-ns = <6>;
423 status = "disabled";
424 };
425
426 i2c2: i2c@e6530000 {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 compatible = "renesas,i2c-r8a7791";
430 reg = <0 0xe6530000 0 0x40>;
431 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
433 power-domains = <&cpg_clocks>;
434 i2c-scl-internal-delay-ns = <6>;
435 status = "disabled";
436 };
437
438 i2c3: i2c@e6540000 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 compatible = "renesas,i2c-r8a7791";
442 reg = <0 0xe6540000 0 0x40>;
443 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
445 power-domains = <&cpg_clocks>;
446 i2c-scl-internal-delay-ns = <6>;
447 status = "disabled";
448 };
449
450 i2c4: i2c@e6520000 {
451 #address-cells = <1>;
452 #size-cells = <0>;
453 compatible = "renesas,i2c-r8a7791";
454 reg = <0 0xe6520000 0 0x40>;
455 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
457 power-domains = <&cpg_clocks>;
458 i2c-scl-internal-delay-ns = <6>;
459 status = "disabled";
460 };
461
462 i2c5: i2c@e6528000 {
463 /* doesn't need pinmux */
464 #address-cells = <1>;
465 #size-cells = <0>;
466 compatible = "renesas,i2c-r8a7791";
467 reg = <0 0xe6528000 0 0x40>;
468 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
470 power-domains = <&cpg_clocks>;
471 i2c-scl-internal-delay-ns = <110>;
472 status = "disabled";
473 };
474
475 i2c6: i2c@e60b0000 {
476 /* doesn't need pinmux */
477 #address-cells = <1>;
478 #size-cells = <0>;
479 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
480 reg = <0 0xe60b0000 0 0x425>;
481 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
483 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
484 dma-names = "tx", "rx";
485 power-domains = <&cpg_clocks>;
486 status = "disabled";
487 };
488
489 i2c7: i2c@e6500000 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
493 reg = <0 0xe6500000 0 0x425>;
494 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
496 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
497 dma-names = "tx", "rx";
498 power-domains = <&cpg_clocks>;
499 status = "disabled";
500 };
501
502 i2c8: i2c@e6510000 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
506 reg = <0 0xe6510000 0 0x425>;
507 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
509 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
510 dma-names = "tx", "rx";
511 power-domains = <&cpg_clocks>;
512 status = "disabled";
513 };
514
515 pfc: pfc@e6060000 {
516 compatible = "renesas,pfc-r8a7791";
517 reg = <0 0xe6060000 0 0x250>;
518 };
519
520 mmcif0: mmc@ee200000 {
521 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
522 reg = <0 0xee200000 0 0x80>;
523 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
525 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
526 dma-names = "tx", "rx";
527 power-domains = <&cpg_clocks>;
528 reg-io-width = <4>;
529 status = "disabled";
530 max-frequency = <97500000>;
531 };
532
533 sdhi0: sd@ee100000 {
534 compatible = "renesas,sdhi-r8a7791";
535 reg = <0 0xee100000 0 0x328>;
536 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
538 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
539 dma-names = "tx", "rx";
540 power-domains = <&cpg_clocks>;
541 status = "disabled";
542 };
543
544 sdhi1: sd@ee140000 {
545 compatible = "renesas,sdhi-r8a7791";
546 reg = <0 0xee140000 0 0x100>;
547 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
549 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
550 dma-names = "tx", "rx";
551 power-domains = <&cpg_clocks>;
552 status = "disabled";
553 };
554
555 sdhi2: sd@ee160000 {
556 compatible = "renesas,sdhi-r8a7791";
557 reg = <0 0xee160000 0 0x100>;
558 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
560 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
561 dma-names = "tx", "rx";
562 power-domains = <&cpg_clocks>;
563 status = "disabled";
564 };
565
566 scifa0: serial@e6c40000 {
567 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
568 reg = <0 0xe6c40000 0 64>;
569 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
571 clock-names = "sci_ick";
572 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
573 dma-names = "tx", "rx";
574 power-domains = <&cpg_clocks>;
575 status = "disabled";
576 };
577
578 scifa1: serial@e6c50000 {
579 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
580 reg = <0 0xe6c50000 0 64>;
581 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
583 clock-names = "sci_ick";
584 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
585 dma-names = "tx", "rx";
586 power-domains = <&cpg_clocks>;
587 status = "disabled";
588 };
589
590 scifa2: serial@e6c60000 {
591 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
592 reg = <0 0xe6c60000 0 64>;
593 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
595 clock-names = "sci_ick";
596 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
597 dma-names = "tx", "rx";
598 power-domains = <&cpg_clocks>;
599 status = "disabled";
600 };
601
602 scifa3: serial@e6c70000 {
603 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
604 reg = <0 0xe6c70000 0 64>;
605 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
607 clock-names = "sci_ick";
608 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
609 dma-names = "tx", "rx";
610 power-domains = <&cpg_clocks>;
611 status = "disabled";
612 };
613
614 scifa4: serial@e6c78000 {
615 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
616 reg = <0 0xe6c78000 0 64>;
617 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
619 clock-names = "sci_ick";
620 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
621 dma-names = "tx", "rx";
622 power-domains = <&cpg_clocks>;
623 status = "disabled";
624 };
625
626 scifa5: serial@e6c80000 {
627 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
628 reg = <0 0xe6c80000 0 64>;
629 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
631 clock-names = "sci_ick";
632 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
633 dma-names = "tx", "rx";
634 power-domains = <&cpg_clocks>;
635 status = "disabled";
636 };
637
638 scifb0: serial@e6c20000 {
639 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
640 reg = <0 0xe6c20000 0 64>;
641 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
643 clock-names = "sci_ick";
644 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
645 dma-names = "tx", "rx";
646 power-domains = <&cpg_clocks>;
647 status = "disabled";
648 };
649
650 scifb1: serial@e6c30000 {
651 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
652 reg = <0 0xe6c30000 0 64>;
653 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
655 clock-names = "sci_ick";
656 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
657 dma-names = "tx", "rx";
658 power-domains = <&cpg_clocks>;
659 status = "disabled";
660 };
661
662 scifb2: serial@e6ce0000 {
663 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
664 reg = <0 0xe6ce0000 0 64>;
665 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
667 clock-names = "sci_ick";
668 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
669 dma-names = "tx", "rx";
670 power-domains = <&cpg_clocks>;
671 status = "disabled";
672 };
673
674 scif0: serial@e6e60000 {
675 compatible = "renesas,scif-r8a7791", "renesas,scif";
676 reg = <0 0xe6e60000 0 64>;
677 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
679 clock-names = "sci_ick";
680 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
681 dma-names = "tx", "rx";
682 power-domains = <&cpg_clocks>;
683 status = "disabled";
684 };
685
686 scif1: serial@e6e68000 {
687 compatible = "renesas,scif-r8a7791", "renesas,scif";
688 reg = <0 0xe6e68000 0 64>;
689 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
691 clock-names = "sci_ick";
692 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
693 dma-names = "tx", "rx";
694 power-domains = <&cpg_clocks>;
695 status = "disabled";
696 };
697
698 scif2: serial@e6e58000 {
699 compatible = "renesas,scif-r8a7791", "renesas,scif";
700 reg = <0 0xe6e58000 0 64>;
701 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
703 clock-names = "sci_ick";
704 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
705 dma-names = "tx", "rx";
706 power-domains = <&cpg_clocks>;
707 status = "disabled";
708 };
709
710 scif3: serial@e6ea8000 {
711 compatible = "renesas,scif-r8a7791", "renesas,scif";
712 reg = <0 0xe6ea8000 0 64>;
713 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
715 clock-names = "sci_ick";
716 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
717 dma-names = "tx", "rx";
718 power-domains = <&cpg_clocks>;
719 status = "disabled";
720 };
721
722 scif4: serial@e6ee0000 {
723 compatible = "renesas,scif-r8a7791", "renesas,scif";
724 reg = <0 0xe6ee0000 0 64>;
725 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
727 clock-names = "sci_ick";
728 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
729 dma-names = "tx", "rx";
730 power-domains = <&cpg_clocks>;
731 status = "disabled";
732 };
733
734 scif5: serial@e6ee8000 {
735 compatible = "renesas,scif-r8a7791", "renesas,scif";
736 reg = <0 0xe6ee8000 0 64>;
737 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
739 clock-names = "sci_ick";
740 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
741 dma-names = "tx", "rx";
742 power-domains = <&cpg_clocks>;
743 status = "disabled";
744 };
745
746 hscif0: serial@e62c0000 {
747 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
748 reg = <0 0xe62c0000 0 96>;
749 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
751 clock-names = "sci_ick";
752 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
753 dma-names = "tx", "rx";
754 power-domains = <&cpg_clocks>;
755 status = "disabled";
756 };
757
758 hscif1: serial@e62c8000 {
759 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
760 reg = <0 0xe62c8000 0 96>;
761 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
763 clock-names = "sci_ick";
764 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
765 dma-names = "tx", "rx";
766 power-domains = <&cpg_clocks>;
767 status = "disabled";
768 };
769
770 hscif2: serial@e62d0000 {
771 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
772 reg = <0 0xe62d0000 0 96>;
773 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
775 clock-names = "sci_ick";
776 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
777 dma-names = "tx", "rx";
778 power-domains = <&cpg_clocks>;
779 status = "disabled";
780 };
781
782 ether: ethernet@ee700000 {
783 compatible = "renesas,ether-r8a7791";
784 reg = <0 0xee700000 0 0x400>;
785 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
787 power-domains = <&cpg_clocks>;
788 phy-mode = "rmii";
789 #address-cells = <1>;
790 #size-cells = <0>;
791 status = "disabled";
792 };
793
794 avb: ethernet@e6800000 {
795 compatible = "renesas,etheravb-r8a7791",
796 "renesas,etheravb-rcar-gen2";
797 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
798 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
800 power-domains = <&cpg_clocks>;
801 #address-cells = <1>;
802 #size-cells = <0>;
803 status = "disabled";
804 };
805
806 sata0: sata@ee300000 {
807 compatible = "renesas,sata-r8a7791";
808 reg = <0 0xee300000 0 0x2000>;
809 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
811 power-domains = <&cpg_clocks>;
812 status = "disabled";
813 };
814
815 sata1: sata@ee500000 {
816 compatible = "renesas,sata-r8a7791";
817 reg = <0 0xee500000 0 0x2000>;
818 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
820 power-domains = <&cpg_clocks>;
821 status = "disabled";
822 };
823
824 hsusb: usb@e6590000 {
825 compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
826 reg = <0 0xe6590000 0 0x100>;
827 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
829 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
830 <&usb_dmac1 0>, <&usb_dmac1 1>;
831 dma-names = "ch0", "ch1", "ch2", "ch3";
832 power-domains = <&cpg_clocks>;
833 renesas,buswait = <4>;
834 phys = <&usb0 1>;
835 phy-names = "usb";
836 status = "disabled";
837 };
838
839 usbphy: usb-phy@e6590100 {
840 compatible = "renesas,usb-phy-r8a7791";
841 reg = <0 0xe6590100 0 0x100>;
842 #address-cells = <1>;
843 #size-cells = <0>;
844 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
845 clock-names = "usbhs";
846 power-domains = <&cpg_clocks>;
847 status = "disabled";
848
849 usb0: usb-channel@0 {
850 reg = <0>;
851 #phy-cells = <1>;
852 };
853 usb2: usb-channel@2 {
854 reg = <2>;
855 #phy-cells = <1>;
856 };
857 };
858
859 vin0: video@e6ef0000 {
860 compatible = "renesas,vin-r8a7791";
861 reg = <0 0xe6ef0000 0 0x1000>;
862 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
863 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
864 power-domains = <&cpg_clocks>;
865 status = "disabled";
866 };
867
868 vin1: video@e6ef1000 {
869 compatible = "renesas,vin-r8a7791";
870 reg = <0 0xe6ef1000 0 0x1000>;
871 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
873 power-domains = <&cpg_clocks>;
874 status = "disabled";
875 };
876
877 vin2: video@e6ef2000 {
878 compatible = "renesas,vin-r8a7791";
879 reg = <0 0xe6ef2000 0 0x1000>;
880 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
882 power-domains = <&cpg_clocks>;
883 status = "disabled";
884 };
885
886 vsp1@fe928000 {
887 compatible = "renesas,vsp1";
888 reg = <0 0xfe928000 0 0x8000>;
889 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
891 power-domains = <&cpg_clocks>;
892
893 renesas,has-lut;
894 renesas,has-sru;
895 renesas,#rpf = <5>;
896 renesas,#uds = <3>;
897 renesas,#wpf = <4>;
898 };
899
900 vsp1@fe930000 {
901 compatible = "renesas,vsp1";
902 reg = <0 0xfe930000 0 0x8000>;
903 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
905 power-domains = <&cpg_clocks>;
906
907 renesas,has-lif;
908 renesas,has-lut;
909 renesas,#rpf = <4>;
910 renesas,#uds = <1>;
911 renesas,#wpf = <4>;
912 };
913
914 vsp1@fe938000 {
915 compatible = "renesas,vsp1";
916 reg = <0 0xfe938000 0 0x8000>;
917 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
919 power-domains = <&cpg_clocks>;
920
921 renesas,has-lif;
922 renesas,has-lut;
923 renesas,#rpf = <4>;
924 renesas,#uds = <1>;
925 renesas,#wpf = <4>;
926 };
927
928 du: display@feb00000 {
929 compatible = "renesas,du-r8a7791";
930 reg = <0 0xfeb00000 0 0x40000>,
931 <0 0xfeb90000 0 0x1c>;
932 reg-names = "du", "lvds.0";
933 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
936 <&mstp7_clks R8A7791_CLK_DU1>,
937 <&mstp7_clks R8A7791_CLK_LVDS0>;
938 clock-names = "du.0", "du.1", "lvds.0";
939 status = "disabled";
940
941 ports {
942 #address-cells = <1>;
943 #size-cells = <0>;
944
945 port@0 {
946 reg = <0>;
947 du_out_rgb: endpoint {
948 };
949 };
950 port@1 {
951 reg = <1>;
952 du_out_lvds0: endpoint {
953 };
954 };
955 };
956 };
957
958 can0: can@e6e80000 {
959 compatible = "renesas,can-r8a7791";
960 reg = <0 0xe6e80000 0 0x1000>;
961 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
963 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
964 clock-names = "clkp1", "clkp2", "can_clk";
965 power-domains = <&cpg_clocks>;
966 status = "disabled";
967 };
968
969 can1: can@e6e88000 {
970 compatible = "renesas,can-r8a7791";
971 reg = <0 0xe6e88000 0 0x1000>;
972 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
974 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
975 clock-names = "clkp1", "clkp2", "can_clk";
976 power-domains = <&cpg_clocks>;
977 status = "disabled";
978 };
979
980 jpu: jpeg-codec@fe980000 {
981 compatible = "renesas,jpu-r8a7791";
982 reg = <0 0xfe980000 0 0x10300>;
983 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
985 power-domains = <&cpg_clocks>;
986 };
987
988 clocks {
989 #address-cells = <2>;
990 #size-cells = <2>;
991 ranges;
992
993 /* External root clock */
994 extal_clk: extal_clk {
995 compatible = "fixed-clock";
996 #clock-cells = <0>;
997 /* This value must be overriden by the board. */
998 clock-frequency = <0>;
999 clock-output-names = "extal";
1000 };
1001
1002 /*
1003 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1004 * default. Boards that provide audio clocks should override them.
1005 */
1006 audio_clk_a: audio_clk_a {
1007 compatible = "fixed-clock";
1008 #clock-cells = <0>;
1009 clock-frequency = <0>;
1010 clock-output-names = "audio_clk_a";
1011 };
1012 audio_clk_b: audio_clk_b {
1013 compatible = "fixed-clock";
1014 #clock-cells = <0>;
1015 clock-frequency = <0>;
1016 clock-output-names = "audio_clk_b";
1017 };
1018 audio_clk_c: audio_clk_c {
1019 compatible = "fixed-clock";
1020 #clock-cells = <0>;
1021 clock-frequency = <0>;
1022 clock-output-names = "audio_clk_c";
1023 };
1024
1025 /* External PCIe clock - can be overridden by the board */
1026 pcie_bus_clk: pcie_bus_clk {
1027 compatible = "fixed-clock";
1028 #clock-cells = <0>;
1029 clock-frequency = <100000000>;
1030 clock-output-names = "pcie_bus";
1031 status = "disabled";
1032 };
1033
1034 /* External USB clock - can be overridden by the board */
1035 usb_extal_clk: usb_extal_clk {
1036 compatible = "fixed-clock";
1037 #clock-cells = <0>;
1038 clock-frequency = <48000000>;
1039 clock-output-names = "usb_extal";
1040 };
1041
1042 /* External CAN clock */
1043 can_clk: can_clk {
1044 compatible = "fixed-clock";
1045 #clock-cells = <0>;
1046 /* This value must be overridden by the board. */
1047 clock-frequency = <0>;
1048 clock-output-names = "can_clk";
1049 status = "disabled";
1050 };
1051
1052 /* Special CPG clocks */
1053 cpg_clocks: cpg_clocks@e6150000 {
1054 compatible = "renesas,r8a7791-cpg-clocks",
1055 "renesas,rcar-gen2-cpg-clocks";
1056 reg = <0 0xe6150000 0 0x1000>;
1057 clocks = <&extal_clk &usb_extal_clk>;
1058 #clock-cells = <1>;
1059 clock-output-names = "main", "pll0", "pll1", "pll3",
1060 "lb", "qspi", "sdh", "sd0", "z",
1061 "rcan", "adsp";
1062 #power-domain-cells = <0>;
1063 };
1064
1065 /* Variable factor clocks */
1066 sd2_clk: sd2_clk@e6150078 {
1067 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1068 reg = <0 0xe6150078 0 4>;
1069 clocks = <&pll1_div2_clk>;
1070 #clock-cells = <0>;
1071 clock-output-names = "sd2";
1072 };
1073 sd3_clk: sd3_clk@e615026c {
1074 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1075 reg = <0 0xe615026c 0 4>;
1076 clocks = <&pll1_div2_clk>;
1077 #clock-cells = <0>;
1078 clock-output-names = "sd3";
1079 };
1080 mmc0_clk: mmc0_clk@e6150240 {
1081 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1082 reg = <0 0xe6150240 0 4>;
1083 clocks = <&pll1_div2_clk>;
1084 #clock-cells = <0>;
1085 clock-output-names = "mmc0";
1086 };
1087 ssp_clk: ssp_clk@e6150248 {
1088 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1089 reg = <0 0xe6150248 0 4>;
1090 clocks = <&pll1_div2_clk>;
1091 #clock-cells = <0>;
1092 clock-output-names = "ssp";
1093 };
1094 ssprs_clk: ssprs_clk@e615024c {
1095 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1096 reg = <0 0xe615024c 0 4>;
1097 clocks = <&pll1_div2_clk>;
1098 #clock-cells = <0>;
1099 clock-output-names = "ssprs";
1100 };
1101
1102 /* Fixed factor clocks */
1103 pll1_div2_clk: pll1_div2_clk {
1104 compatible = "fixed-factor-clock";
1105 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1106 #clock-cells = <0>;
1107 clock-div = <2>;
1108 clock-mult = <1>;
1109 clock-output-names = "pll1_div2";
1110 };
1111 zg_clk: zg_clk {
1112 compatible = "fixed-factor-clock";
1113 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1114 #clock-cells = <0>;
1115 clock-div = <3>;
1116 clock-mult = <1>;
1117 clock-output-names = "zg";
1118 };
1119 zx_clk: zx_clk {
1120 compatible = "fixed-factor-clock";
1121 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1122 #clock-cells = <0>;
1123 clock-div = <3>;
1124 clock-mult = <1>;
1125 clock-output-names = "zx";
1126 };
1127 zs_clk: zs_clk {
1128 compatible = "fixed-factor-clock";
1129 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1130 #clock-cells = <0>;
1131 clock-div = <6>;
1132 clock-mult = <1>;
1133 clock-output-names = "zs";
1134 };
1135 hp_clk: hp_clk {
1136 compatible = "fixed-factor-clock";
1137 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1138 #clock-cells = <0>;
1139 clock-div = <12>;
1140 clock-mult = <1>;
1141 clock-output-names = "hp";
1142 };
1143 i_clk: i_clk {
1144 compatible = "fixed-factor-clock";
1145 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1146 #clock-cells = <0>;
1147 clock-div = <2>;
1148 clock-mult = <1>;
1149 clock-output-names = "i";
1150 };
1151 b_clk: b_clk {
1152 compatible = "fixed-factor-clock";
1153 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1154 #clock-cells = <0>;
1155 clock-div = <12>;
1156 clock-mult = <1>;
1157 clock-output-names = "b";
1158 };
1159 p_clk: p_clk {
1160 compatible = "fixed-factor-clock";
1161 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1162 #clock-cells = <0>;
1163 clock-div = <24>;
1164 clock-mult = <1>;
1165 clock-output-names = "p";
1166 };
1167 cl_clk: cl_clk {
1168 compatible = "fixed-factor-clock";
1169 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1170 #clock-cells = <0>;
1171 clock-div = <48>;
1172 clock-mult = <1>;
1173 clock-output-names = "cl";
1174 };
1175 m2_clk: m2_clk {
1176 compatible = "fixed-factor-clock";
1177 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1178 #clock-cells = <0>;
1179 clock-div = <8>;
1180 clock-mult = <1>;
1181 clock-output-names = "m2";
1182 };
1183 rclk_clk: rclk_clk {
1184 compatible = "fixed-factor-clock";
1185 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1186 #clock-cells = <0>;
1187 clock-div = <(48 * 1024)>;
1188 clock-mult = <1>;
1189 clock-output-names = "rclk";
1190 };
1191 oscclk_clk: oscclk_clk {
1192 compatible = "fixed-factor-clock";
1193 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1194 #clock-cells = <0>;
1195 clock-div = <(12 * 1024)>;
1196 clock-mult = <1>;
1197 clock-output-names = "oscclk";
1198 };
1199 zb3_clk: zb3_clk {
1200 compatible = "fixed-factor-clock";
1201 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1202 #clock-cells = <0>;
1203 clock-div = <4>;
1204 clock-mult = <1>;
1205 clock-output-names = "zb3";
1206 };
1207 zb3d2_clk: zb3d2_clk {
1208 compatible = "fixed-factor-clock";
1209 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1210 #clock-cells = <0>;
1211 clock-div = <8>;
1212 clock-mult = <1>;
1213 clock-output-names = "zb3d2";
1214 };
1215 ddr_clk: ddr_clk {
1216 compatible = "fixed-factor-clock";
1217 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1218 #clock-cells = <0>;
1219 clock-div = <8>;
1220 clock-mult = <1>;
1221 clock-output-names = "ddr";
1222 };
1223 mp_clk: mp_clk {
1224 compatible = "fixed-factor-clock";
1225 clocks = <&pll1_div2_clk>;
1226 #clock-cells = <0>;
1227 clock-div = <15>;
1228 clock-mult = <1>;
1229 clock-output-names = "mp";
1230 };
1231 cp_clk: cp_clk {
1232 compatible = "fixed-factor-clock";
1233 clocks = <&extal_clk>;
1234 #clock-cells = <0>;
1235 clock-div = <2>;
1236 clock-mult = <1>;
1237 clock-output-names = "cp";
1238 };
1239
1240 /* Gate clocks */
1241 mstp0_clks: mstp0_clks@e6150130 {
1242 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1243 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1244 clocks = <&mp_clk>;
1245 #clock-cells = <1>;
1246 clock-indices = <R8A7791_CLK_MSIOF0>;
1247 clock-output-names = "msiof0";
1248 };
1249 mstp1_clks: mstp1_clks@e6150134 {
1250 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1251 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1252 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1253 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1254 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1255 <&zs_clk>;
1256 #clock-cells = <1>;
1257 clock-indices = <
1258 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1259 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1260 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1261 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1262 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1263 R8A7791_CLK_VSP1_S
1264 >;
1265 clock-output-names =
1266 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1267 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1268 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1269 };
1270 mstp2_clks: mstp2_clks@e6150138 {
1271 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1272 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1273 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1274 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1275 <&zs_clk>, <&zs_clk>;
1276 #clock-cells = <1>;
1277 clock-indices = <
1278 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1279 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1280 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1281 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1282 >;
1283 clock-output-names =
1284 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1285 "scifb1", "msiof1", "scifb2",
1286 "sys-dmac1", "sys-dmac0";
1287 };
1288 mstp3_clks: mstp3_clks@e615013c {
1289 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1290 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1291 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1292 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1293 <&hp_clk>, <&hp_clk>;
1294 #clock-cells = <1>;
1295 clock-indices = <
1296 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1297 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1298 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1299 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1300 >;
1301 clock-output-names =
1302 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1303 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1304 "usbdmac0", "usbdmac1";
1305 };
1306 mstp4_clks: mstp4_clks@e6150140 {
1307 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1308 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1309 clocks = <&cp_clk>;
1310 #clock-cells = <1>;
1311 clock-indices = <R8A7791_CLK_IRQC>;
1312 clock-output-names = "irqc";
1313 };
1314 mstp5_clks: mstp5_clks@e6150144 {
1315 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1316 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1317 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1318 <&extal_clk>, <&p_clk>;
1319 #clock-cells = <1>;
1320 clock-indices = <
1321 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1322 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1323 R8A7791_CLK_PWM
1324 >;
1325 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1326 "thermal", "pwm";
1327 };
1328 mstp7_clks: mstp7_clks@e615014c {
1329 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1330 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1331 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1332 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1333 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1334 #clock-cells = <1>;
1335 clock-indices = <
1336 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1337 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1338 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1339 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1340 R8A7791_CLK_LVDS0
1341 >;
1342 clock-output-names =
1343 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1344 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1345 };
1346 mstp8_clks: mstp8_clks@e6150990 {
1347 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1348 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1349 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1350 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1351 <&zs_clk>;
1352 #clock-cells = <1>;
1353 clock-indices = <
1354 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1355 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1356 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
1357 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1358 >;
1359 clock-output-names =
1360 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
1361 "etheravb", "ether", "sata1", "sata0";
1362 };
1363 mstp9_clks: mstp9_clks@e6150994 {
1364 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1365 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1366 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1367 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1368 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1369 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1370 <&hp_clk>, <&hp_clk>;
1371 #clock-cells = <1>;
1372 clock-indices = <
1373 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1374 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1375 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1376 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1377 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1378 >;
1379 clock-output-names =
1380 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1381 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1382 "i2c1", "i2c0";
1383 };
1384 mstp10_clks: mstp10_clks@e6150998 {
1385 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1386 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1387 clocks = <&p_clk>,
1388 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1389 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1390 <&p_clk>,
1391 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1392 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1393 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1394 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1395 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1396 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1397 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1398
1399 #clock-cells = <1>;
1400 clock-indices = <
1401 R8A7791_CLK_SSI_ALL
1402 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1403 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1404 R8A7791_CLK_SCU_ALL
1405 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1406 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
1407 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1408 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1409 >;
1410 clock-output-names =
1411 "ssi-all",
1412 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1413 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1414 "scu-all",
1415 "scu-dvc1", "scu-dvc0",
1416 "scu-ctu1-mix1", "scu-ctu0-mix0",
1417 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1418 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1419 };
1420 mstp11_clks: mstp11_clks@e615099c {
1421 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1422 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1423 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1424 #clock-cells = <1>;
1425 clock-indices = <
1426 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1427 >;
1428 clock-output-names = "scifa3", "scifa4", "scifa5";
1429 };
1430 };
1431
1432 qspi: spi@e6b10000 {
1433 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1434 reg = <0 0xe6b10000 0 0x2c>;
1435 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1436 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1437 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1438 dma-names = "tx", "rx";
1439 power-domains = <&cpg_clocks>;
1440 num-cs = <1>;
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1443 status = "disabled";
1444 };
1445
1446 msiof0: spi@e6e20000 {
1447 compatible = "renesas,msiof-r8a7791";
1448 reg = <0 0xe6e20000 0 0x0064>;
1449 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1450 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1451 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1452 dma-names = "tx", "rx";
1453 power-domains = <&cpg_clocks>;
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1456 status = "disabled";
1457 };
1458
1459 msiof1: spi@e6e10000 {
1460 compatible = "renesas,msiof-r8a7791";
1461 reg = <0 0xe6e10000 0 0x0064>;
1462 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1463 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1464 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1465 dma-names = "tx", "rx";
1466 power-domains = <&cpg_clocks>;
1467 #address-cells = <1>;
1468 #size-cells = <0>;
1469 status = "disabled";
1470 };
1471
1472 msiof2: spi@e6e00000 {
1473 compatible = "renesas,msiof-r8a7791";
1474 reg = <0 0xe6e00000 0 0x0064>;
1475 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1476 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1477 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1478 dma-names = "tx", "rx";
1479 power-domains = <&cpg_clocks>;
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1482 status = "disabled";
1483 };
1484
1485 xhci: usb@ee000000 {
1486 compatible = "renesas,xhci-r8a7791";
1487 reg = <0 0xee000000 0 0xc00>;
1488 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1489 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1490 power-domains = <&cpg_clocks>;
1491 phys = <&usb2 1>;
1492 phy-names = "usb";
1493 status = "disabled";
1494 };
1495
1496 pci0: pci@ee090000 {
1497 compatible = "renesas,pci-r8a7791";
1498 device_type = "pci";
1499 reg = <0 0xee090000 0 0xc00>,
1500 <0 0xee080000 0 0x1100>;
1501 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1503 power-domains = <&cpg_clocks>;
1504 status = "disabled";
1505
1506 bus-range = <0 0>;
1507 #address-cells = <3>;
1508 #size-cells = <2>;
1509 #interrupt-cells = <1>;
1510 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1511 interrupt-map-mask = <0xff00 0 0 0x7>;
1512 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1513 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1514 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1515
1516 usb@0,1 {
1517 reg = <0x800 0 0 0 0>;
1518 device_type = "pci";
1519 phys = <&usb0 0>;
1520 phy-names = "usb";
1521 };
1522
1523 usb@0,2 {
1524 reg = <0x1000 0 0 0 0>;
1525 device_type = "pci";
1526 phys = <&usb0 0>;
1527 phy-names = "usb";
1528 };
1529 };
1530
1531 pci1: pci@ee0d0000 {
1532 compatible = "renesas,pci-r8a7791";
1533 device_type = "pci";
1534 reg = <0 0xee0d0000 0 0xc00>,
1535 <0 0xee0c0000 0 0x1100>;
1536 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1538 power-domains = <&cpg_clocks>;
1539 status = "disabled";
1540
1541 bus-range = <1 1>;
1542 #address-cells = <3>;
1543 #size-cells = <2>;
1544 #interrupt-cells = <1>;
1545 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1546 interrupt-map-mask = <0xff00 0 0 0x7>;
1547 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1548 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1549 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1550
1551 usb@0,1 {
1552 reg = <0x800 0 0 0 0>;
1553 device_type = "pci";
1554 phys = <&usb2 0>;
1555 phy-names = "usb";
1556 };
1557
1558 usb@0,2 {
1559 reg = <0x1000 0 0 0 0>;
1560 device_type = "pci";
1561 phys = <&usb2 0>;
1562 phy-names = "usb";
1563 };
1564 };
1565
1566 pciec: pcie@fe000000 {
1567 compatible = "renesas,pcie-r8a7791";
1568 reg = <0 0xfe000000 0 0x80000>;
1569 #address-cells = <3>;
1570 #size-cells = <2>;
1571 bus-range = <0x00 0xff>;
1572 device_type = "pci";
1573 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1574 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1575 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1576 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1577 /* Map all possible DDR as inbound ranges */
1578 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1579 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1580 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1582 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1583 #interrupt-cells = <1>;
1584 interrupt-map-mask = <0 0 0 0>;
1585 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1586 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1587 clock-names = "pcie", "pcie_bus";
1588 power-domains = <&cpg_clocks>;
1589 status = "disabled";
1590 };
1591
1592 ipmmu_sy0: mmu@e6280000 {
1593 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1594 reg = <0 0xe6280000 0 0x1000>;
1595 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1596 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1597 #iommu-cells = <1>;
1598 status = "disabled";
1599 };
1600
1601 ipmmu_sy1: mmu@e6290000 {
1602 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1603 reg = <0 0xe6290000 0 0x1000>;
1604 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1605 #iommu-cells = <1>;
1606 status = "disabled";
1607 };
1608
1609 ipmmu_ds: mmu@e6740000 {
1610 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1611 reg = <0 0xe6740000 0 0x1000>;
1612 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1613 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1614 #iommu-cells = <1>;
1615 status = "disabled";
1616 };
1617
1618 ipmmu_mp: mmu@ec680000 {
1619 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1620 reg = <0 0xec680000 0 0x1000>;
1621 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1622 #iommu-cells = <1>;
1623 status = "disabled";
1624 };
1625
1626 ipmmu_mx: mmu@fe951000 {
1627 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1628 reg = <0 0xfe951000 0 0x1000>;
1629 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1630 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1631 #iommu-cells = <1>;
1632 status = "disabled";
1633 };
1634
1635 ipmmu_rt: mmu@ffc80000 {
1636 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1637 reg = <0 0xffc80000 0 0x1000>;
1638 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1639 #iommu-cells = <1>;
1640 status = "disabled";
1641 };
1642
1643 ipmmu_gp: mmu@e62a0000 {
1644 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1645 reg = <0 0xe62a0000 0 0x1000>;
1646 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1647 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1648 #iommu-cells = <1>;
1649 status = "disabled";
1650 };
1651
1652 rcar_sound: sound@ec500000 {
1653 /*
1654 * #sound-dai-cells is required
1655 *
1656 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1657 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1658 */
1659 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1660 reg = <0 0xec500000 0 0x1000>, /* SCU */
1661 <0 0xec5a0000 0 0x100>, /* ADG */
1662 <0 0xec540000 0 0x1000>, /* SSIU */
1663 <0 0xec541000 0 0x280>, /* SSI */
1664 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1665 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1666
1667 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1668 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1669 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1670 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1671 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1672 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1673 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1674 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1675 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1676 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1677 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1678 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1679 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1680 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1681 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1682 clock-names = "ssi-all",
1683 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1684 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1685 "src.9", "src.8", "src.7", "src.6", "src.5",
1686 "src.4", "src.3", "src.2", "src.1", "src.0",
1687 "ctu.0", "ctu.1",
1688 "mix.0", "mix.1",
1689 "dvc.0", "dvc.1",
1690 "clk_a", "clk_b", "clk_c", "clk_i";
1691 power-domains = <&cpg_clocks>;
1692
1693 status = "disabled";
1694
1695 rcar_sound,dvc {
1696 dvc0: dvc@0 {
1697 dmas = <&audma0 0xbc>;
1698 dma-names = "tx";
1699 };
1700 dvc1: dvc@1 {
1701 dmas = <&audma0 0xbe>;
1702 dma-names = "tx";
1703 };
1704 };
1705
1706 rcar_sound,mix {
1707 mix0: mix@0 { };
1708 mix1: mix@1 { };
1709 };
1710
1711 rcar_sound,ctu {
1712 ctu00: ctu@0 { };
1713 ctu01: ctu@1 { };
1714 ctu02: ctu@2 { };
1715 ctu03: ctu@3 { };
1716 ctu10: ctu@4 { };
1717 ctu11: ctu@5 { };
1718 ctu12: ctu@6 { };
1719 ctu13: ctu@7 { };
1720 };
1721
1722 rcar_sound,src {
1723 src0: src@0 {
1724 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1725 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1726 dma-names = "rx", "tx";
1727 };
1728 src1: src@1 {
1729 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1730 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1731 dma-names = "rx", "tx";
1732 };
1733 src2: src@2 {
1734 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1735 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1736 dma-names = "rx", "tx";
1737 };
1738 src3: src@3 {
1739 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1740 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1741 dma-names = "rx", "tx";
1742 };
1743 src4: src@4 {
1744 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1745 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1746 dma-names = "rx", "tx";
1747 };
1748 src5: src@5 {
1749 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1750 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1751 dma-names = "rx", "tx";
1752 };
1753 src6: src@6 {
1754 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1755 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1756 dma-names = "rx", "tx";
1757 };
1758 src7: src@7 {
1759 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1760 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1761 dma-names = "rx", "tx";
1762 };
1763 src8: src@8 {
1764 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1765 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1766 dma-names = "rx", "tx";
1767 };
1768 src9: src@9 {
1769 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1770 dmas = <&audma0 0x97>, <&audma1 0xba>;
1771 dma-names = "rx", "tx";
1772 };
1773 };
1774
1775 rcar_sound,ssi {
1776 ssi0: ssi@0 {
1777 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1778 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1779 dma-names = "rx", "tx", "rxu", "txu";
1780 };
1781 ssi1: ssi@1 {
1782 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1783 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1784 dma-names = "rx", "tx", "rxu", "txu";
1785 };
1786 ssi2: ssi@2 {
1787 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1788 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1789 dma-names = "rx", "tx", "rxu", "txu";
1790 };
1791 ssi3: ssi@3 {
1792 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1793 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1794 dma-names = "rx", "tx", "rxu", "txu";
1795 };
1796 ssi4: ssi@4 {
1797 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1798 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1799 dma-names = "rx", "tx", "rxu", "txu";
1800 };
1801 ssi5: ssi@5 {
1802 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1803 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1804 dma-names = "rx", "tx", "rxu", "txu";
1805 };
1806 ssi6: ssi@6 {
1807 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1808 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1809 dma-names = "rx", "tx", "rxu", "txu";
1810 };
1811 ssi7: ssi@7 {
1812 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1813 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1814 dma-names = "rx", "tx", "rxu", "txu";
1815 };
1816 ssi8: ssi@8 {
1817 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1818 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1819 dma-names = "rx", "tx", "rxu", "txu";
1820 };
1821 ssi9: ssi@9 {
1822 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1823 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1824 dma-names = "rx", "tx", "rxu", "txu";
1825 };
1826 };
1827 };
1828 };
Linux kernel - Deliverables
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