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ARM: shmobile: r8a7791: add EtherAVB DT support
[deliverable/linux.git] / arch / arm / boot / dts / r8a7791.dtsi
1 /*
2 * Device Tree Source for the r8a7791 SoC
3 *
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #include <dt-bindings/clock/r8a7791-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16
17 / {
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
30 i2c6 = &i2c6;
31 i2c7 = &i2c7;
32 i2c8 = &i2c8;
33 spi0 = &qspi;
34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
50 clock-frequency = <1500000000>;
51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
54
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1500000 1000000>,
57 <1312500 1000000>,
58 <1125000 1000000>,
59 < 937500 1000000>,
60 < 750000 1000000>,
61 < 375000 1000000>;
62 };
63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 clock-frequency = <1500000000>;
69 };
70 };
71
72 gic: interrupt-controller@f1001000 {
73 compatible = "arm,gic-400";
74 #interrupt-cells = <3>;
75 #address-cells = <0>;
76 interrupt-controller;
77 reg = <0 0xf1001000 0 0x1000>,
78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>;
81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
82 };
83
84 gpio0: gpio@e6050000 {
85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
86 reg = <0 0xe6050000 0 0x50>;
87 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pfc 0 0 32>;
91 #interrupt-cells = <2>;
92 interrupt-controller;
93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
94 power-domains = <&cpg_clocks>;
95 };
96
97 gpio1: gpio@e6051000 {
98 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
99 reg = <0 0xe6051000 0 0x50>;
100 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
101 #gpio-cells = <2>;
102 gpio-controller;
103 gpio-ranges = <&pfc 0 32 26>;
104 #interrupt-cells = <2>;
105 interrupt-controller;
106 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
107 power-domains = <&cpg_clocks>;
108 };
109
110 gpio2: gpio@e6052000 {
111 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
112 reg = <0 0xe6052000 0 0x50>;
113 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
114 #gpio-cells = <2>;
115 gpio-controller;
116 gpio-ranges = <&pfc 0 64 32>;
117 #interrupt-cells = <2>;
118 interrupt-controller;
119 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
120 power-domains = <&cpg_clocks>;
121 };
122
123 gpio3: gpio@e6053000 {
124 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
125 reg = <0 0xe6053000 0 0x50>;
126 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
127 #gpio-cells = <2>;
128 gpio-controller;
129 gpio-ranges = <&pfc 0 96 32>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
132 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
133 power-domains = <&cpg_clocks>;
134 };
135
136 gpio4: gpio@e6054000 {
137 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
138 reg = <0 0xe6054000 0 0x50>;
139 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
140 #gpio-cells = <2>;
141 gpio-controller;
142 gpio-ranges = <&pfc 0 128 32>;
143 #interrupt-cells = <2>;
144 interrupt-controller;
145 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
146 power-domains = <&cpg_clocks>;
147 };
148
149 gpio5: gpio@e6055000 {
150 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
151 reg = <0 0xe6055000 0 0x50>;
152 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
153 #gpio-cells = <2>;
154 gpio-controller;
155 gpio-ranges = <&pfc 0 160 32>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
158 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
159 power-domains = <&cpg_clocks>;
160 };
161
162 gpio6: gpio@e6055400 {
163 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
164 reg = <0 0xe6055400 0 0x50>;
165 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 192 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
172 power-domains = <&cpg_clocks>;
173 };
174
175 gpio7: gpio@e6055800 {
176 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
177 reg = <0 0xe6055800 0 0x50>;
178 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
179 #gpio-cells = <2>;
180 gpio-controller;
181 gpio-ranges = <&pfc 0 224 26>;
182 #interrupt-cells = <2>;
183 interrupt-controller;
184 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
185 power-domains = <&cpg_clocks>;
186 };
187
188 thermal@e61f0000 {
189 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
190 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
191 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
193 power-domains = <&cpg_clocks>;
194 };
195
196 timer {
197 compatible = "arm,armv7-timer";
198 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
199 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
200 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
201 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
202 };
203
204 cmt0: timer@ffca0000 {
205 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
206 reg = <0 0xffca0000 0 0x1004>;
207 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
208 <0 143 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
210 clock-names = "fck";
211 power-domains = <&cpg_clocks>;
212
213 renesas,channels-mask = <0x60>;
214
215 status = "disabled";
216 };
217
218 cmt1: timer@e6130000 {
219 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
220 reg = <0 0xe6130000 0 0x1004>;
221 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
222 <0 121 IRQ_TYPE_LEVEL_HIGH>,
223 <0 122 IRQ_TYPE_LEVEL_HIGH>,
224 <0 123 IRQ_TYPE_LEVEL_HIGH>,
225 <0 124 IRQ_TYPE_LEVEL_HIGH>,
226 <0 125 IRQ_TYPE_LEVEL_HIGH>,
227 <0 126 IRQ_TYPE_LEVEL_HIGH>,
228 <0 127 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
230 clock-names = "fck";
231 power-domains = <&cpg_clocks>;
232
233 renesas,channels-mask = <0xff>;
234
235 status = "disabled";
236 };
237
238 irqc0: interrupt-controller@e61c0000 {
239 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
240 #interrupt-cells = <2>;
241 interrupt-controller;
242 reg = <0 0xe61c0000 0 0x200>;
243 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
244 <0 1 IRQ_TYPE_LEVEL_HIGH>,
245 <0 2 IRQ_TYPE_LEVEL_HIGH>,
246 <0 3 IRQ_TYPE_LEVEL_HIGH>,
247 <0 12 IRQ_TYPE_LEVEL_HIGH>,
248 <0 13 IRQ_TYPE_LEVEL_HIGH>,
249 <0 14 IRQ_TYPE_LEVEL_HIGH>,
250 <0 15 IRQ_TYPE_LEVEL_HIGH>,
251 <0 16 IRQ_TYPE_LEVEL_HIGH>,
252 <0 17 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
254 power-domains = <&cpg_clocks>;
255 };
256
257 dmac0: dma-controller@e6700000 {
258 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
259 reg = <0 0xe6700000 0 0x20000>;
260 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
261 0 200 IRQ_TYPE_LEVEL_HIGH
262 0 201 IRQ_TYPE_LEVEL_HIGH
263 0 202 IRQ_TYPE_LEVEL_HIGH
264 0 203 IRQ_TYPE_LEVEL_HIGH
265 0 204 IRQ_TYPE_LEVEL_HIGH
266 0 205 IRQ_TYPE_LEVEL_HIGH
267 0 206 IRQ_TYPE_LEVEL_HIGH
268 0 207 IRQ_TYPE_LEVEL_HIGH
269 0 208 IRQ_TYPE_LEVEL_HIGH
270 0 209 IRQ_TYPE_LEVEL_HIGH
271 0 210 IRQ_TYPE_LEVEL_HIGH
272 0 211 IRQ_TYPE_LEVEL_HIGH
273 0 212 IRQ_TYPE_LEVEL_HIGH
274 0 213 IRQ_TYPE_LEVEL_HIGH
275 0 214 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "error",
277 "ch0", "ch1", "ch2", "ch3",
278 "ch4", "ch5", "ch6", "ch7",
279 "ch8", "ch9", "ch10", "ch11",
280 "ch12", "ch13", "ch14";
281 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
282 clock-names = "fck";
283 power-domains = <&cpg_clocks>;
284 #dma-cells = <1>;
285 dma-channels = <15>;
286 };
287
288 dmac1: dma-controller@e6720000 {
289 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
290 reg = <0 0xe6720000 0 0x20000>;
291 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
292 0 216 IRQ_TYPE_LEVEL_HIGH
293 0 217 IRQ_TYPE_LEVEL_HIGH
294 0 218 IRQ_TYPE_LEVEL_HIGH
295 0 219 IRQ_TYPE_LEVEL_HIGH
296 0 308 IRQ_TYPE_LEVEL_HIGH
297 0 309 IRQ_TYPE_LEVEL_HIGH
298 0 310 IRQ_TYPE_LEVEL_HIGH
299 0 311 IRQ_TYPE_LEVEL_HIGH
300 0 312 IRQ_TYPE_LEVEL_HIGH
301 0 313 IRQ_TYPE_LEVEL_HIGH
302 0 314 IRQ_TYPE_LEVEL_HIGH
303 0 315 IRQ_TYPE_LEVEL_HIGH
304 0 316 IRQ_TYPE_LEVEL_HIGH
305 0 317 IRQ_TYPE_LEVEL_HIGH
306 0 318 IRQ_TYPE_LEVEL_HIGH>;
307 interrupt-names = "error",
308 "ch0", "ch1", "ch2", "ch3",
309 "ch4", "ch5", "ch6", "ch7",
310 "ch8", "ch9", "ch10", "ch11",
311 "ch12", "ch13", "ch14";
312 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
313 clock-names = "fck";
314 power-domains = <&cpg_clocks>;
315 #dma-cells = <1>;
316 dma-channels = <15>;
317 };
318
319 audma0: dma-controller@ec700000 {
320 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
321 reg = <0 0xec700000 0 0x10000>;
322 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
323 0 320 IRQ_TYPE_LEVEL_HIGH
324 0 321 IRQ_TYPE_LEVEL_HIGH
325 0 322 IRQ_TYPE_LEVEL_HIGH
326 0 323 IRQ_TYPE_LEVEL_HIGH
327 0 324 IRQ_TYPE_LEVEL_HIGH
328 0 325 IRQ_TYPE_LEVEL_HIGH
329 0 326 IRQ_TYPE_LEVEL_HIGH
330 0 327 IRQ_TYPE_LEVEL_HIGH
331 0 328 IRQ_TYPE_LEVEL_HIGH
332 0 329 IRQ_TYPE_LEVEL_HIGH
333 0 330 IRQ_TYPE_LEVEL_HIGH
334 0 331 IRQ_TYPE_LEVEL_HIGH
335 0 332 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-names = "error",
337 "ch0", "ch1", "ch2", "ch3",
338 "ch4", "ch5", "ch6", "ch7",
339 "ch8", "ch9", "ch10", "ch11",
340 "ch12";
341 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
342 clock-names = "fck";
343 power-domains = <&cpg_clocks>;
344 #dma-cells = <1>;
345 dma-channels = <13>;
346 };
347
348 audma1: dma-controller@ec720000 {
349 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
350 reg = <0 0xec720000 0 0x10000>;
351 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
352 0 333 IRQ_TYPE_LEVEL_HIGH
353 0 334 IRQ_TYPE_LEVEL_HIGH
354 0 335 IRQ_TYPE_LEVEL_HIGH
355 0 336 IRQ_TYPE_LEVEL_HIGH
356 0 337 IRQ_TYPE_LEVEL_HIGH
357 0 338 IRQ_TYPE_LEVEL_HIGH
358 0 339 IRQ_TYPE_LEVEL_HIGH
359 0 340 IRQ_TYPE_LEVEL_HIGH
360 0 341 IRQ_TYPE_LEVEL_HIGH
361 0 342 IRQ_TYPE_LEVEL_HIGH
362 0 343 IRQ_TYPE_LEVEL_HIGH
363 0 344 IRQ_TYPE_LEVEL_HIGH
364 0 345 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "error",
366 "ch0", "ch1", "ch2", "ch3",
367 "ch4", "ch5", "ch6", "ch7",
368 "ch8", "ch9", "ch10", "ch11",
369 "ch12";
370 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
371 clock-names = "fck";
372 power-domains = <&cpg_clocks>;
373 #dma-cells = <1>;
374 dma-channels = <13>;
375 };
376
377 usb_dmac0: dma-controller@e65a0000 {
378 compatible = "renesas,usb-dmac";
379 reg = <0 0xe65a0000 0 0x100>;
380 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
381 0 109 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "ch0", "ch1";
383 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
384 power-domains = <&cpg_clocks>;
385 #dma-cells = <1>;
386 dma-channels = <2>;
387 };
388
389 usb_dmac1: dma-controller@e65b0000 {
390 compatible = "renesas,usb-dmac";
391 reg = <0 0xe65b0000 0 0x100>;
392 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
393 0 110 IRQ_TYPE_LEVEL_HIGH>;
394 interrupt-names = "ch0", "ch1";
395 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
396 power-domains = <&cpg_clocks>;
397 #dma-cells = <1>;
398 dma-channels = <2>;
399 };
400
401 /* The memory map in the User's Manual maps the cores to bus numbers */
402 i2c0: i2c@e6508000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 compatible = "renesas,i2c-r8a7791";
406 reg = <0 0xe6508000 0 0x40>;
407 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
409 power-domains = <&cpg_clocks>;
410 status = "disabled";
411 };
412
413 i2c1: i2c@e6518000 {
414 #address-cells = <1>;
415 #size-cells = <0>;
416 compatible = "renesas,i2c-r8a7791";
417 reg = <0 0xe6518000 0 0x40>;
418 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
420 power-domains = <&cpg_clocks>;
421 status = "disabled";
422 };
423
424 i2c2: i2c@e6530000 {
425 #address-cells = <1>;
426 #size-cells = <0>;
427 compatible = "renesas,i2c-r8a7791";
428 reg = <0 0xe6530000 0 0x40>;
429 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
431 power-domains = <&cpg_clocks>;
432 status = "disabled";
433 };
434
435 i2c3: i2c@e6540000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "renesas,i2c-r8a7791";
439 reg = <0 0xe6540000 0 0x40>;
440 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
442 power-domains = <&cpg_clocks>;
443 status = "disabled";
444 };
445
446 i2c4: i2c@e6520000 {
447 #address-cells = <1>;
448 #size-cells = <0>;
449 compatible = "renesas,i2c-r8a7791";
450 reg = <0 0xe6520000 0 0x40>;
451 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
453 power-domains = <&cpg_clocks>;
454 status = "disabled";
455 };
456
457 i2c5: i2c@e6528000 {
458 /* doesn't need pinmux */
459 #address-cells = <1>;
460 #size-cells = <0>;
461 compatible = "renesas,i2c-r8a7791";
462 reg = <0 0xe6528000 0 0x40>;
463 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
465 power-domains = <&cpg_clocks>;
466 status = "disabled";
467 };
468
469 i2c6: i2c@e60b0000 {
470 /* doesn't need pinmux */
471 #address-cells = <1>;
472 #size-cells = <0>;
473 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
474 reg = <0 0xe60b0000 0 0x425>;
475 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
477 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
478 dma-names = "tx", "rx";
479 power-domains = <&cpg_clocks>;
480 status = "disabled";
481 };
482
483 i2c7: i2c@e6500000 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
487 reg = <0 0xe6500000 0 0x425>;
488 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
490 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
491 dma-names = "tx", "rx";
492 power-domains = <&cpg_clocks>;
493 status = "disabled";
494 };
495
496 i2c8: i2c@e6510000 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
500 reg = <0 0xe6510000 0 0x425>;
501 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
503 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
504 dma-names = "tx", "rx";
505 power-domains = <&cpg_clocks>;
506 status = "disabled";
507 };
508
509 pfc: pfc@e6060000 {
510 compatible = "renesas,pfc-r8a7791";
511 reg = <0 0xe6060000 0 0x250>;
512 };
513
514 mmcif0: mmc@ee200000 {
515 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
516 reg = <0 0xee200000 0 0x80>;
517 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
519 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
520 dma-names = "tx", "rx";
521 power-domains = <&cpg_clocks>;
522 reg-io-width = <4>;
523 status = "disabled";
524 max-frequency = <97500000>;
525 };
526
527 sdhi0: sd@ee100000 {
528 compatible = "renesas,sdhi-r8a7791";
529 reg = <0 0xee100000 0 0x328>;
530 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
532 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
533 dma-names = "tx", "rx";
534 power-domains = <&cpg_clocks>;
535 status = "disabled";
536 };
537
538 sdhi1: sd@ee140000 {
539 compatible = "renesas,sdhi-r8a7791";
540 reg = <0 0xee140000 0 0x100>;
541 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
543 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
544 dma-names = "tx", "rx";
545 power-domains = <&cpg_clocks>;
546 status = "disabled";
547 };
548
549 sdhi2: sd@ee160000 {
550 compatible = "renesas,sdhi-r8a7791";
551 reg = <0 0xee160000 0 0x100>;
552 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
554 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
555 dma-names = "tx", "rx";
556 power-domains = <&cpg_clocks>;
557 status = "disabled";
558 };
559
560 scifa0: serial@e6c40000 {
561 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
562 reg = <0 0xe6c40000 0 64>;
563 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
565 clock-names = "sci_ick";
566 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
567 dma-names = "tx", "rx";
568 power-domains = <&cpg_clocks>;
569 status = "disabled";
570 };
571
572 scifa1: serial@e6c50000 {
573 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
574 reg = <0 0xe6c50000 0 64>;
575 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
577 clock-names = "sci_ick";
578 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
579 dma-names = "tx", "rx";
580 power-domains = <&cpg_clocks>;
581 status = "disabled";
582 };
583
584 scifa2: serial@e6c60000 {
585 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
586 reg = <0 0xe6c60000 0 64>;
587 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
589 clock-names = "sci_ick";
590 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
591 dma-names = "tx", "rx";
592 power-domains = <&cpg_clocks>;
593 status = "disabled";
594 };
595
596 scifa3: serial@e6c70000 {
597 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
598 reg = <0 0xe6c70000 0 64>;
599 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
601 clock-names = "sci_ick";
602 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
603 dma-names = "tx", "rx";
604 power-domains = <&cpg_clocks>;
605 status = "disabled";
606 };
607
608 scifa4: serial@e6c78000 {
609 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
610 reg = <0 0xe6c78000 0 64>;
611 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
613 clock-names = "sci_ick";
614 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
615 dma-names = "tx", "rx";
616 power-domains = <&cpg_clocks>;
617 status = "disabled";
618 };
619
620 scifa5: serial@e6c80000 {
621 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
622 reg = <0 0xe6c80000 0 64>;
623 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
625 clock-names = "sci_ick";
626 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
627 dma-names = "tx", "rx";
628 power-domains = <&cpg_clocks>;
629 status = "disabled";
630 };
631
632 scifb0: serial@e6c20000 {
633 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
634 reg = <0 0xe6c20000 0 64>;
635 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
637 clock-names = "sci_ick";
638 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
639 dma-names = "tx", "rx";
640 power-domains = <&cpg_clocks>;
641 status = "disabled";
642 };
643
644 scifb1: serial@e6c30000 {
645 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
646 reg = <0 0xe6c30000 0 64>;
647 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
649 clock-names = "sci_ick";
650 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
651 dma-names = "tx", "rx";
652 power-domains = <&cpg_clocks>;
653 status = "disabled";
654 };
655
656 scifb2: serial@e6ce0000 {
657 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
658 reg = <0 0xe6ce0000 0 64>;
659 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
661 clock-names = "sci_ick";
662 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
663 dma-names = "tx", "rx";
664 power-domains = <&cpg_clocks>;
665 status = "disabled";
666 };
667
668 scif0: serial@e6e60000 {
669 compatible = "renesas,scif-r8a7791", "renesas,scif";
670 reg = <0 0xe6e60000 0 64>;
671 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
673 clock-names = "sci_ick";
674 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
675 dma-names = "tx", "rx";
676 power-domains = <&cpg_clocks>;
677 status = "disabled";
678 };
679
680 scif1: serial@e6e68000 {
681 compatible = "renesas,scif-r8a7791", "renesas,scif";
682 reg = <0 0xe6e68000 0 64>;
683 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
685 clock-names = "sci_ick";
686 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
687 dma-names = "tx", "rx";
688 power-domains = <&cpg_clocks>;
689 status = "disabled";
690 };
691
692 scif2: serial@e6e58000 {
693 compatible = "renesas,scif-r8a7791", "renesas,scif";
694 reg = <0 0xe6e58000 0 64>;
695 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
697 clock-names = "sci_ick";
698 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
699 dma-names = "tx", "rx";
700 power-domains = <&cpg_clocks>;
701 status = "disabled";
702 };
703
704 scif3: serial@e6ea8000 {
705 compatible = "renesas,scif-r8a7791", "renesas,scif";
706 reg = <0 0xe6ea8000 0 64>;
707 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
709 clock-names = "sci_ick";
710 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
711 dma-names = "tx", "rx";
712 power-domains = <&cpg_clocks>;
713 status = "disabled";
714 };
715
716 scif4: serial@e6ee0000 {
717 compatible = "renesas,scif-r8a7791", "renesas,scif";
718 reg = <0 0xe6ee0000 0 64>;
719 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
721 clock-names = "sci_ick";
722 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
723 dma-names = "tx", "rx";
724 power-domains = <&cpg_clocks>;
725 status = "disabled";
726 };
727
728 scif5: serial@e6ee8000 {
729 compatible = "renesas,scif-r8a7791", "renesas,scif";
730 reg = <0 0xe6ee8000 0 64>;
731 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
733 clock-names = "sci_ick";
734 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
735 dma-names = "tx", "rx";
736 power-domains = <&cpg_clocks>;
737 status = "disabled";
738 };
739
740 hscif0: serial@e62c0000 {
741 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
742 reg = <0 0xe62c0000 0 96>;
743 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
745 clock-names = "sci_ick";
746 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
747 dma-names = "tx", "rx";
748 power-domains = <&cpg_clocks>;
749 status = "disabled";
750 };
751
752 hscif1: serial@e62c8000 {
753 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
754 reg = <0 0xe62c8000 0 96>;
755 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
757 clock-names = "sci_ick";
758 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
759 dma-names = "tx", "rx";
760 power-domains = <&cpg_clocks>;
761 status = "disabled";
762 };
763
764 hscif2: serial@e62d0000 {
765 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
766 reg = <0 0xe62d0000 0 96>;
767 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
769 clock-names = "sci_ick";
770 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
771 dma-names = "tx", "rx";
772 power-domains = <&cpg_clocks>;
773 status = "disabled";
774 };
775
776 ether: ethernet@ee700000 {
777 compatible = "renesas,ether-r8a7791";
778 reg = <0 0xee700000 0 0x400>;
779 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
781 power-domains = <&cpg_clocks>;
782 phy-mode = "rmii";
783 #address-cells = <1>;
784 #size-cells = <0>;
785 status = "disabled";
786 };
787
788 avb: ethernet@e6800000 {
789 compatible = "renesas,etheravb-r8a7791",
790 "renesas,etheravb-rcar-gen2";
791 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
792 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
794 power-domains = <&cpg_clocks>;
795 #address-cells = <1>;
796 #size-cells = <0>;
797 status = "disabled";
798 };
799
800 sata0: sata@ee300000 {
801 compatible = "renesas,sata-r8a7791";
802 reg = <0 0xee300000 0 0x2000>;
803 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
805 power-domains = <&cpg_clocks>;
806 status = "disabled";
807 };
808
809 sata1: sata@ee500000 {
810 compatible = "renesas,sata-r8a7791";
811 reg = <0 0xee500000 0 0x2000>;
812 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
814 power-domains = <&cpg_clocks>;
815 status = "disabled";
816 };
817
818 hsusb: usb@e6590000 {
819 compatible = "renesas,usbhs-r8a7791";
820 reg = <0 0xe6590000 0 0x100>;
821 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
823 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
824 <&usb_dmac1 0>, <&usb_dmac1 1>;
825 dma-names = "ch0", "ch1", "ch2", "ch3";
826 power-domains = <&cpg_clocks>;
827 renesas,buswait = <4>;
828 phys = <&usb0 1>;
829 phy-names = "usb";
830 status = "disabled";
831 };
832
833 usbphy: usb-phy@e6590100 {
834 compatible = "renesas,usb-phy-r8a7791";
835 reg = <0 0xe6590100 0 0x100>;
836 #address-cells = <1>;
837 #size-cells = <0>;
838 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
839 clock-names = "usbhs";
840 power-domains = <&cpg_clocks>;
841 status = "disabled";
842
843 usb0: usb-channel@0 {
844 reg = <0>;
845 #phy-cells = <1>;
846 };
847 usb2: usb-channel@2 {
848 reg = <2>;
849 #phy-cells = <1>;
850 };
851 };
852
853 vin0: video@e6ef0000 {
854 compatible = "renesas,vin-r8a7791";
855 reg = <0 0xe6ef0000 0 0x1000>;
856 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
858 power-domains = <&cpg_clocks>;
859 status = "disabled";
860 };
861
862 vin1: video@e6ef1000 {
863 compatible = "renesas,vin-r8a7791";
864 reg = <0 0xe6ef1000 0 0x1000>;
865 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
867 power-domains = <&cpg_clocks>;
868 status = "disabled";
869 };
870
871 vin2: video@e6ef2000 {
872 compatible = "renesas,vin-r8a7791";
873 reg = <0 0xe6ef2000 0 0x1000>;
874 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
876 power-domains = <&cpg_clocks>;
877 status = "disabled";
878 };
879
880 vsp1@fe928000 {
881 compatible = "renesas,vsp1";
882 reg = <0 0xfe928000 0 0x8000>;
883 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
885 power-domains = <&cpg_clocks>;
886
887 renesas,has-lut;
888 renesas,has-sru;
889 renesas,#rpf = <5>;
890 renesas,#uds = <3>;
891 renesas,#wpf = <4>;
892 };
893
894 vsp1@fe930000 {
895 compatible = "renesas,vsp1";
896 reg = <0 0xfe930000 0 0x8000>;
897 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
899 power-domains = <&cpg_clocks>;
900
901 renesas,has-lif;
902 renesas,has-lut;
903 renesas,#rpf = <4>;
904 renesas,#uds = <1>;
905 renesas,#wpf = <4>;
906 };
907
908 vsp1@fe938000 {
909 compatible = "renesas,vsp1";
910 reg = <0 0xfe938000 0 0x8000>;
911 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
913 power-domains = <&cpg_clocks>;
914
915 renesas,has-lif;
916 renesas,has-lut;
917 renesas,#rpf = <4>;
918 renesas,#uds = <1>;
919 renesas,#wpf = <4>;
920 };
921
922 du: display@feb00000 {
923 compatible = "renesas,du-r8a7791";
924 reg = <0 0xfeb00000 0 0x40000>,
925 <0 0xfeb90000 0 0x1c>;
926 reg-names = "du", "lvds.0";
927 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
928 <0 268 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
930 <&mstp7_clks R8A7791_CLK_DU1>,
931 <&mstp7_clks R8A7791_CLK_LVDS0>;
932 clock-names = "du.0", "du.1", "lvds.0";
933 status = "disabled";
934
935 ports {
936 #address-cells = <1>;
937 #size-cells = <0>;
938
939 port@0 {
940 reg = <0>;
941 du_out_rgb: endpoint {
942 };
943 };
944 port@1 {
945 reg = <1>;
946 du_out_lvds0: endpoint {
947 };
948 };
949 };
950 };
951
952 can0: can@e6e80000 {
953 compatible = "renesas,can-r8a7791";
954 reg = <0 0xe6e80000 0 0x1000>;
955 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
957 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
958 clock-names = "clkp1", "clkp2", "can_clk";
959 power-domains = <&cpg_clocks>;
960 status = "disabled";
961 };
962
963 can1: can@e6e88000 {
964 compatible = "renesas,can-r8a7791";
965 reg = <0 0xe6e88000 0 0x1000>;
966 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
968 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
969 clock-names = "clkp1", "clkp2", "can_clk";
970 power-domains = <&cpg_clocks>;
971 status = "disabled";
972 };
973
974 jpu: jpeg-codec@fe980000 {
975 compatible = "renesas,jpu-r8a7791";
976 reg = <0 0xfe980000 0 0x10300>;
977 interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
979 power-domains = <&cpg_clocks>;
980 };
981
982 clocks {
983 #address-cells = <2>;
984 #size-cells = <2>;
985 ranges;
986
987 /* External root clock */
988 extal_clk: extal_clk {
989 compatible = "fixed-clock";
990 #clock-cells = <0>;
991 /* This value must be overriden by the board. */
992 clock-frequency = <0>;
993 clock-output-names = "extal";
994 };
995
996 /*
997 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
998 * default. Boards that provide audio clocks should override them.
999 */
1000 audio_clk_a: audio_clk_a {
1001 compatible = "fixed-clock";
1002 #clock-cells = <0>;
1003 clock-frequency = <0>;
1004 clock-output-names = "audio_clk_a";
1005 };
1006 audio_clk_b: audio_clk_b {
1007 compatible = "fixed-clock";
1008 #clock-cells = <0>;
1009 clock-frequency = <0>;
1010 clock-output-names = "audio_clk_b";
1011 };
1012 audio_clk_c: audio_clk_c {
1013 compatible = "fixed-clock";
1014 #clock-cells = <0>;
1015 clock-frequency = <0>;
1016 clock-output-names = "audio_clk_c";
1017 };
1018
1019 /* External PCIe clock - can be overridden by the board */
1020 pcie_bus_clk: pcie_bus_clk {
1021 compatible = "fixed-clock";
1022 #clock-cells = <0>;
1023 clock-frequency = <100000000>;
1024 clock-output-names = "pcie_bus";
1025 status = "disabled";
1026 };
1027
1028 /* External USB clock - can be overridden by the board */
1029 usb_extal_clk: usb_extal_clk {
1030 compatible = "fixed-clock";
1031 #clock-cells = <0>;
1032 clock-frequency = <48000000>;
1033 clock-output-names = "usb_extal";
1034 };
1035
1036 /* External CAN clock */
1037 can_clk: can_clk {
1038 compatible = "fixed-clock";
1039 #clock-cells = <0>;
1040 /* This value must be overridden by the board. */
1041 clock-frequency = <0>;
1042 clock-output-names = "can_clk";
1043 status = "disabled";
1044 };
1045
1046 /* Special CPG clocks */
1047 cpg_clocks: cpg_clocks@e6150000 {
1048 compatible = "renesas,r8a7791-cpg-clocks",
1049 "renesas,rcar-gen2-cpg-clocks";
1050 reg = <0 0xe6150000 0 0x1000>;
1051 clocks = <&extal_clk &usb_extal_clk>;
1052 #clock-cells = <1>;
1053 clock-output-names = "main", "pll0", "pll1", "pll3",
1054 "lb", "qspi", "sdh", "sd0", "z",
1055 "rcan", "adsp";
1056 #power-domain-cells = <0>;
1057 };
1058
1059 /* Variable factor clocks */
1060 sd2_clk: sd2_clk@e6150078 {
1061 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1062 reg = <0 0xe6150078 0 4>;
1063 clocks = <&pll1_div2_clk>;
1064 #clock-cells = <0>;
1065 clock-output-names = "sd2";
1066 };
1067 sd3_clk: sd3_clk@e615026c {
1068 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1069 reg = <0 0xe615026c 0 4>;
1070 clocks = <&pll1_div2_clk>;
1071 #clock-cells = <0>;
1072 clock-output-names = "sd3";
1073 };
1074 mmc0_clk: mmc0_clk@e6150240 {
1075 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1076 reg = <0 0xe6150240 0 4>;
1077 clocks = <&pll1_div2_clk>;
1078 #clock-cells = <0>;
1079 clock-output-names = "mmc0";
1080 };
1081 ssp_clk: ssp_clk@e6150248 {
1082 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1083 reg = <0 0xe6150248 0 4>;
1084 clocks = <&pll1_div2_clk>;
1085 #clock-cells = <0>;
1086 clock-output-names = "ssp";
1087 };
1088 ssprs_clk: ssprs_clk@e615024c {
1089 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1090 reg = <0 0xe615024c 0 4>;
1091 clocks = <&pll1_div2_clk>;
1092 #clock-cells = <0>;
1093 clock-output-names = "ssprs";
1094 };
1095
1096 /* Fixed factor clocks */
1097 pll1_div2_clk: pll1_div2_clk {
1098 compatible = "fixed-factor-clock";
1099 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1100 #clock-cells = <0>;
1101 clock-div = <2>;
1102 clock-mult = <1>;
1103 clock-output-names = "pll1_div2";
1104 };
1105 zg_clk: zg_clk {
1106 compatible = "fixed-factor-clock";
1107 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1108 #clock-cells = <0>;
1109 clock-div = <3>;
1110 clock-mult = <1>;
1111 clock-output-names = "zg";
1112 };
1113 zx_clk: zx_clk {
1114 compatible = "fixed-factor-clock";
1115 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1116 #clock-cells = <0>;
1117 clock-div = <3>;
1118 clock-mult = <1>;
1119 clock-output-names = "zx";
1120 };
1121 zs_clk: zs_clk {
1122 compatible = "fixed-factor-clock";
1123 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1124 #clock-cells = <0>;
1125 clock-div = <6>;
1126 clock-mult = <1>;
1127 clock-output-names = "zs";
1128 };
1129 hp_clk: hp_clk {
1130 compatible = "fixed-factor-clock";
1131 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1132 #clock-cells = <0>;
1133 clock-div = <12>;
1134 clock-mult = <1>;
1135 clock-output-names = "hp";
1136 };
1137 i_clk: i_clk {
1138 compatible = "fixed-factor-clock";
1139 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1140 #clock-cells = <0>;
1141 clock-div = <2>;
1142 clock-mult = <1>;
1143 clock-output-names = "i";
1144 };
1145 b_clk: b_clk {
1146 compatible = "fixed-factor-clock";
1147 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1148 #clock-cells = <0>;
1149 clock-div = <12>;
1150 clock-mult = <1>;
1151 clock-output-names = "b";
1152 };
1153 p_clk: p_clk {
1154 compatible = "fixed-factor-clock";
1155 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1156 #clock-cells = <0>;
1157 clock-div = <24>;
1158 clock-mult = <1>;
1159 clock-output-names = "p";
1160 };
1161 cl_clk: cl_clk {
1162 compatible = "fixed-factor-clock";
1163 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1164 #clock-cells = <0>;
1165 clock-div = <48>;
1166 clock-mult = <1>;
1167 clock-output-names = "cl";
1168 };
1169 m2_clk: m2_clk {
1170 compatible = "fixed-factor-clock";
1171 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1172 #clock-cells = <0>;
1173 clock-div = <8>;
1174 clock-mult = <1>;
1175 clock-output-names = "m2";
1176 };
1177 rclk_clk: rclk_clk {
1178 compatible = "fixed-factor-clock";
1179 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1180 #clock-cells = <0>;
1181 clock-div = <(48 * 1024)>;
1182 clock-mult = <1>;
1183 clock-output-names = "rclk";
1184 };
1185 oscclk_clk: oscclk_clk {
1186 compatible = "fixed-factor-clock";
1187 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1188 #clock-cells = <0>;
1189 clock-div = <(12 * 1024)>;
1190 clock-mult = <1>;
1191 clock-output-names = "oscclk";
1192 };
1193 zb3_clk: zb3_clk {
1194 compatible = "fixed-factor-clock";
1195 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1196 #clock-cells = <0>;
1197 clock-div = <4>;
1198 clock-mult = <1>;
1199 clock-output-names = "zb3";
1200 };
1201 zb3d2_clk: zb3d2_clk {
1202 compatible = "fixed-factor-clock";
1203 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1204 #clock-cells = <0>;
1205 clock-div = <8>;
1206 clock-mult = <1>;
1207 clock-output-names = "zb3d2";
1208 };
1209 ddr_clk: ddr_clk {
1210 compatible = "fixed-factor-clock";
1211 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1212 #clock-cells = <0>;
1213 clock-div = <8>;
1214 clock-mult = <1>;
1215 clock-output-names = "ddr";
1216 };
1217 mp_clk: mp_clk {
1218 compatible = "fixed-factor-clock";
1219 clocks = <&pll1_div2_clk>;
1220 #clock-cells = <0>;
1221 clock-div = <15>;
1222 clock-mult = <1>;
1223 clock-output-names = "mp";
1224 };
1225 cp_clk: cp_clk {
1226 compatible = "fixed-factor-clock";
1227 clocks = <&extal_clk>;
1228 #clock-cells = <0>;
1229 clock-div = <2>;
1230 clock-mult = <1>;
1231 clock-output-names = "cp";
1232 };
1233
1234 /* Gate clocks */
1235 mstp0_clks: mstp0_clks@e6150130 {
1236 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1237 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1238 clocks = <&mp_clk>;
1239 #clock-cells = <1>;
1240 clock-indices = <R8A7791_CLK_MSIOF0>;
1241 clock-output-names = "msiof0";
1242 };
1243 mstp1_clks: mstp1_clks@e6150134 {
1244 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1245 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1246 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1247 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1248 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1249 <&zs_clk>;
1250 #clock-cells = <1>;
1251 clock-indices = <
1252 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1253 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1254 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1255 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1256 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1257 R8A7791_CLK_VSP1_S
1258 >;
1259 clock-output-names =
1260 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1261 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1262 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1263 };
1264 mstp2_clks: mstp2_clks@e6150138 {
1265 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1266 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1267 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1268 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1269 <&zs_clk>, <&zs_clk>;
1270 #clock-cells = <1>;
1271 clock-indices = <
1272 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1273 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1274 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1275 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1276 >;
1277 clock-output-names =
1278 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1279 "scifb1", "msiof1", "scifb2",
1280 "sys-dmac1", "sys-dmac0";
1281 };
1282 mstp3_clks: mstp3_clks@e615013c {
1283 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1284 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1285 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1286 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1287 <&hp_clk>, <&hp_clk>;
1288 #clock-cells = <1>;
1289 clock-indices = <
1290 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1291 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1292 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1293 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1294 >;
1295 clock-output-names =
1296 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1297 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1298 "usbdmac0", "usbdmac1";
1299 };
1300 mstp4_clks: mstp4_clks@e6150140 {
1301 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1302 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1303 clocks = <&cp_clk>;
1304 #clock-cells = <1>;
1305 clock-indices = <R8A7791_CLK_IRQC>;
1306 clock-output-names = "irqc";
1307 };
1308 mstp5_clks: mstp5_clks@e6150144 {
1309 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1310 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1311 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1312 <&extal_clk>, <&p_clk>;
1313 #clock-cells = <1>;
1314 clock-indices = <
1315 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1316 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1317 R8A7791_CLK_PWM
1318 >;
1319 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1320 "thermal", "pwm";
1321 };
1322 mstp7_clks: mstp7_clks@e615014c {
1323 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1324 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1325 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1326 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1327 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1328 #clock-cells = <1>;
1329 clock-indices = <
1330 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1331 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1332 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1333 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1334 R8A7791_CLK_LVDS0
1335 >;
1336 clock-output-names =
1337 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1338 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1339 };
1340 mstp8_clks: mstp8_clks@e6150990 {
1341 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1342 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1343 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1344 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1345 <&zs_clk>;
1346 #clock-cells = <1>;
1347 clock-indices = <
1348 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1349 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1350 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
1351 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1352 >;
1353 clock-output-names =
1354 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
1355 "etheravb", "ether", "sata1", "sata0";
1356 };
1357 mstp9_clks: mstp9_clks@e6150994 {
1358 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1359 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1360 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1361 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1362 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1363 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1364 <&hp_clk>, <&hp_clk>;
1365 #clock-cells = <1>;
1366 clock-indices = <
1367 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1368 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1369 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1370 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1371 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1372 >;
1373 clock-output-names =
1374 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1375 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1376 "i2c1", "i2c0";
1377 };
1378 mstp10_clks: mstp10_clks@e6150998 {
1379 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1380 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1381 clocks = <&p_clk>,
1382 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1383 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1384 <&p_clk>,
1385 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1386 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1387 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1388 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1389 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1390 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1391 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1392
1393 #clock-cells = <1>;
1394 clock-indices = <
1395 R8A7791_CLK_SSI_ALL
1396 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1397 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1398 R8A7791_CLK_SCU_ALL
1399 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1400 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
1401 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1402 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1403 >;
1404 clock-output-names =
1405 "ssi-all",
1406 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1407 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1408 "scu-all",
1409 "scu-dvc1", "scu-dvc0",
1410 "scu-ctu1-mix1", "scu-ctu0-mix0",
1411 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1412 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1413 };
1414 mstp11_clks: mstp11_clks@e615099c {
1415 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1416 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1417 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1418 #clock-cells = <1>;
1419 clock-indices = <
1420 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1421 >;
1422 clock-output-names = "scifa3", "scifa4", "scifa5";
1423 };
1424 };
1425
1426 qspi: spi@e6b10000 {
1427 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1428 reg = <0 0xe6b10000 0 0x2c>;
1429 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1430 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1431 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1432 dma-names = "tx", "rx";
1433 power-domains = <&cpg_clocks>;
1434 num-cs = <1>;
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1437 status = "disabled";
1438 };
1439
1440 msiof0: spi@e6e20000 {
1441 compatible = "renesas,msiof-r8a7791";
1442 reg = <0 0xe6e20000 0 0x0064>;
1443 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1445 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1446 dma-names = "tx", "rx";
1447 power-domains = <&cpg_clocks>;
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1450 status = "disabled";
1451 };
1452
1453 msiof1: spi@e6e10000 {
1454 compatible = "renesas,msiof-r8a7791";
1455 reg = <0 0xe6e10000 0 0x0064>;
1456 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1458 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1459 dma-names = "tx", "rx";
1460 power-domains = <&cpg_clocks>;
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 status = "disabled";
1464 };
1465
1466 msiof2: spi@e6e00000 {
1467 compatible = "renesas,msiof-r8a7791";
1468 reg = <0 0xe6e00000 0 0x0064>;
1469 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1470 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1471 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1472 dma-names = "tx", "rx";
1473 power-domains = <&cpg_clocks>;
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1476 status = "disabled";
1477 };
1478
1479 xhci: usb@ee000000 {
1480 compatible = "renesas,xhci-r8a7791";
1481 reg = <0 0xee000000 0 0xc00>;
1482 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1483 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1484 power-domains = <&cpg_clocks>;
1485 phys = <&usb2 1>;
1486 phy-names = "usb";
1487 status = "disabled";
1488 };
1489
1490 pci0: pci@ee090000 {
1491 compatible = "renesas,pci-r8a7791";
1492 device_type = "pci";
1493 reg = <0 0xee090000 0 0xc00>,
1494 <0 0xee080000 0 0x1100>;
1495 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1496 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1497 power-domains = <&cpg_clocks>;
1498 status = "disabled";
1499
1500 bus-range = <0 0>;
1501 #address-cells = <3>;
1502 #size-cells = <2>;
1503 #interrupt-cells = <1>;
1504 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1505 interrupt-map-mask = <0xff00 0 0 0x7>;
1506 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1507 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1508 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1509
1510 usb@0,1 {
1511 reg = <0x800 0 0 0 0>;
1512 device_type = "pci";
1513 phys = <&usb0 0>;
1514 phy-names = "usb";
1515 };
1516
1517 usb@0,2 {
1518 reg = <0x1000 0 0 0 0>;
1519 device_type = "pci";
1520 phys = <&usb0 0>;
1521 phy-names = "usb";
1522 };
1523 };
1524
1525 pci1: pci@ee0d0000 {
1526 compatible = "renesas,pci-r8a7791";
1527 device_type = "pci";
1528 reg = <0 0xee0d0000 0 0xc00>,
1529 <0 0xee0c0000 0 0x1100>;
1530 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1531 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1532 power-domains = <&cpg_clocks>;
1533 status = "disabled";
1534
1535 bus-range = <1 1>;
1536 #address-cells = <3>;
1537 #size-cells = <2>;
1538 #interrupt-cells = <1>;
1539 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1540 interrupt-map-mask = <0xff00 0 0 0x7>;
1541 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1542 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1543 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1544
1545 usb@0,1 {
1546 reg = <0x800 0 0 0 0>;
1547 device_type = "pci";
1548 phys = <&usb2 0>;
1549 phy-names = "usb";
1550 };
1551
1552 usb@0,2 {
1553 reg = <0x1000 0 0 0 0>;
1554 device_type = "pci";
1555 phys = <&usb2 0>;
1556 phy-names = "usb";
1557 };
1558 };
1559
1560 pciec: pcie@fe000000 {
1561 compatible = "renesas,pcie-r8a7791";
1562 reg = <0 0xfe000000 0 0x80000>;
1563 #address-cells = <3>;
1564 #size-cells = <2>;
1565 bus-range = <0x00 0xff>;
1566 device_type = "pci";
1567 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1568 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1569 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1570 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1571 /* Map all possible DDR as inbound ranges */
1572 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1573 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1574 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1575 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1576 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1577 #interrupt-cells = <1>;
1578 interrupt-map-mask = <0 0 0 0>;
1579 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1580 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1581 clock-names = "pcie", "pcie_bus";
1582 power-domains = <&cpg_clocks>;
1583 status = "disabled";
1584 };
1585
1586 ipmmu_sy0: mmu@e6280000 {
1587 compatible = "renesas,ipmmu-vmsa";
1588 reg = <0 0xe6280000 0 0x1000>;
1589 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1590 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1591 #iommu-cells = <1>;
1592 status = "disabled";
1593 };
1594
1595 ipmmu_sy1: mmu@e6290000 {
1596 compatible = "renesas,ipmmu-vmsa";
1597 reg = <0 0xe6290000 0 0x1000>;
1598 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1599 #iommu-cells = <1>;
1600 status = "disabled";
1601 };
1602
1603 ipmmu_ds: mmu@e6740000 {
1604 compatible = "renesas,ipmmu-vmsa";
1605 reg = <0 0xe6740000 0 0x1000>;
1606 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1607 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1608 #iommu-cells = <1>;
1609 status = "disabled";
1610 };
1611
1612 ipmmu_mp: mmu@ec680000 {
1613 compatible = "renesas,ipmmu-vmsa";
1614 reg = <0 0xec680000 0 0x1000>;
1615 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1616 #iommu-cells = <1>;
1617 status = "disabled";
1618 };
1619
1620 ipmmu_mx: mmu@fe951000 {
1621 compatible = "renesas,ipmmu-vmsa";
1622 reg = <0 0xfe951000 0 0x1000>;
1623 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1624 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1625 #iommu-cells = <1>;
1626 status = "disabled";
1627 };
1628
1629 ipmmu_rt: mmu@ffc80000 {
1630 compatible = "renesas,ipmmu-vmsa";
1631 reg = <0 0xffc80000 0 0x1000>;
1632 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1633 #iommu-cells = <1>;
1634 status = "disabled";
1635 };
1636
1637 ipmmu_gp: mmu@e62a0000 {
1638 compatible = "renesas,ipmmu-vmsa";
1639 reg = <0 0xe62a0000 0 0x1000>;
1640 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1641 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1642 #iommu-cells = <1>;
1643 status = "disabled";
1644 };
1645
1646 rcar_sound: sound@ec500000 {
1647 /*
1648 * #sound-dai-cells is required
1649 *
1650 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1651 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1652 */
1653 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1654 reg = <0 0xec500000 0 0x1000>, /* SCU */
1655 <0 0xec5a0000 0 0x100>, /* ADG */
1656 <0 0xec540000 0 0x1000>, /* SSIU */
1657 <0 0xec541000 0 0x280>, /* SSI */
1658 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1659 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1660
1661 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1662 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1663 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1664 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1665 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1666 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1667 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1668 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1669 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1670 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1671 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1672 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1673 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1674 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1675 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1676 clock-names = "ssi-all",
1677 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1678 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1679 "src.9", "src.8", "src.7", "src.6", "src.5",
1680 "src.4", "src.3", "src.2", "src.1", "src.0",
1681 "ctu.0", "ctu.1",
1682 "mix.0", "mix.1",
1683 "dvc.0", "dvc.1",
1684 "clk_a", "clk_b", "clk_c", "clk_i";
1685 power-domains = <&cpg_clocks>;
1686
1687 status = "disabled";
1688
1689 rcar_sound,dvc {
1690 dvc0: dvc@0 {
1691 dmas = <&audma0 0xbc>;
1692 dma-names = "tx";
1693 };
1694 dvc1: dvc@1 {
1695 dmas = <&audma0 0xbe>;
1696 dma-names = "tx";
1697 };
1698 };
1699
1700 rcar_sound,mix {
1701 mix0: mix@0 { };
1702 mix1: mix@1 { };
1703 };
1704
1705 rcar_sound,ctu {
1706 ctu00: ctu@0 { };
1707 ctu01: ctu@1 { };
1708 ctu02: ctu@2 { };
1709 ctu03: ctu@3 { };
1710 ctu10: ctu@4 { };
1711 ctu11: ctu@5 { };
1712 ctu12: ctu@6 { };
1713 ctu13: ctu@7 { };
1714 };
1715
1716 rcar_sound,src {
1717 src0: src@0 {
1718 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1719 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1720 dma-names = "rx", "tx";
1721 };
1722 src1: src@1 {
1723 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1724 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1725 dma-names = "rx", "tx";
1726 };
1727 src2: src@2 {
1728 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1729 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1730 dma-names = "rx", "tx";
1731 };
1732 src3: src@3 {
1733 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1734 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1735 dma-names = "rx", "tx";
1736 };
1737 src4: src@4 {
1738 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1740 dma-names = "rx", "tx";
1741 };
1742 src5: src@5 {
1743 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1744 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1745 dma-names = "rx", "tx";
1746 };
1747 src6: src@6 {
1748 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1749 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1750 dma-names = "rx", "tx";
1751 };
1752 src7: src@7 {
1753 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1754 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1755 dma-names = "rx", "tx";
1756 };
1757 src8: src@8 {
1758 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1759 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1760 dma-names = "rx", "tx";
1761 };
1762 src9: src@9 {
1763 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1764 dmas = <&audma0 0x97>, <&audma1 0xba>;
1765 dma-names = "rx", "tx";
1766 };
1767 };
1768
1769 rcar_sound,ssi {
1770 ssi0: ssi@0 {
1771 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1772 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1773 dma-names = "rx", "tx", "rxu", "txu";
1774 };
1775 ssi1: ssi@1 {
1776 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1777 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1778 dma-names = "rx", "tx", "rxu", "txu";
1779 };
1780 ssi2: ssi@2 {
1781 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1782 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1783 dma-names = "rx", "tx", "rxu", "txu";
1784 };
1785 ssi3: ssi@3 {
1786 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1787 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1788 dma-names = "rx", "tx", "rxu", "txu";
1789 };
1790 ssi4: ssi@4 {
1791 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1792 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1793 dma-names = "rx", "tx", "rxu", "txu";
1794 };
1795 ssi5: ssi@5 {
1796 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1797 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1798 dma-names = "rx", "tx", "rxu", "txu";
1799 };
1800 ssi6: ssi@6 {
1801 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1802 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1803 dma-names = "rx", "tx", "rxu", "txu";
1804 };
1805 ssi7: ssi@7 {
1806 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1807 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1808 dma-names = "rx", "tx", "rxu", "txu";
1809 };
1810 ssi8: ssi@8 {
1811 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1812 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1813 dma-names = "rx", "tx", "rxu", "txu";
1814 };
1815 ssi9: ssi@9 {
1816 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1818 dma-names = "rx", "tx", "rxu", "txu";
1819 };
1820 };
1821 };
1822 };
Linux kernel - Deliverables
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