2 * Device Tree Source for the r8a7791 SoC
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <dt-bindings/clock/r8a7791-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
45 compatible = "arm,cortex-a15";
47 clock-frequency = <1500000000>;
48 voltage-tolerance = <1>; /* 1% */
49 clocks = <&cpg_clocks R8A7791_CLK_Z>;
50 clock-latency = <300000>; /* 300 us */
52 /* kHz - uV - OPPs unknown yet */
53 operating-points = <1500000 1000000>,
63 compatible = "arm,cortex-a15";
65 clock-frequency = <1500000000>;
69 gic: interrupt-controller@f1001000 {
70 compatible = "arm,cortex-a15-gic";
71 #interrupt-cells = <3>;
74 reg = <0 0xf1001000 0 0x1000>,
75 <0 0xf1002000 0 0x1000>,
76 <0 0xf1004000 0 0x2000>,
77 <0 0xf1006000 0 0x2000>;
78 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
81 gpio0: gpio@e6050000 {
82 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
83 reg = <0 0xe6050000 0 0x50>;
84 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
87 gpio-ranges = <&pfc 0 0 32>;
88 #interrupt-cells = <2>;
90 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
93 gpio1: gpio@e6051000 {
94 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
95 reg = <0 0xe6051000 0 0x50>;
96 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
99 gpio-ranges = <&pfc 0 32 32>;
100 #interrupt-cells = <2>;
101 interrupt-controller;
102 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
105 gpio2: gpio@e6052000 {
106 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
107 reg = <0 0xe6052000 0 0x50>;
108 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
111 gpio-ranges = <&pfc 0 64 32>;
112 #interrupt-cells = <2>;
113 interrupt-controller;
114 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
117 gpio3: gpio@e6053000 {
118 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
119 reg = <0 0xe6053000 0 0x50>;
120 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
123 gpio-ranges = <&pfc 0 96 32>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
129 gpio4: gpio@e6054000 {
130 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
131 reg = <0 0xe6054000 0 0x50>;
132 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
135 gpio-ranges = <&pfc 0 128 32>;
136 #interrupt-cells = <2>;
137 interrupt-controller;
138 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
141 gpio5: gpio@e6055000 {
142 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
143 reg = <0 0xe6055000 0 0x50>;
144 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
147 gpio-ranges = <&pfc 0 160 32>;
148 #interrupt-cells = <2>;
149 interrupt-controller;
150 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
153 gpio6: gpio@e6055400 {
154 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
155 reg = <0 0xe6055400 0 0x50>;
156 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
159 gpio-ranges = <&pfc 0 192 32>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
165 gpio7: gpio@e6055800 {
166 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
167 reg = <0 0xe6055800 0 0x50>;
168 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
171 gpio-ranges = <&pfc 0 224 26>;
172 #interrupt-cells = <2>;
173 interrupt-controller;
174 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
178 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
179 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
180 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
185 compatible = "arm,armv7-timer";
186 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
187 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
188 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
189 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
192 irqc0: interrupt-controller@e61c0000 {
193 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
194 #interrupt-cells = <2>;
195 interrupt-controller;
196 reg = <0 0xe61c0000 0 0x200>;
197 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
198 <0 1 IRQ_TYPE_LEVEL_HIGH>,
199 <0 2 IRQ_TYPE_LEVEL_HIGH>,
200 <0 3 IRQ_TYPE_LEVEL_HIGH>,
201 <0 12 IRQ_TYPE_LEVEL_HIGH>,
202 <0 13 IRQ_TYPE_LEVEL_HIGH>,
203 <0 14 IRQ_TYPE_LEVEL_HIGH>,
204 <0 15 IRQ_TYPE_LEVEL_HIGH>,
205 <0 16 IRQ_TYPE_LEVEL_HIGH>,
206 <0 17 IRQ_TYPE_LEVEL_HIGH>;
209 /* The memory map in the User's Manual maps the cores to bus numbers */
211 #address-cells = <1>;
213 compatible = "renesas,i2c-r8a7791";
214 reg = <0 0xe6508000 0 0x40>;
215 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
221 #address-cells = <1>;
223 compatible = "renesas,i2c-r8a7791";
224 reg = <0 0xe6518000 0 0x40>;
225 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
231 #address-cells = <1>;
233 compatible = "renesas,i2c-r8a7791";
234 reg = <0 0xe6530000 0 0x40>;
235 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
241 #address-cells = <1>;
243 compatible = "renesas,i2c-r8a7791";
244 reg = <0 0xe6540000 0 0x40>;
245 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
251 #address-cells = <1>;
253 compatible = "renesas,i2c-r8a7791";
254 reg = <0 0xe6520000 0 0x40>;
255 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
261 /* doesn't need pinmux */
262 #address-cells = <1>;
264 compatible = "renesas,i2c-r8a7791";
265 reg = <0 0xe6528000 0 0x40>;
266 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
272 /* doesn't need pinmux */
273 #address-cells = <1>;
275 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
276 reg = <0 0xe60b0000 0 0x425>;
277 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
283 #address-cells = <1>;
285 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
286 reg = <0 0xe6500000 0 0x425>;
287 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
293 #address-cells = <1>;
295 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
296 reg = <0 0xe6510000 0 0x425>;
297 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
303 compatible = "renesas,pfc-r8a7791";
304 reg = <0 0xe6060000 0 0x250>;
305 #gpio-range-cells = <3>;
309 compatible = "renesas,sdhi-r8a7791";
310 reg = <0 0xee100000 0 0x200>;
311 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
317 compatible = "renesas,sdhi-r8a7791";
318 reg = <0 0xee140000 0 0x100>;
319 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
325 compatible = "renesas,sdhi-r8a7791";
326 reg = <0 0xee160000 0 0x100>;
327 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
332 scifa0: serial@e6c40000 {
333 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
334 reg = <0 0xe6c40000 0 64>;
335 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
337 clock-names = "sci_ick";
341 scifa1: serial@e6c50000 {
342 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
343 reg = <0 0xe6c50000 0 64>;
344 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
346 clock-names = "sci_ick";
350 scifa2: serial@e6c60000 {
351 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
352 reg = <0 0xe6c60000 0 64>;
353 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
355 clock-names = "sci_ick";
359 scifa3: serial@e6c70000 {
360 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
361 reg = <0 0xe6c70000 0 64>;
362 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
364 clock-names = "sci_ick";
368 scifa4: serial@e6c78000 {
369 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
370 reg = <0 0xe6c78000 0 64>;
371 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
373 clock-names = "sci_ick";
377 scifa5: serial@e6c80000 {
378 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
379 reg = <0 0xe6c80000 0 64>;
380 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
382 clock-names = "sci_ick";
386 scifb0: serial@e6c20000 {
387 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
388 reg = <0 0xe6c20000 0 64>;
389 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
391 clock-names = "sci_ick";
395 scifb1: serial@e6c30000 {
396 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
397 reg = <0 0xe6c30000 0 64>;
398 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
400 clock-names = "sci_ick";
404 scifb2: serial@e6ce0000 {
405 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
406 reg = <0 0xe6ce0000 0 64>;
407 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
409 clock-names = "sci_ick";
413 scif0: serial@e6e60000 {
414 compatible = "renesas,scif-r8a7791", "renesas,scif";
415 reg = <0 0xe6e60000 0 64>;
416 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
418 clock-names = "sci_ick";
422 scif1: serial@e6e68000 {
423 compatible = "renesas,scif-r8a7791", "renesas,scif";
424 reg = <0 0xe6e68000 0 64>;
425 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
427 clock-names = "sci_ick";
431 scif2: serial@e6e58000 {
432 compatible = "renesas,scif-r8a7791", "renesas,scif";
433 reg = <0 0xe6e58000 0 64>;
434 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
436 clock-names = "sci_ick";
440 scif3: serial@e6ea8000 {
441 compatible = "renesas,scif-r8a7791", "renesas,scif";
442 reg = <0 0xe6ea8000 0 64>;
443 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
445 clock-names = "sci_ick";
449 scif4: serial@e6ee0000 {
450 compatible = "renesas,scif-r8a7791", "renesas,scif";
451 reg = <0 0xe6ee0000 0 64>;
452 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
454 clock-names = "sci_ick";
458 scif5: serial@e6ee8000 {
459 compatible = "renesas,scif-r8a7791", "renesas,scif";
460 reg = <0 0xe6ee8000 0 64>;
461 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
463 clock-names = "sci_ick";
467 hscif0: serial@e62c0000 {
468 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
469 reg = <0 0xe62c0000 0 96>;
470 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
472 clock-names = "sci_ick";
476 hscif1: serial@e62c8000 {
477 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
478 reg = <0 0xe62c8000 0 96>;
479 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
481 clock-names = "sci_ick";
485 hscif2: serial@e62d0000 {
486 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
487 reg = <0 0xe62d0000 0 96>;
488 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
490 clock-names = "sci_ick";
494 ether: ethernet@ee700000 {
495 compatible = "renesas,ether-r8a7791";
496 reg = <0 0xee700000 0 0x400>;
497 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
500 #address-cells = <1>;
505 sata0: sata@ee300000 {
506 compatible = "renesas,sata-r8a7791";
507 reg = <0 0xee300000 0 0x2000>;
508 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
513 sata1: sata@ee500000 {
514 compatible = "renesas,sata-r8a7791";
515 reg = <0 0xee500000 0 0x2000>;
516 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
522 #address-cells = <2>;
526 /* External root clock */
527 extal_clk: extal_clk {
528 compatible = "fixed-clock";
530 /* This value must be overriden by the board. */
531 clock-frequency = <0>;
532 clock-output-names = "extal";
536 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
537 * default. Boards that provide audio clocks should override them.
539 audio_clk_a: audio_clk_a {
540 compatible = "fixed-clock";
542 clock-frequency = <0>;
543 clock-output-names = "audio_clk_a";
545 audio_clk_b: audio_clk_b {
546 compatible = "fixed-clock";
548 clock-frequency = <0>;
549 clock-output-names = "audio_clk_b";
551 audio_clk_c: audio_clk_c {
552 compatible = "fixed-clock";
554 clock-frequency = <0>;
555 clock-output-names = "audio_clk_c";
558 /* External PCIe clock - can be overridden by the board */
559 pcie_bus_clk: pcie_bus_clk {
560 compatible = "fixed-clock";
562 clock-frequency = <100000000>;
563 clock-output-names = "pcie_bus";
567 /* Special CPG clocks */
568 cpg_clocks: cpg_clocks@e6150000 {
569 compatible = "renesas,r8a7791-cpg-clocks",
570 "renesas,rcar-gen2-cpg-clocks";
571 reg = <0 0xe6150000 0 0x1000>;
572 clocks = <&extal_clk>;
574 clock-output-names = "main", "pll0", "pll1", "pll3",
575 "lb", "qspi", "sdh", "sd0", "z";
578 /* Variable factor clocks */
579 sd1_clk: sd2_clk@e6150078 {
580 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
581 reg = <0 0xe6150078 0 4>;
582 clocks = <&pll1_div2_clk>;
584 clock-output-names = "sd1";
586 sd2_clk: sd3_clk@e615026c {
587 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
588 reg = <0 0xe615026c 0 4>;
589 clocks = <&pll1_div2_clk>;
591 clock-output-names = "sd2";
593 mmc0_clk: mmc0_clk@e6150240 {
594 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
595 reg = <0 0xe6150240 0 4>;
596 clocks = <&pll1_div2_clk>;
598 clock-output-names = "mmc0";
600 ssp_clk: ssp_clk@e6150248 {
601 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
602 reg = <0 0xe6150248 0 4>;
603 clocks = <&pll1_div2_clk>;
605 clock-output-names = "ssp";
607 ssprs_clk: ssprs_clk@e615024c {
608 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
609 reg = <0 0xe615024c 0 4>;
610 clocks = <&pll1_div2_clk>;
612 clock-output-names = "ssprs";
615 /* Fixed factor clocks */
616 pll1_div2_clk: pll1_div2_clk {
617 compatible = "fixed-factor-clock";
618 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
622 clock-output-names = "pll1_div2";
625 compatible = "fixed-factor-clock";
626 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
630 clock-output-names = "zg";
633 compatible = "fixed-factor-clock";
634 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
638 clock-output-names = "zx";
641 compatible = "fixed-factor-clock";
642 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
646 clock-output-names = "zs";
649 compatible = "fixed-factor-clock";
650 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
654 clock-output-names = "hp";
657 compatible = "fixed-factor-clock";
658 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
662 clock-output-names = "i";
665 compatible = "fixed-factor-clock";
666 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
670 clock-output-names = "b";
673 compatible = "fixed-factor-clock";
674 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
678 clock-output-names = "p";
681 compatible = "fixed-factor-clock";
682 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
686 clock-output-names = "cl";
689 compatible = "fixed-factor-clock";
690 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
694 clock-output-names = "m2";
697 compatible = "fixed-factor-clock";
698 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
702 clock-output-names = "imp";
705 compatible = "fixed-factor-clock";
706 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
708 clock-div = <(48 * 1024)>;
710 clock-output-names = "rclk";
712 oscclk_clk: oscclk_clk {
713 compatible = "fixed-factor-clock";
714 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
716 clock-div = <(12 * 1024)>;
718 clock-output-names = "oscclk";
721 compatible = "fixed-factor-clock";
722 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
726 clock-output-names = "zb3";
728 zb3d2_clk: zb3d2_clk {
729 compatible = "fixed-factor-clock";
730 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
734 clock-output-names = "zb3d2";
737 compatible = "fixed-factor-clock";
738 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
742 clock-output-names = "ddr";
745 compatible = "fixed-factor-clock";
746 clocks = <&pll1_div2_clk>;
750 clock-output-names = "mp";
753 compatible = "fixed-factor-clock";
754 clocks = <&extal_clk>;
758 clock-output-names = "cp";
762 mstp0_clks: mstp0_clks@e6150130 {
763 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
764 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
767 renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
768 clock-output-names = "msiof0";
770 mstp1_clks: mstp1_clks@e6150134 {
771 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
772 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
773 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
774 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
776 renesas,clock-indices = <
777 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
778 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
779 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
782 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
783 "vsp1-du0", "vsp1-sy";
785 mstp2_clks: mstp2_clks@e6150138 {
786 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
787 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
788 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
789 <&mp_clk>, <&mp_clk>, <&mp_clk>,
790 <&zs_clk>, <&zs_clk>;
792 renesas,clock-indices = <
793 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
794 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
795 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
796 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
799 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
800 "scifb1", "msiof1", "scifb2",
801 "sys-dmac1", "sys-dmac0";
803 mstp3_clks: mstp3_clks@e615013c {
804 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
805 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
806 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
807 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
809 renesas,clock-indices = <
810 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
811 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
812 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
815 "tpu0", "sdhi2", "sdhi1", "sdhi0",
816 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
818 mstp5_clks: mstp5_clks@e6150144 {
819 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
820 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
821 clocks = <&extal_clk>, <&p_clk>;
823 renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
824 clock-output-names = "thermal", "pwm";
826 mstp7_clks: mstp7_clks@e615014c {
827 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
828 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
829 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
830 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
831 <&zx_clk>, <&zx_clk>, <&zx_clk>;
833 renesas,clock-indices = <
834 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
835 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
836 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
837 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
841 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
842 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
844 mstp8_clks: mstp8_clks@e6150990 {
845 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
846 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
847 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
850 renesas,clock-indices = <
851 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
852 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
855 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
857 mstp9_clks: mstp9_clks@e6150994 {
858 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
859 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
860 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
861 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
862 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
863 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
864 <&hp_clk>, <&hp_clk>;
866 renesas,clock-indices = <
867 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
868 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
869 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
870 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
871 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
874 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
875 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
878 mstp10_clks: mstp10_clks@e6150998 {
879 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
880 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
882 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
883 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
885 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
886 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
887 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
888 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
889 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
890 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
895 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
896 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
898 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
899 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
900 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
904 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
905 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
907 "scu-dvc1", "scu-dvc0",
908 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
909 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
911 mstp11_clks: mstp11_clks@e615099c {
912 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
913 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
914 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
916 renesas,clock-indices = <
917 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
919 clock-output-names = "scifa3", "scifa4", "scifa5";
924 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
925 reg = <0 0xe6b10000 0 0x2c>;
926 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
929 #address-cells = <1>;
934 msiof0: spi@e6e20000 {
935 compatible = "renesas,msiof-r8a7791";
936 reg = <0 0xe6e20000 0 0x0064>;
937 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
939 #address-cells = <1>;
944 msiof1: spi@e6e10000 {
945 compatible = "renesas,msiof-r8a7791";
946 reg = <0 0xe6e10000 0 0x0064>;
947 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
949 #address-cells = <1>;
954 msiof2: spi@e6e00000 {
955 compatible = "renesas,msiof-r8a7791";
956 reg = <0 0xe6e00000 0 0x0064>;
957 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
959 #address-cells = <1>;
965 compatible = "renesas,pci-r8a7791";
967 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
968 reg = <0 0xee090000 0 0xc00>,
969 <0 0xee080000 0 0x1100>;
970 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
974 #address-cells = <3>;
976 #interrupt-cells = <1>;
977 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
978 interrupt-map-mask = <0xff00 0 0 0x7>;
979 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
980 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
981 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
985 compatible = "renesas,pci-r8a7791";
987 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
988 reg = <0 0xee0d0000 0 0xc00>,
989 <0 0xee0c0000 0 0x1100>;
990 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
994 #address-cells = <3>;
996 #interrupt-cells = <1>;
997 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
998 interrupt-map-mask = <0xff00 0 0 0x7>;
999 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1000 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1001 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1004 pciec: pcie@fe000000 {
1005 compatible = "renesas,pcie-r8a7791";
1006 reg = <0 0xfe000000 0 0x80000>;
1007 #address-cells = <3>;
1009 bus-range = <0x00 0xff>;
1010 device_type = "pci";
1011 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1012 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1013 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1014 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1015 /* Map all possible DDR as inbound ranges */
1016 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1017 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1018 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1019 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1020 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1021 #interrupt-cells = <1>;
1022 interrupt-map-mask = <0 0 0 0>;
1023 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1025 clock-names = "pcie", "pcie_bus";
1026 status = "disabled";
1029 rcar_sound: rcar_sound@0xec500000 {
1030 #sound-dai-cells = <1>;
1031 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1032 interrupt-parent = <&gic>;
1033 reg = <0 0xec500000 0 0x1000>, /* SCU */
1034 <0 0xec5a0000 0 0x100>, /* ADG */
1035 <0 0xec540000 0 0x1000>, /* SSIU */
1036 <0 0xec541000 0 0x1280>; /* SSI */
1037 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1038 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1039 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1040 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1041 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1042 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1043 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1044 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1045 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1046 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1047 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1048 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1049 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1050 clock-names = "ssi-all",
1051 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1052 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1053 "src.9", "src.8", "src.7", "src.6", "src.5",
1054 "src.4", "src.3", "src.2", "src.1", "src.0",
1056 "clk_a", "clk_b", "clk_c", "clk_i";
1058 status = "disabled";
1079 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1080 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1081 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1082 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1083 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1084 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1085 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1086 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1087 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1088 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };