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Merge tag 'at91-ab-4.8-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni...
[deliverable/linux.git] / arch / arm / boot / dts / r8a7793.dtsi
1 /*
2 * Device Tree Source for the r8a7793 SoC
3 *
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11 #include <dt-bindings/clock/r8a7793-clock.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/r8a7793-sysc.h>
15
16 / {
17 compatible = "renesas,r8a7793";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
32 spi0 = &qspi;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu0: cpu@0 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a15";
42 reg = <0>;
43 clock-frequency = <1500000000>;
44 voltage-tolerance = <1>; /* 1% */
45 clocks = <&cpg_clocks R8A7793_CLK_Z>;
46 clock-latency = <300000>; /* 300 us */
47 power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
48
49 /* kHz - uV - OPPs unknown yet */
50 operating-points = <1500000 1000000>,
51 <1312500 1000000>,
52 <1125000 1000000>,
53 < 937500 1000000>,
54 < 750000 1000000>,
55 < 375000 1000000>;
56 next-level-cache = <&L2_CA15>;
57 };
58
59 L2_CA15: cache-controller@0 {
60 compatible = "cache";
61 reg = <0>;
62 power-domains = <&sysc R8A7793_PD_CA15_SCU>;
63 cache-unified;
64 cache-level = <2>;
65 };
66 };
67
68 thermal-zones {
69 cpu_thermal: cpu-thermal {
70 polling-delay-passive = <0>;
71 polling-delay = <0>;
72
73 thermal-sensors = <&thermal>;
74
75 trips {
76 cpu-crit {
77 temperature = <115000>;
78 hysteresis = <0>;
79 type = "critical";
80 };
81 };
82 cooling-maps {
83 };
84 };
85 };
86
87 gic: interrupt-controller@f1001000 {
88 compatible = "arm,gic-400";
89 #interrupt-cells = <3>;
90 #address-cells = <0>;
91 interrupt-controller;
92 reg = <0 0xf1001000 0 0x1000>,
93 <0 0xf1002000 0 0x1000>,
94 <0 0xf1004000 0 0x2000>,
95 <0 0xf1006000 0 0x2000>;
96 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
97 };
98
99 gpio0: gpio@e6050000 {
100 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
101 reg = <0 0xe6050000 0 0x50>;
102 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
103 #gpio-cells = <2>;
104 gpio-controller;
105 gpio-ranges = <&pfc 0 0 32>;
106 #interrupt-cells = <2>;
107 interrupt-controller;
108 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
109 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
110 };
111
112 gpio1: gpio@e6051000 {
113 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
114 reg = <0 0xe6051000 0 0x50>;
115 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
116 #gpio-cells = <2>;
117 gpio-controller;
118 gpio-ranges = <&pfc 0 32 26>;
119 #interrupt-cells = <2>;
120 interrupt-controller;
121 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
122 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
123 };
124
125 gpio2: gpio@e6052000 {
126 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
127 reg = <0 0xe6052000 0 0x50>;
128 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
129 #gpio-cells = <2>;
130 gpio-controller;
131 gpio-ranges = <&pfc 0 64 32>;
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
135 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
136 };
137
138 gpio3: gpio@e6053000 {
139 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
140 reg = <0 0xe6053000 0 0x50>;
141 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
142 #gpio-cells = <2>;
143 gpio-controller;
144 gpio-ranges = <&pfc 0 96 32>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
147 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
148 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
149 };
150
151 gpio4: gpio@e6054000 {
152 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
153 reg = <0 0xe6054000 0 0x50>;
154 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
155 #gpio-cells = <2>;
156 gpio-controller;
157 gpio-ranges = <&pfc 0 128 32>;
158 #interrupt-cells = <2>;
159 interrupt-controller;
160 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
161 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
162 };
163
164 gpio5: gpio@e6055000 {
165 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
166 reg = <0 0xe6055000 0 0x50>;
167 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
168 #gpio-cells = <2>;
169 gpio-controller;
170 gpio-ranges = <&pfc 0 160 32>;
171 #interrupt-cells = <2>;
172 interrupt-controller;
173 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
174 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
175 };
176
177 gpio6: gpio@e6055400 {
178 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
179 reg = <0 0xe6055400 0 0x50>;
180 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
181 #gpio-cells = <2>;
182 gpio-controller;
183 gpio-ranges = <&pfc 0 192 32>;
184 #interrupt-cells = <2>;
185 interrupt-controller;
186 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
187 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
188 };
189
190 gpio7: gpio@e6055800 {
191 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
192 reg = <0 0xe6055800 0 0x50>;
193 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
194 #gpio-cells = <2>;
195 gpio-controller;
196 gpio-ranges = <&pfc 0 224 26>;
197 #interrupt-cells = <2>;
198 interrupt-controller;
199 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
200 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
201 };
202
203 thermal: thermal@e61f0000 {
204 compatible = "renesas,thermal-r8a7793",
205 "renesas,rcar-gen2-thermal",
206 "renesas,rcar-thermal";
207 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
208 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
210 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
211 #thermal-sensor-cells = <0>;
212 };
213
214 timer {
215 compatible = "arm,armv7-timer";
216 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
217 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
218 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
219 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
220 };
221
222 cmt0: timer@ffca0000 {
223 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
224 reg = <0 0xffca0000 0 0x1004>;
225 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
228 clock-names = "fck";
229 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
230
231 renesas,channels-mask = <0x60>;
232
233 status = "disabled";
234 };
235
236 cmt1: timer@e6130000 {
237 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
238 reg = <0 0xe6130000 0 0x1004>;
239 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
248 clock-names = "fck";
249 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
250
251 renesas,channels-mask = <0xff>;
252
253 status = "disabled";
254 };
255
256 irqc0: interrupt-controller@e61c0000 {
257 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
258 #interrupt-cells = <2>;
259 interrupt-controller;
260 reg = <0 0xe61c0000 0 0x200>;
261 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
272 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
273 };
274
275 dmac0: dma-controller@e6700000 {
276 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
277 reg = <0 0xe6700000 0 0x20000>;
278 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
280 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
282 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
283 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
284 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
285 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
286 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
287 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
288 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
289 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
290 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
291 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
292 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
293 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
294 interrupt-names = "error",
295 "ch0", "ch1", "ch2", "ch3",
296 "ch4", "ch5", "ch6", "ch7",
297 "ch8", "ch9", "ch10", "ch11",
298 "ch12", "ch13", "ch14";
299 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
300 clock-names = "fck";
301 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
302 #dma-cells = <1>;
303 dma-channels = <15>;
304 };
305
306 dmac1: dma-controller@e6720000 {
307 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
308 reg = <0 0xe6720000 0 0x20000>;
309 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
312 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
313 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-names = "error",
326 "ch0", "ch1", "ch2", "ch3",
327 "ch4", "ch5", "ch6", "ch7",
328 "ch8", "ch9", "ch10", "ch11",
329 "ch12", "ch13", "ch14";
330 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
331 clock-names = "fck";
332 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
333 #dma-cells = <1>;
334 dma-channels = <15>;
335 };
336
337 audma0: dma-controller@ec700000 {
338 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
339 reg = <0 0xec700000 0 0x10000>;
340 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
354 interrupt-names = "error",
355 "ch0", "ch1", "ch2", "ch3",
356 "ch4", "ch5", "ch6", "ch7",
357 "ch8", "ch9", "ch10", "ch11",
358 "ch12";
359 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
360 clock-names = "fck";
361 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
362 #dma-cells = <1>;
363 dma-channels = <13>;
364 };
365
366 audma1: dma-controller@ec720000 {
367 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
368 reg = <0 0xec720000 0 0x10000>;
369 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
383 interrupt-names = "error",
384 "ch0", "ch1", "ch2", "ch3",
385 "ch4", "ch5", "ch6", "ch7",
386 "ch8", "ch9", "ch10", "ch11",
387 "ch12";
388 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
389 clock-names = "fck";
390 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
391 #dma-cells = <1>;
392 dma-channels = <13>;
393 };
394
395 /* The memory map in the User's Manual maps the cores to bus numbers */
396 i2c0: i2c@e6508000 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 compatible = "renesas,i2c-r8a7793";
400 reg = <0 0xe6508000 0 0x40>;
401 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
403 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
404 i2c-scl-internal-delay-ns = <6>;
405 status = "disabled";
406 };
407
408 i2c1: i2c@e6518000 {
409 #address-cells = <1>;
410 #size-cells = <0>;
411 compatible = "renesas,i2c-r8a7793";
412 reg = <0 0xe6518000 0 0x40>;
413 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
415 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
416 i2c-scl-internal-delay-ns = <6>;
417 status = "disabled";
418 };
419
420 i2c2: i2c@e6530000 {
421 #address-cells = <1>;
422 #size-cells = <0>;
423 compatible = "renesas,i2c-r8a7793";
424 reg = <0 0xe6530000 0 0x40>;
425 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
427 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
428 i2c-scl-internal-delay-ns = <6>;
429 status = "disabled";
430 };
431
432 i2c3: i2c@e6540000 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 compatible = "renesas,i2c-r8a7793";
436 reg = <0 0xe6540000 0 0x40>;
437 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
439 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
440 i2c-scl-internal-delay-ns = <6>;
441 status = "disabled";
442 };
443
444 i2c4: i2c@e6520000 {
445 #address-cells = <1>;
446 #size-cells = <0>;
447 compatible = "renesas,i2c-r8a7793";
448 reg = <0 0xe6520000 0 0x40>;
449 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
451 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
452 i2c-scl-internal-delay-ns = <6>;
453 status = "disabled";
454 };
455
456 i2c5: i2c@e6528000 {
457 /* doesn't need pinmux */
458 #address-cells = <1>;
459 #size-cells = <0>;
460 compatible = "renesas,i2c-r8a7793";
461 reg = <0 0xe6528000 0 0x40>;
462 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
464 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
465 i2c-scl-internal-delay-ns = <110>;
466 status = "disabled";
467 };
468
469 i2c6: i2c@e60b0000 {
470 /* doesn't need pinmux */
471 #address-cells = <1>;
472 #size-cells = <0>;
473 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
474 reg = <0 0xe60b0000 0 0x425>;
475 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
477 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
478 <&dmac1 0x77>, <&dmac1 0x78>;
479 dma-names = "tx", "rx", "tx", "rx";
480 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
481 status = "disabled";
482 };
483
484 i2c7: i2c@e6500000 {
485 #address-cells = <1>;
486 #size-cells = <0>;
487 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
488 reg = <0 0xe6500000 0 0x425>;
489 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
491 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
492 <&dmac1 0x61>, <&dmac1 0x62>;
493 dma-names = "tx", "rx", "tx", "rx";
494 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
495 status = "disabled";
496 };
497
498 i2c8: i2c@e6510000 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
502 reg = <0 0xe6510000 0 0x425>;
503 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
505 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
506 <&dmac1 0x65>, <&dmac1 0x66>;
507 dma-names = "tx", "rx", "tx", "rx";
508 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
509 status = "disabled";
510 };
511
512 pfc: pfc@e6060000 {
513 compatible = "renesas,pfc-r8a7793";
514 reg = <0 0xe6060000 0 0x250>;
515 };
516
517 sdhi0: sd@ee100000 {
518 compatible = "renesas,sdhi-r8a7793";
519 reg = <0 0xee100000 0 0x328>;
520 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
522 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
523 <&dmac1 0xcd>, <&dmac1 0xce>;
524 dma-names = "tx", "rx", "tx", "rx";
525 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
526 status = "disabled";
527 };
528
529 sdhi1: sd@ee140000 {
530 compatible = "renesas,sdhi-r8a7793";
531 reg = <0 0xee140000 0 0x100>;
532 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
534 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
535 <&dmac1 0xc1>, <&dmac1 0xc2>;
536 dma-names = "tx", "rx", "tx", "rx";
537 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
538 status = "disabled";
539 };
540
541 sdhi2: sd@ee160000 {
542 compatible = "renesas,sdhi-r8a7793";
543 reg = <0 0xee160000 0 0x100>;
544 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
546 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
547 <&dmac1 0xd3>, <&dmac1 0xd4>;
548 dma-names = "tx", "rx", "tx", "rx";
549 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
550 status = "disabled";
551 };
552
553 mmcif0: mmc@ee200000 {
554 compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
555 reg = <0 0xee200000 0 0x80>;
556 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
558 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
559 <&dmac1 0xd1>, <&dmac1 0xd2>;
560 dma-names = "tx", "rx", "tx", "rx";
561 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
562 reg-io-width = <4>;
563 status = "disabled";
564 max-frequency = <97500000>;
565 };
566
567 scifa0: serial@e6c40000 {
568 compatible = "renesas,scifa-r8a7793",
569 "renesas,rcar-gen2-scifa", "renesas,scifa";
570 reg = <0 0xe6c40000 0 64>;
571 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
573 clock-names = "fck";
574 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
575 <&dmac1 0x21>, <&dmac1 0x22>;
576 dma-names = "tx", "rx", "tx", "rx";
577 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
578 status = "disabled";
579 };
580
581 scifa1: serial@e6c50000 {
582 compatible = "renesas,scifa-r8a7793",
583 "renesas,rcar-gen2-scifa", "renesas,scifa";
584 reg = <0 0xe6c50000 0 64>;
585 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
587 clock-names = "fck";
588 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
589 <&dmac1 0x25>, <&dmac1 0x26>;
590 dma-names = "tx", "rx", "tx", "rx";
591 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
592 status = "disabled";
593 };
594
595 scifa2: serial@e6c60000 {
596 compatible = "renesas,scifa-r8a7793",
597 "renesas,rcar-gen2-scifa", "renesas,scifa";
598 reg = <0 0xe6c60000 0 64>;
599 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
601 clock-names = "fck";
602 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
603 <&dmac1 0x27>, <&dmac1 0x28>;
604 dma-names = "tx", "rx", "tx", "rx";
605 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
606 status = "disabled";
607 };
608
609 scifa3: serial@e6c70000 {
610 compatible = "renesas,scifa-r8a7793",
611 "renesas,rcar-gen2-scifa", "renesas,scifa";
612 reg = <0 0xe6c70000 0 64>;
613 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
615 clock-names = "fck";
616 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
617 <&dmac1 0x1b>, <&dmac1 0x1c>;
618 dma-names = "tx", "rx", "tx", "rx";
619 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
620 status = "disabled";
621 };
622
623 scifa4: serial@e6c78000 {
624 compatible = "renesas,scifa-r8a7793",
625 "renesas,rcar-gen2-scifa", "renesas,scifa";
626 reg = <0 0xe6c78000 0 64>;
627 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
629 clock-names = "fck";
630 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
631 <&dmac1 0x1f>, <&dmac1 0x20>;
632 dma-names = "tx", "rx", "tx", "rx";
633 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
634 status = "disabled";
635 };
636
637 scifa5: serial@e6c80000 {
638 compatible = "renesas,scifa-r8a7793",
639 "renesas,rcar-gen2-scifa", "renesas,scifa";
640 reg = <0 0xe6c80000 0 64>;
641 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
643 clock-names = "fck";
644 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
645 <&dmac1 0x23>, <&dmac1 0x24>;
646 dma-names = "tx", "rx", "tx", "rx";
647 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
648 status = "disabled";
649 };
650
651 scifb0: serial@e6c20000 {
652 compatible = "renesas,scifb-r8a7793",
653 "renesas,rcar-gen2-scifb", "renesas,scifb";
654 reg = <0 0xe6c20000 0 64>;
655 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
657 clock-names = "fck";
658 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
659 <&dmac1 0x3d>, <&dmac1 0x3e>;
660 dma-names = "tx", "rx", "tx", "rx";
661 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
662 status = "disabled";
663 };
664
665 scifb1: serial@e6c30000 {
666 compatible = "renesas,scifb-r8a7793",
667 "renesas,rcar-gen2-scifb", "renesas,scifb";
668 reg = <0 0xe6c30000 0 64>;
669 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
671 clock-names = "fck";
672 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
673 <&dmac1 0x19>, <&dmac1 0x1a>;
674 dma-names = "tx", "rx", "tx", "rx";
675 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
676 status = "disabled";
677 };
678
679 scifb2: serial@e6ce0000 {
680 compatible = "renesas,scifb-r8a7793",
681 "renesas,rcar-gen2-scifb", "renesas,scifb";
682 reg = <0 0xe6ce0000 0 64>;
683 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
685 clock-names = "fck";
686 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
687 <&dmac1 0x1d>, <&dmac1 0x1e>;
688 dma-names = "tx", "rx", "tx", "rx";
689 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
690 status = "disabled";
691 };
692
693 scif0: serial@e6e60000 {
694 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
695 "renesas,scif";
696 reg = <0 0xe6e60000 0 64>;
697 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
699 <&scif_clk>;
700 clock-names = "fck", "brg_int", "scif_clk";
701 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
702 <&dmac1 0x29>, <&dmac1 0x2a>;
703 dma-names = "tx", "rx", "tx", "rx";
704 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
705 status = "disabled";
706 };
707
708 scif1: serial@e6e68000 {
709 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
710 "renesas,scif";
711 reg = <0 0xe6e68000 0 64>;
712 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
714 <&scif_clk>;
715 clock-names = "fck", "brg_int", "scif_clk";
716 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
717 <&dmac1 0x2d>, <&dmac1 0x2e>;
718 dma-names = "tx", "rx", "tx", "rx";
719 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
720 status = "disabled";
721 };
722
723 scif2: serial@e6e58000 {
724 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
725 "renesas,scif";
726 reg = <0 0xe6e58000 0 64>;
727 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
729 <&scif_clk>;
730 clock-names = "fck", "brg_int", "scif_clk";
731 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
732 <&dmac1 0x2b>, <&dmac1 0x2c>;
733 dma-names = "tx", "rx", "tx", "rx";
734 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
735 status = "disabled";
736 };
737
738 scif3: serial@e6ea8000 {
739 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
740 "renesas,scif";
741 reg = <0 0xe6ea8000 0 64>;
742 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
744 <&scif_clk>;
745 clock-names = "fck", "brg_int", "scif_clk";
746 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
747 <&dmac1 0x2f>, <&dmac1 0x30>;
748 dma-names = "tx", "rx", "tx", "rx";
749 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
750 status = "disabled";
751 };
752
753 scif4: serial@e6ee0000 {
754 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
755 "renesas,scif";
756 reg = <0 0xe6ee0000 0 64>;
757 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
759 <&scif_clk>;
760 clock-names = "fck", "brg_int", "scif_clk";
761 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
762 <&dmac1 0xfb>, <&dmac1 0xfc>;
763 dma-names = "tx", "rx", "tx", "rx";
764 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
765 status = "disabled";
766 };
767
768 scif5: serial@e6ee8000 {
769 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
770 "renesas,scif";
771 reg = <0 0xe6ee8000 0 64>;
772 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
774 <&scif_clk>;
775 clock-names = "fck", "brg_int", "scif_clk";
776 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
777 <&dmac1 0xfd>, <&dmac1 0xfe>;
778 dma-names = "tx", "rx", "tx", "rx";
779 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
780 status = "disabled";
781 };
782
783 hscif0: serial@e62c0000 {
784 compatible = "renesas,hscif-r8a7793",
785 "renesas,rcar-gen2-hscif", "renesas,hscif";
786 reg = <0 0xe62c0000 0 96>;
787 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
789 <&scif_clk>;
790 clock-names = "fck", "brg_int", "scif_clk";
791 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
792 <&dmac1 0x39>, <&dmac1 0x3a>;
793 dma-names = "tx", "rx", "tx", "rx";
794 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
795 status = "disabled";
796 };
797
798 hscif1: serial@e62c8000 {
799 compatible = "renesas,hscif-r8a7793",
800 "renesas,rcar-gen2-hscif", "renesas,hscif";
801 reg = <0 0xe62c8000 0 96>;
802 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
804 <&scif_clk>;
805 clock-names = "fck", "brg_int", "scif_clk";
806 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
807 <&dmac1 0x4d>, <&dmac1 0x4e>;
808 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
810 status = "disabled";
811 };
812
813 hscif2: serial@e62d0000 {
814 compatible = "renesas,hscif-r8a7793",
815 "renesas,rcar-gen2-hscif", "renesas,hscif";
816 reg = <0 0xe62d0000 0 96>;
817 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
819 <&scif_clk>;
820 clock-names = "fck", "brg_int", "scif_clk";
821 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
822 <&dmac1 0x3b>, <&dmac1 0x3c>;
823 dma-names = "tx", "rx", "tx", "rx";
824 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
825 status = "disabled";
826 };
827
828 ether: ethernet@ee700000 {
829 compatible = "renesas,ether-r8a7793";
830 reg = <0 0xee700000 0 0x400>;
831 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
833 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
834 phy-mode = "rmii";
835 #address-cells = <1>;
836 #size-cells = <0>;
837 status = "disabled";
838 };
839
840 qspi: spi@e6b10000 {
841 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
842 reg = <0 0xe6b10000 0 0x2c>;
843 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
845 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
846 <&dmac1 0x17>, <&dmac1 0x18>;
847 dma-names = "tx", "rx", "tx", "rx";
848 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
849 num-cs = <1>;
850 #address-cells = <1>;
851 #size-cells = <0>;
852 status = "disabled";
853 };
854
855 du: display@feb00000 {
856 compatible = "renesas,du-r8a7793";
857 reg = <0 0xfeb00000 0 0x40000>,
858 <0 0xfeb90000 0 0x1c>;
859 reg-names = "du", "lvds.0";
860 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
861 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
863 <&mstp7_clks R8A7793_CLK_DU1>,
864 <&mstp7_clks R8A7793_CLK_LVDS0>;
865 clock-names = "du.0", "du.1", "lvds.0";
866 status = "disabled";
867
868 ports {
869 #address-cells = <1>;
870 #size-cells = <0>;
871
872 port@0 {
873 reg = <0>;
874 du_out_rgb: endpoint {
875 };
876 };
877 port@1 {
878 reg = <1>;
879 du_out_lvds0: endpoint {
880 };
881 };
882 };
883 };
884
885 can0: can@e6e80000 {
886 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
887 reg = <0 0xe6e80000 0 0x1000>;
888 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
890 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
891 clock-names = "clkp1", "clkp2", "can_clk";
892 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
893 status = "disabled";
894 };
895
896 can1: can@e6e88000 {
897 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
898 reg = <0 0xe6e88000 0 0x1000>;
899 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
901 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
902 clock-names = "clkp1", "clkp2", "can_clk";
903 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
904 status = "disabled";
905 };
906
907 clocks {
908 #address-cells = <2>;
909 #size-cells = <2>;
910 ranges;
911
912 /* External root clock */
913 extal_clk: extal {
914 compatible = "fixed-clock";
915 #clock-cells = <0>;
916 /* This value must be overridden by the board. */
917 clock-frequency = <0>;
918 };
919
920 /*
921 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
922 * default. Boards that provide audio clocks should override them.
923 */
924 audio_clk_a: audio_clk_a {
925 compatible = "fixed-clock";
926 #clock-cells = <0>;
927 clock-frequency = <0>;
928 };
929 audio_clk_b: audio_clk_b {
930 compatible = "fixed-clock";
931 #clock-cells = <0>;
932 clock-frequency = <0>;
933 };
934 audio_clk_c: audio_clk_c {
935 compatible = "fixed-clock";
936 #clock-cells = <0>;
937 clock-frequency = <0>;
938 };
939
940 /* External USB clock - can be overridden by the board */
941 usb_extal_clk: usb_extal {
942 compatible = "fixed-clock";
943 #clock-cells = <0>;
944 clock-frequency = <48000000>;
945 };
946
947 /* External CAN clock */
948 can_clk: can {
949 compatible = "fixed-clock";
950 #clock-cells = <0>;
951 /* This value must be overridden by the board. */
952 clock-frequency = <0>;
953 };
954
955 /* External SCIF clock */
956 scif_clk: scif {
957 compatible = "fixed-clock";
958 #clock-cells = <0>;
959 /* This value must be overridden by the board. */
960 clock-frequency = <0>;
961 };
962
963 /* Special CPG clocks */
964 cpg_clocks: cpg_clocks@e6150000 {
965 compatible = "renesas,r8a7793-cpg-clocks",
966 "renesas,rcar-gen2-cpg-clocks";
967 reg = <0 0xe6150000 0 0x1000>;
968 clocks = <&extal_clk &usb_extal_clk>;
969 #clock-cells = <1>;
970 clock-output-names = "main", "pll0", "pll1", "pll3",
971 "lb", "qspi", "sdh", "sd0", "z",
972 "rcan", "adsp";
973 #power-domain-cells = <0>;
974 };
975
976 /* Variable factor clocks */
977 sd2_clk: sd2@e6150078 {
978 compatible = "renesas,r8a7793-div6-clock",
979 "renesas,cpg-div6-clock";
980 reg = <0 0xe6150078 0 4>;
981 clocks = <&pll1_div2_clk>;
982 #clock-cells = <0>;
983 };
984 sd3_clk: sd3@e615026c {
985 compatible = "renesas,r8a7793-div6-clock",
986 "renesas,cpg-div6-clock";
987 reg = <0 0xe615026c 0 4>;
988 clocks = <&pll1_div2_clk>;
989 #clock-cells = <0>;
990 };
991 mmc0_clk: mmc0@e6150240 {
992 compatible = "renesas,r8a7793-div6-clock",
993 "renesas,cpg-div6-clock";
994 reg = <0 0xe6150240 0 4>;
995 clocks = <&pll1_div2_clk>;
996 #clock-cells = <0>;
997 };
998
999 /* Fixed factor clocks */
1000 pll1_div2_clk: pll1_div2 {
1001 compatible = "fixed-factor-clock";
1002 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1003 #clock-cells = <0>;
1004 clock-div = <2>;
1005 clock-mult = <1>;
1006 };
1007 zg_clk: zg {
1008 compatible = "fixed-factor-clock";
1009 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1010 #clock-cells = <0>;
1011 clock-div = <5>;
1012 clock-mult = <1>;
1013 };
1014 zx_clk: zx {
1015 compatible = "fixed-factor-clock";
1016 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1017 #clock-cells = <0>;
1018 clock-div = <3>;
1019 clock-mult = <1>;
1020 };
1021 zs_clk: zs {
1022 compatible = "fixed-factor-clock";
1023 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1024 #clock-cells = <0>;
1025 clock-div = <6>;
1026 clock-mult = <1>;
1027 };
1028 hp_clk: hp {
1029 compatible = "fixed-factor-clock";
1030 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1031 #clock-cells = <0>;
1032 clock-div = <12>;
1033 clock-mult = <1>;
1034 };
1035 p_clk: p {
1036 compatible = "fixed-factor-clock";
1037 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1038 #clock-cells = <0>;
1039 clock-div = <24>;
1040 clock-mult = <1>;
1041 };
1042 m2_clk: m2 {
1043 compatible = "fixed-factor-clock";
1044 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1045 #clock-cells = <0>;
1046 clock-div = <8>;
1047 clock-mult = <1>;
1048 };
1049 rclk_clk: rclk {
1050 compatible = "fixed-factor-clock";
1051 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1052 #clock-cells = <0>;
1053 clock-div = <(48 * 1024)>;
1054 clock-mult = <1>;
1055 };
1056 mp_clk: mp {
1057 compatible = "fixed-factor-clock";
1058 clocks = <&pll1_div2_clk>;
1059 #clock-cells = <0>;
1060 clock-div = <15>;
1061 clock-mult = <1>;
1062 };
1063 cp_clk: cp {
1064 compatible = "fixed-factor-clock";
1065 clocks = <&extal_clk>;
1066 #clock-cells = <0>;
1067 clock-div = <2>;
1068 clock-mult = <1>;
1069 };
1070
1071 /* Gate clocks */
1072 mstp1_clks: mstp1_clks@e6150134 {
1073 compatible = "renesas,r8a7793-mstp-clocks",
1074 "renesas,cpg-mstp-clocks";
1075 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1076 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1077 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
1078 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1079 <&zs_clk>, <&zs_clk>, <&zs_clk>;
1080 #clock-cells = <1>;
1081 clock-indices = <
1082 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
1083 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
1084 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
1085 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
1086 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
1087 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
1088 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
1089 R8A7793_CLK_VSP1_S
1090 >;
1091 clock-output-names =
1092 "vcp0", "vpc0", "ssp_dev", "tmu1",
1093 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
1094 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
1095 "vsp1-du0", "vsps";
1096 };
1097 mstp2_clks: mstp2_clks@e6150138 {
1098 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1099 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1100 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1101 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
1102 #clock-cells = <1>;
1103 clock-indices = <
1104 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
1105 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
1106 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
1107 >;
1108 clock-output-names =
1109 "scifa2", "scifa1", "scifa0", "scifb0",
1110 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1111 };
1112 mstp3_clks: mstp3_clks@e615013c {
1113 compatible = "renesas,r8a7793-mstp-clocks",
1114 "renesas,cpg-mstp-clocks";
1115 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1116 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1117 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1118 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1119 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1120 #clock-cells = <1>;
1121 clock-indices = <
1122 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1123 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1124 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1125 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1126 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1127 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1128 >;
1129 clock-output-names =
1130 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1131 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1132 "usbdmac0", "usbdmac1";
1133 };
1134 mstp4_clks: mstp4_clks@e6150140 {
1135 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1136 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1137 clocks = <&cp_clk>;
1138 #clock-cells = <1>;
1139 clock-indices = <R8A7793_CLK_IRQC>;
1140 clock-output-names = "irqc";
1141 };
1142 mstp5_clks: mstp5_clks@e6150144 {
1143 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1144 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1145 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1146 #clock-cells = <1>;
1147 clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1148 R8A7793_CLK_THERMAL>;
1149 clock-output-names = "audmac0", "audmac1", "thermal";
1150 };
1151 mstp7_clks: mstp7_clks@e615014c {
1152 compatible = "renesas,r8a7793-mstp-clocks",
1153 "renesas,cpg-mstp-clocks";
1154 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1155 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
1156 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1157 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1158 <&zx_clk>, <&zx_clk>;
1159 #clock-cells = <1>;
1160 clock-indices = <
1161 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1162 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1163 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1164 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1165 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1166 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1167 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1168 >;
1169 clock-output-names =
1170 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1171 "hscif1", "hscif0", "scif3", "scif2",
1172 "scif1", "scif0", "du1", "du0", "lvds0";
1173 };
1174 mstp8_clks: mstp8_clks@e6150990 {
1175 compatible = "renesas,r8a7793-mstp-clocks",
1176 "renesas,cpg-mstp-clocks";
1177 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1178 clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1179 <&p_clk>, <&zs_clk>, <&zs_clk>;
1180 #clock-cells = <1>;
1181 clock-indices = <
1182 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1183 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1184 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1185 R8A7793_CLK_SATA0
1186 >;
1187 clock-output-names =
1188 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1189 "sata1", "sata0";
1190 };
1191 mstp9_clks: mstp9_clks@e6150994 {
1192 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1193 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1194 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1195 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1196 <&p_clk>, <&p_clk>,
1197 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1198 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1199 <&hp_clk>, <&hp_clk>;
1200 #clock-cells = <1>;
1201 clock-indices = <
1202 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1203 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1204 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1205 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1206 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
1207 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
1208 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1209 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1210 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1211 >;
1212 clock-output-names =
1213 "gpio7", "gpio6", "gpio5", "gpio4",
1214 "gpio3", "gpio2", "gpio1", "gpio0",
1215 "rcan1", "rcan0", "qspi_mod", "i2c5",
1216 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
1217 "i2c0";
1218 };
1219 mstp10_clks: mstp10_clks@e6150998 {
1220 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1221 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1222 clocks = <&p_clk>,
1223 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1224 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1225 <&p_clk>,
1226 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1227 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1228 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1229 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1230 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1231 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1232 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1233
1234 #clock-cells = <1>;
1235 clock-indices = <
1236 R8A7793_CLK_SSI_ALL
1237 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1238 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1239 R8A7793_CLK_SCU_ALL
1240 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1241 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1242 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1243 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1244 >;
1245 clock-output-names =
1246 "ssi-all",
1247 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1248 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1249 "scu-all",
1250 "scu-dvc1", "scu-dvc0",
1251 "scu-ctu1-mix1", "scu-ctu0-mix0",
1252 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1253 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1254 };
1255 mstp11_clks: mstp11_clks@e615099c {
1256 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1257 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1258 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1259 #clock-cells = <1>;
1260 clock-indices = <
1261 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1262 >;
1263 clock-output-names = "scifa3", "scifa4", "scifa5";
1264 };
1265 };
1266
1267 sysc: system-controller@e6180000 {
1268 compatible = "renesas,r8a7793-sysc";
1269 reg = <0 0xe6180000 0 0x0200>;
1270 #power-domain-cells = <1>;
1271 };
1272
1273 ipmmu_sy0: mmu@e6280000 {
1274 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1275 reg = <0 0xe6280000 0 0x1000>;
1276 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1278 #iommu-cells = <1>;
1279 status = "disabled";
1280 };
1281
1282 ipmmu_sy1: mmu@e6290000 {
1283 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1284 reg = <0 0xe6290000 0 0x1000>;
1285 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1286 #iommu-cells = <1>;
1287 status = "disabled";
1288 };
1289
1290 ipmmu_ds: mmu@e6740000 {
1291 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1292 reg = <0 0xe6740000 0 0x1000>;
1293 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1295 #iommu-cells = <1>;
1296 status = "disabled";
1297 };
1298
1299 ipmmu_mp: mmu@ec680000 {
1300 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1301 reg = <0 0xec680000 0 0x1000>;
1302 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1303 #iommu-cells = <1>;
1304 status = "disabled";
1305 };
1306
1307 ipmmu_mx: mmu@fe951000 {
1308 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1309 reg = <0 0xfe951000 0 0x1000>;
1310 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1312 #iommu-cells = <1>;
1313 status = "disabled";
1314 };
1315
1316 ipmmu_rt: mmu@ffc80000 {
1317 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1318 reg = <0 0xffc80000 0 0x1000>;
1319 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1320 #iommu-cells = <1>;
1321 status = "disabled";
1322 };
1323
1324 ipmmu_gp: mmu@e62a0000 {
1325 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1326 reg = <0 0xe62a0000 0 0x1000>;
1327 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1329 #iommu-cells = <1>;
1330 status = "disabled";
1331 };
1332
1333 rcar_sound: sound@ec500000 {
1334 /*
1335 * #sound-dai-cells is required
1336 *
1337 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1338 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1339 */
1340 compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1341 reg = <0 0xec500000 0 0x1000>, /* SCU */
1342 <0 0xec5a0000 0 0x100>, /* ADG */
1343 <0 0xec540000 0 0x1000>, /* SSIU */
1344 <0 0xec541000 0 0x280>, /* SSI */
1345 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1346 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1347
1348 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1349 <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1350 <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1351 <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1352 <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1353 <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1354 <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1355 <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1356 <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1357 <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1358 <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1359 <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1360 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1361 clock-names = "ssi-all",
1362 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1363 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1364 "src.9", "src.8", "src.7", "src.6", "src.5",
1365 "src.4", "src.3", "src.2", "src.1", "src.0",
1366 "dvc.0", "dvc.1",
1367 "clk_a", "clk_b", "clk_c", "clk_i";
1368 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1369
1370 status = "disabled";
1371
1372 rcar_sound,dvc {
1373 dvc0: dvc-0 {
1374 dmas = <&audma0 0xbc>;
1375 dma-names = "tx";
1376 };
1377 dvc1: dvc-1 {
1378 dmas = <&audma0 0xbe>;
1379 dma-names = "tx";
1380 };
1381 };
1382
1383 rcar_sound,src {
1384 src0: src-0 {
1385 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1386 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1387 dma-names = "rx", "tx";
1388 };
1389 src1: src-1 {
1390 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1391 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1392 dma-names = "rx", "tx";
1393 };
1394 src2: src-2 {
1395 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1396 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1397 dma-names = "rx", "tx";
1398 };
1399 src3: src-3 {
1400 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1401 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1402 dma-names = "rx", "tx";
1403 };
1404 src4: src-4 {
1405 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1406 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1407 dma-names = "rx", "tx";
1408 };
1409 src5: src-5 {
1410 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1411 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1412 dma-names = "rx", "tx";
1413 };
1414 src6: src-6 {
1415 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1416 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1417 dma-names = "rx", "tx";
1418 };
1419 src7: src-7 {
1420 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1421 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1422 dma-names = "rx", "tx";
1423 };
1424 src8: src-8 {
1425 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1426 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1427 dma-names = "rx", "tx";
1428 };
1429 src9: src-9 {
1430 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1431 dmas = <&audma0 0x97>, <&audma1 0xba>;
1432 dma-names = "rx", "tx";
1433 };
1434 };
1435
1436 rcar_sound,ssi {
1437 ssi0: ssi-0 {
1438 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1439 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1440 dma-names = "rx", "tx", "rxu", "txu";
1441 };
1442 ssi1: ssi-1 {
1443 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1444 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1445 dma-names = "rx", "tx", "rxu", "txu";
1446 };
1447 ssi2: ssi-2 {
1448 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1449 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1450 dma-names = "rx", "tx", "rxu", "txu";
1451 };
1452 ssi3: ssi-3 {
1453 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1454 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1455 dma-names = "rx", "tx", "rxu", "txu";
1456 };
1457 ssi4: ssi-4 {
1458 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1460 dma-names = "rx", "tx", "rxu", "txu";
1461 };
1462 ssi5: ssi-5 {
1463 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1464 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1465 dma-names = "rx", "tx", "rxu", "txu";
1466 };
1467 ssi6: ssi-6 {
1468 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1469 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1470 dma-names = "rx", "tx", "rxu", "txu";
1471 };
1472 ssi7: ssi-7 {
1473 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1474 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1475 dma-names = "rx", "tx", "rxu", "txu";
1476 };
1477 ssi8: ssi-8 {
1478 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1479 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1480 dma-names = "rx", "tx", "rxu", "txu";
1481 };
1482 ssi9: ssi-9 {
1483 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1484 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1485 dma-names = "rx", "tx", "rxu", "txu";
1486 };
1487 };
1488 };
1489 };
Linux kernel - Deliverables
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