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Merge tag 'at91-dt3' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux...
[deliverable/linux.git] / arch / arm / boot / dts / r8a7793.dtsi
1 /*
2 * Device Tree Source for the r8a7793 SoC
3 *
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11 #include <dt-bindings/clock/r8a7793-clock.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14
15 / {
16 compatible = "renesas,r8a7793";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
28 i2c6 = &i2c6;
29 i2c7 = &i2c7;
30 i2c8 = &i2c8;
31 spi0 = &qspi;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a15";
41 reg = <0>;
42 clock-frequency = <1500000000>;
43 voltage-tolerance = <1>; /* 1% */
44 clocks = <&cpg_clocks R8A7793_CLK_Z>;
45 clock-latency = <300000>; /* 300 us */
46
47 /* kHz - uV - OPPs unknown yet */
48 operating-points = <1500000 1000000>,
49 <1312500 1000000>,
50 <1125000 1000000>,
51 < 937500 1000000>,
52 < 750000 1000000>,
53 < 375000 1000000>;
54 next-level-cache = <&L2_CA15>;
55 };
56 };
57
58 thermal-zones {
59 cpu_thermal: cpu-thermal {
60 polling-delay-passive = <0>;
61 polling-delay = <0>;
62
63 thermal-sensors = <&thermal>;
64
65 trips {
66 cpu-crit {
67 temperature = <115000>;
68 hysteresis = <0>;
69 type = "critical";
70 };
71 };
72 cooling-maps {
73 };
74 };
75 };
76
77 L2_CA15: cache-controller@0 {
78 compatible = "cache";
79 cache-unified;
80 cache-level = <2>;
81 };
82
83 gic: interrupt-controller@f1001000 {
84 compatible = "arm,gic-400";
85 #interrupt-cells = <3>;
86 #address-cells = <0>;
87 interrupt-controller;
88 reg = <0 0xf1001000 0 0x1000>,
89 <0 0xf1002000 0 0x1000>,
90 <0 0xf1004000 0 0x2000>,
91 <0 0xf1006000 0 0x2000>;
92 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
93 };
94
95 gpio0: gpio@e6050000 {
96 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
97 reg = <0 0xe6050000 0 0x50>;
98 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
99 #gpio-cells = <2>;
100 gpio-controller;
101 gpio-ranges = <&pfc 0 0 32>;
102 #interrupt-cells = <2>;
103 interrupt-controller;
104 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
105 power-domains = <&cpg_clocks>;
106 };
107
108 gpio1: gpio@e6051000 {
109 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
110 reg = <0 0xe6051000 0 0x50>;
111 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
112 #gpio-cells = <2>;
113 gpio-controller;
114 gpio-ranges = <&pfc 0 32 26>;
115 #interrupt-cells = <2>;
116 interrupt-controller;
117 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
118 power-domains = <&cpg_clocks>;
119 };
120
121 gpio2: gpio@e6052000 {
122 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
123 reg = <0 0xe6052000 0 0x50>;
124 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
125 #gpio-cells = <2>;
126 gpio-controller;
127 gpio-ranges = <&pfc 0 64 32>;
128 #interrupt-cells = <2>;
129 interrupt-controller;
130 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
131 power-domains = <&cpg_clocks>;
132 };
133
134 gpio3: gpio@e6053000 {
135 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
136 reg = <0 0xe6053000 0 0x50>;
137 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
138 #gpio-cells = <2>;
139 gpio-controller;
140 gpio-ranges = <&pfc 0 96 32>;
141 #interrupt-cells = <2>;
142 interrupt-controller;
143 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
144 power-domains = <&cpg_clocks>;
145 };
146
147 gpio4: gpio@e6054000 {
148 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
149 reg = <0 0xe6054000 0 0x50>;
150 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
151 #gpio-cells = <2>;
152 gpio-controller;
153 gpio-ranges = <&pfc 0 128 32>;
154 #interrupt-cells = <2>;
155 interrupt-controller;
156 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
157 power-domains = <&cpg_clocks>;
158 };
159
160 gpio5: gpio@e6055000 {
161 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
162 reg = <0 0xe6055000 0 0x50>;
163 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
164 #gpio-cells = <2>;
165 gpio-controller;
166 gpio-ranges = <&pfc 0 160 32>;
167 #interrupt-cells = <2>;
168 interrupt-controller;
169 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
170 power-domains = <&cpg_clocks>;
171 };
172
173 gpio6: gpio@e6055400 {
174 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
175 reg = <0 0xe6055400 0 0x50>;
176 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
177 #gpio-cells = <2>;
178 gpio-controller;
179 gpio-ranges = <&pfc 0 192 32>;
180 #interrupt-cells = <2>;
181 interrupt-controller;
182 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
183 power-domains = <&cpg_clocks>;
184 };
185
186 gpio7: gpio@e6055800 {
187 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
188 reg = <0 0xe6055800 0 0x50>;
189 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
190 #gpio-cells = <2>;
191 gpio-controller;
192 gpio-ranges = <&pfc 0 224 26>;
193 #interrupt-cells = <2>;
194 interrupt-controller;
195 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
196 power-domains = <&cpg_clocks>;
197 };
198
199 thermal: thermal@e61f0000 {
200 compatible = "renesas,thermal-r8a7793",
201 "renesas,rcar-gen2-thermal",
202 "renesas,rcar-thermal";
203 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
204 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
206 power-domains = <&cpg_clocks>;
207 #thermal-sensor-cells = <0>;
208 };
209
210 timer {
211 compatible = "arm,armv7-timer";
212 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
213 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
214 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
215 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
216 };
217
218 cmt0: timer@ffca0000 {
219 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
220 reg = <0 0xffca0000 0 0x1004>;
221 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
224 clock-names = "fck";
225 power-domains = <&cpg_clocks>;
226
227 renesas,channels-mask = <0x60>;
228
229 status = "disabled";
230 };
231
232 cmt1: timer@e6130000 {
233 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
234 reg = <0 0xe6130000 0 0x1004>;
235 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
244 clock-names = "fck";
245 power-domains = <&cpg_clocks>;
246
247 renesas,channels-mask = <0xff>;
248
249 status = "disabled";
250 };
251
252 irqc0: interrupt-controller@e61c0000 {
253 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
254 #interrupt-cells = <2>;
255 interrupt-controller;
256 reg = <0 0xe61c0000 0 0x200>;
257 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
268 power-domains = <&cpg_clocks>;
269 };
270
271 dmac0: dma-controller@e6700000 {
272 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
273 reg = <0 0xe6700000 0 0x20000>;
274 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
275 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
277 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
280 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
282 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
283 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
284 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
285 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
286 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
287 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
288 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
289 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "error",
291 "ch0", "ch1", "ch2", "ch3",
292 "ch4", "ch5", "ch6", "ch7",
293 "ch8", "ch9", "ch10", "ch11",
294 "ch12", "ch13", "ch14";
295 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
296 clock-names = "fck";
297 power-domains = <&cpg_clocks>;
298 #dma-cells = <1>;
299 dma-channels = <15>;
300 };
301
302 dmac1: dma-controller@e6720000 {
303 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
304 reg = <0 0xe6720000 0 0x20000>;
305 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
309 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
312 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
313 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
321 interrupt-names = "error",
322 "ch0", "ch1", "ch2", "ch3",
323 "ch4", "ch5", "ch6", "ch7",
324 "ch8", "ch9", "ch10", "ch11",
325 "ch12", "ch13", "ch14";
326 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
327 clock-names = "fck";
328 power-domains = <&cpg_clocks>;
329 #dma-cells = <1>;
330 dma-channels = <15>;
331 };
332
333 audma0: dma-controller@ec700000 {
334 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
335 reg = <0 0xec700000 0 0x10000>;
336 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "error",
351 "ch0", "ch1", "ch2", "ch3",
352 "ch4", "ch5", "ch6", "ch7",
353 "ch8", "ch9", "ch10", "ch11",
354 "ch12";
355 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
356 clock-names = "fck";
357 power-domains = <&cpg_clocks>;
358 #dma-cells = <1>;
359 dma-channels = <13>;
360 };
361
362 audma1: dma-controller@ec720000 {
363 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
364 reg = <0 0xec720000 0 0x10000>;
365 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
379 interrupt-names = "error",
380 "ch0", "ch1", "ch2", "ch3",
381 "ch4", "ch5", "ch6", "ch7",
382 "ch8", "ch9", "ch10", "ch11",
383 "ch12";
384 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
385 clock-names = "fck";
386 power-domains = <&cpg_clocks>;
387 #dma-cells = <1>;
388 dma-channels = <13>;
389 };
390
391 /* The memory map in the User's Manual maps the cores to bus numbers */
392 i2c0: i2c@e6508000 {
393 #address-cells = <1>;
394 #size-cells = <0>;
395 compatible = "renesas,i2c-r8a7793";
396 reg = <0 0xe6508000 0 0x40>;
397 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
399 power-domains = <&cpg_clocks>;
400 i2c-scl-internal-delay-ns = <6>;
401 status = "disabled";
402 };
403
404 i2c1: i2c@e6518000 {
405 #address-cells = <1>;
406 #size-cells = <0>;
407 compatible = "renesas,i2c-r8a7793";
408 reg = <0 0xe6518000 0 0x40>;
409 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
411 power-domains = <&cpg_clocks>;
412 i2c-scl-internal-delay-ns = <6>;
413 status = "disabled";
414 };
415
416 i2c2: i2c@e6530000 {
417 #address-cells = <1>;
418 #size-cells = <0>;
419 compatible = "renesas,i2c-r8a7793";
420 reg = <0 0xe6530000 0 0x40>;
421 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
423 power-domains = <&cpg_clocks>;
424 i2c-scl-internal-delay-ns = <6>;
425 status = "disabled";
426 };
427
428 i2c3: i2c@e6540000 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "renesas,i2c-r8a7793";
432 reg = <0 0xe6540000 0 0x40>;
433 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
435 power-domains = <&cpg_clocks>;
436 i2c-scl-internal-delay-ns = <6>;
437 status = "disabled";
438 };
439
440 i2c4: i2c@e6520000 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 compatible = "renesas,i2c-r8a7793";
444 reg = <0 0xe6520000 0 0x40>;
445 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
447 power-domains = <&cpg_clocks>;
448 i2c-scl-internal-delay-ns = <6>;
449 status = "disabled";
450 };
451
452 i2c5: i2c@e6528000 {
453 /* doesn't need pinmux */
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "renesas,i2c-r8a7793";
457 reg = <0 0xe6528000 0 0x40>;
458 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
460 power-domains = <&cpg_clocks>;
461 i2c-scl-internal-delay-ns = <110>;
462 status = "disabled";
463 };
464
465 i2c6: i2c@e60b0000 {
466 /* doesn't need pinmux */
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
470 reg = <0 0xe60b0000 0 0x425>;
471 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
473 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
474 dma-names = "tx", "rx";
475 power-domains = <&cpg_clocks>;
476 status = "disabled";
477 };
478
479 i2c7: i2c@e6500000 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
483 reg = <0 0xe6500000 0 0x425>;
484 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
486 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
487 dma-names = "tx", "rx";
488 power-domains = <&cpg_clocks>;
489 status = "disabled";
490 };
491
492 i2c8: i2c@e6510000 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
496 reg = <0 0xe6510000 0 0x425>;
497 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
499 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
500 dma-names = "tx", "rx";
501 power-domains = <&cpg_clocks>;
502 status = "disabled";
503 };
504
505 pfc: pfc@e6060000 {
506 compatible = "renesas,pfc-r8a7793";
507 reg = <0 0xe6060000 0 0x250>;
508 };
509
510 sdhi0: sd@ee100000 {
511 compatible = "renesas,sdhi-r8a7793";
512 reg = <0 0xee100000 0 0x328>;
513 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
515 dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
516 dma-names = "tx", "rx";
517 power-domains = <&cpg_clocks>;
518 status = "disabled";
519 };
520
521 sdhi1: sd@ee140000 {
522 compatible = "renesas,sdhi-r8a7793";
523 reg = <0 0xee140000 0 0x100>;
524 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
526 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
527 dma-names = "tx", "rx";
528 power-domains = <&cpg_clocks>;
529 status = "disabled";
530 };
531
532 sdhi2: sd@ee160000 {
533 compatible = "renesas,sdhi-r8a7793";
534 reg = <0 0xee160000 0 0x100>;
535 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
537 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
538 dma-names = "tx", "rx";
539 power-domains = <&cpg_clocks>;
540 status = "disabled";
541 };
542
543 scifa0: serial@e6c40000 {
544 compatible = "renesas,scifa-r8a7793",
545 "renesas,rcar-gen2-scifa", "renesas,scifa";
546 reg = <0 0xe6c40000 0 64>;
547 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
549 clock-names = "fck";
550 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
551 dma-names = "tx", "rx";
552 power-domains = <&cpg_clocks>;
553 status = "disabled";
554 };
555
556 scifa1: serial@e6c50000 {
557 compatible = "renesas,scifa-r8a7793",
558 "renesas,rcar-gen2-scifa", "renesas,scifa";
559 reg = <0 0xe6c50000 0 64>;
560 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
562 clock-names = "fck";
563 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
564 dma-names = "tx", "rx";
565 power-domains = <&cpg_clocks>;
566 status = "disabled";
567 };
568
569 scifa2: serial@e6c60000 {
570 compatible = "renesas,scifa-r8a7793",
571 "renesas,rcar-gen2-scifa", "renesas,scifa";
572 reg = <0 0xe6c60000 0 64>;
573 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
575 clock-names = "fck";
576 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
577 dma-names = "tx", "rx";
578 power-domains = <&cpg_clocks>;
579 status = "disabled";
580 };
581
582 scifa3: serial@e6c70000 {
583 compatible = "renesas,scifa-r8a7793",
584 "renesas,rcar-gen2-scifa", "renesas,scifa";
585 reg = <0 0xe6c70000 0 64>;
586 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
588 clock-names = "fck";
589 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
590 dma-names = "tx", "rx";
591 power-domains = <&cpg_clocks>;
592 status = "disabled";
593 };
594
595 scifa4: serial@e6c78000 {
596 compatible = "renesas,scifa-r8a7793",
597 "renesas,rcar-gen2-scifa", "renesas,scifa";
598 reg = <0 0xe6c78000 0 64>;
599 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
601 clock-names = "fck";
602 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
603 dma-names = "tx", "rx";
604 power-domains = <&cpg_clocks>;
605 status = "disabled";
606 };
607
608 scifa5: serial@e6c80000 {
609 compatible = "renesas,scifa-r8a7793",
610 "renesas,rcar-gen2-scifa", "renesas,scifa";
611 reg = <0 0xe6c80000 0 64>;
612 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
614 clock-names = "fck";
615 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
616 dma-names = "tx", "rx";
617 power-domains = <&cpg_clocks>;
618 status = "disabled";
619 };
620
621 scifb0: serial@e6c20000 {
622 compatible = "renesas,scifb-r8a7793",
623 "renesas,rcar-gen2-scifb", "renesas,scifb";
624 reg = <0 0xe6c20000 0 64>;
625 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
627 clock-names = "fck";
628 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
629 dma-names = "tx", "rx";
630 power-domains = <&cpg_clocks>;
631 status = "disabled";
632 };
633
634 scifb1: serial@e6c30000 {
635 compatible = "renesas,scifb-r8a7793",
636 "renesas,rcar-gen2-scifb", "renesas,scifb";
637 reg = <0 0xe6c30000 0 64>;
638 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
640 clock-names = "fck";
641 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
642 dma-names = "tx", "rx";
643 power-domains = <&cpg_clocks>;
644 status = "disabled";
645 };
646
647 scifb2: serial@e6ce0000 {
648 compatible = "renesas,scifb-r8a7793",
649 "renesas,rcar-gen2-scifb", "renesas,scifb";
650 reg = <0 0xe6ce0000 0 64>;
651 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
653 clock-names = "fck";
654 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
655 dma-names = "tx", "rx";
656 power-domains = <&cpg_clocks>;
657 status = "disabled";
658 };
659
660 scif0: serial@e6e60000 {
661 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
662 "renesas,scif";
663 reg = <0 0xe6e60000 0 64>;
664 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
666 <&scif_clk>;
667 clock-names = "fck", "brg_int", "scif_clk";
668 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
669 dma-names = "tx", "rx";
670 power-domains = <&cpg_clocks>;
671 status = "disabled";
672 };
673
674 scif1: serial@e6e68000 {
675 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
676 "renesas,scif";
677 reg = <0 0xe6e68000 0 64>;
678 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
680 <&scif_clk>;
681 clock-names = "fck", "brg_int", "scif_clk";
682 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
683 dma-names = "tx", "rx";
684 power-domains = <&cpg_clocks>;
685 status = "disabled";
686 };
687
688 scif2: serial@e6e58000 {
689 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
690 "renesas,scif";
691 reg = <0 0xe6e58000 0 64>;
692 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
694 <&scif_clk>;
695 clock-names = "fck", "brg_int", "scif_clk";
696 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
697 dma-names = "tx", "rx";
698 power-domains = <&cpg_clocks>;
699 status = "disabled";
700 };
701
702 scif3: serial@e6ea8000 {
703 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
704 "renesas,scif";
705 reg = <0 0xe6ea8000 0 64>;
706 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
708 <&scif_clk>;
709 clock-names = "fck", "brg_int", "scif_clk";
710 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
711 dma-names = "tx", "rx";
712 power-domains = <&cpg_clocks>;
713 status = "disabled";
714 };
715
716 scif4: serial@e6ee0000 {
717 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
718 "renesas,scif";
719 reg = <0 0xe6ee0000 0 64>;
720 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
722 <&scif_clk>;
723 clock-names = "fck", "brg_int", "scif_clk";
724 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
725 dma-names = "tx", "rx";
726 power-domains = <&cpg_clocks>;
727 status = "disabled";
728 };
729
730 scif5: serial@e6ee8000 {
731 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
732 "renesas,scif";
733 reg = <0 0xe6ee8000 0 64>;
734 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
736 <&scif_clk>;
737 clock-names = "fck", "brg_int", "scif_clk";
738 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
739 dma-names = "tx", "rx";
740 power-domains = <&cpg_clocks>;
741 status = "disabled";
742 };
743
744 hscif0: serial@e62c0000 {
745 compatible = "renesas,hscif-r8a7793",
746 "renesas,rcar-gen2-hscif", "renesas,hscif";
747 reg = <0 0xe62c0000 0 96>;
748 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
750 <&scif_clk>;
751 clock-names = "fck", "brg_int", "scif_clk";
752 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
753 dma-names = "tx", "rx";
754 power-domains = <&cpg_clocks>;
755 status = "disabled";
756 };
757
758 hscif1: serial@e62c8000 {
759 compatible = "renesas,hscif-r8a7793",
760 "renesas,rcar-gen2-hscif", "renesas,hscif";
761 reg = <0 0xe62c8000 0 96>;
762 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
764 <&scif_clk>;
765 clock-names = "fck", "brg_int", "scif_clk";
766 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
767 dma-names = "tx", "rx";
768 power-domains = <&cpg_clocks>;
769 status = "disabled";
770 };
771
772 hscif2: serial@e62d0000 {
773 compatible = "renesas,hscif-r8a7793",
774 "renesas,rcar-gen2-hscif", "renesas,hscif";
775 reg = <0 0xe62d0000 0 96>;
776 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
778 <&scif_clk>;
779 clock-names = "fck", "brg_int", "scif_clk";
780 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
781 dma-names = "tx", "rx";
782 power-domains = <&cpg_clocks>;
783 status = "disabled";
784 };
785
786 ether: ethernet@ee700000 {
787 compatible = "renesas,ether-r8a7793";
788 reg = <0 0xee700000 0 0x400>;
789 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
791 power-domains = <&cpg_clocks>;
792 phy-mode = "rmii";
793 #address-cells = <1>;
794 #size-cells = <0>;
795 status = "disabled";
796 };
797
798 qspi: spi@e6b10000 {
799 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
800 reg = <0 0xe6b10000 0 0x2c>;
801 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
803 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
804 dma-names = "tx", "rx";
805 power-domains = <&cpg_clocks>;
806 num-cs = <1>;
807 #address-cells = <1>;
808 #size-cells = <0>;
809 status = "disabled";
810 };
811
812 du: display@feb00000 {
813 compatible = "renesas,du-r8a7793";
814 reg = <0 0xfeb00000 0 0x40000>,
815 <0 0xfeb90000 0 0x1c>;
816 reg-names = "du", "lvds.0";
817 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
820 <&mstp7_clks R8A7793_CLK_DU1>,
821 <&mstp7_clks R8A7793_CLK_LVDS0>;
822 clock-names = "du.0", "du.1", "lvds.0";
823 status = "disabled";
824
825 ports {
826 #address-cells = <1>;
827 #size-cells = <0>;
828
829 port@0 {
830 reg = <0>;
831 du_out_rgb: endpoint {
832 };
833 };
834 port@1 {
835 reg = <1>;
836 du_out_lvds0: endpoint {
837 };
838 };
839 };
840 };
841
842 can0: can@e6e80000 {
843 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
844 reg = <0 0xe6e80000 0 0x1000>;
845 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
847 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
848 clock-names = "clkp1", "clkp2", "can_clk";
849 power-domains = <&cpg_clocks>;
850 status = "disabled";
851 };
852
853 can1: can@e6e88000 {
854 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
855 reg = <0 0xe6e88000 0 0x1000>;
856 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
858 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
859 clock-names = "clkp1", "clkp2", "can_clk";
860 power-domains = <&cpg_clocks>;
861 status = "disabled";
862 };
863
864 clocks {
865 #address-cells = <2>;
866 #size-cells = <2>;
867 ranges;
868
869 /* External root clock */
870 extal_clk: extal {
871 compatible = "fixed-clock";
872 #clock-cells = <0>;
873 /* This value must be overridden by the board. */
874 clock-frequency = <0>;
875 };
876
877 /*
878 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
879 * default. Boards that provide audio clocks should override them.
880 */
881 audio_clk_a: audio_clk_a {
882 compatible = "fixed-clock";
883 #clock-cells = <0>;
884 clock-frequency = <0>;
885 };
886 audio_clk_b: audio_clk_b {
887 compatible = "fixed-clock";
888 #clock-cells = <0>;
889 clock-frequency = <0>;
890 };
891 audio_clk_c: audio_clk_c {
892 compatible = "fixed-clock";
893 #clock-cells = <0>;
894 clock-frequency = <0>;
895 };
896
897 /* External USB clock - can be overridden by the board */
898 usb_extal_clk: usb_extal {
899 compatible = "fixed-clock";
900 #clock-cells = <0>;
901 clock-frequency = <48000000>;
902 };
903
904 /* External CAN clock */
905 can_clk: can {
906 compatible = "fixed-clock";
907 #clock-cells = <0>;
908 /* This value must be overridden by the board. */
909 clock-frequency = <0>;
910 };
911
912 /* External SCIF clock */
913 scif_clk: scif {
914 compatible = "fixed-clock";
915 #clock-cells = <0>;
916 /* This value must be overridden by the board. */
917 clock-frequency = <0>;
918 };
919
920 /* Special CPG clocks */
921 cpg_clocks: cpg_clocks@e6150000 {
922 compatible = "renesas,r8a7793-cpg-clocks",
923 "renesas,rcar-gen2-cpg-clocks";
924 reg = <0 0xe6150000 0 0x1000>;
925 clocks = <&extal_clk &usb_extal_clk>;
926 #clock-cells = <1>;
927 clock-output-names = "main", "pll0", "pll1", "pll3",
928 "lb", "qspi", "sdh", "sd0", "z",
929 "rcan", "adsp";
930 #power-domain-cells = <0>;
931 };
932
933 /* Variable factor clocks */
934 sd2_clk: sd2@e6150078 {
935 compatible = "renesas,r8a7793-div6-clock",
936 "renesas,cpg-div6-clock";
937 reg = <0 0xe6150078 0 4>;
938 clocks = <&pll1_div2_clk>;
939 #clock-cells = <0>;
940 };
941 sd3_clk: sd3@e615026c {
942 compatible = "renesas,r8a7793-div6-clock",
943 "renesas,cpg-div6-clock";
944 reg = <0 0xe615026c 0 4>;
945 clocks = <&pll1_div2_clk>;
946 #clock-cells = <0>;
947 };
948 mmc0_clk: mmc0@e6150240 {
949 compatible = "renesas,r8a7793-div6-clock",
950 "renesas,cpg-div6-clock";
951 reg = <0 0xe6150240 0 4>;
952 clocks = <&pll1_div2_clk>;
953 #clock-cells = <0>;
954 };
955
956 /* Fixed factor clocks */
957 pll1_div2_clk: pll1_div2 {
958 compatible = "fixed-factor-clock";
959 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
960 #clock-cells = <0>;
961 clock-div = <2>;
962 clock-mult = <1>;
963 };
964 zg_clk: zg {
965 compatible = "fixed-factor-clock";
966 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
967 #clock-cells = <0>;
968 clock-div = <5>;
969 clock-mult = <1>;
970 };
971 zx_clk: zx {
972 compatible = "fixed-factor-clock";
973 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
974 #clock-cells = <0>;
975 clock-div = <3>;
976 clock-mult = <1>;
977 };
978 zs_clk: zs {
979 compatible = "fixed-factor-clock";
980 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
981 #clock-cells = <0>;
982 clock-div = <6>;
983 clock-mult = <1>;
984 };
985 hp_clk: hp {
986 compatible = "fixed-factor-clock";
987 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
988 #clock-cells = <0>;
989 clock-div = <12>;
990 clock-mult = <1>;
991 };
992 p_clk: p {
993 compatible = "fixed-factor-clock";
994 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
995 #clock-cells = <0>;
996 clock-div = <24>;
997 clock-mult = <1>;
998 };
999 m2_clk: m2 {
1000 compatible = "fixed-factor-clock";
1001 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1002 #clock-cells = <0>;
1003 clock-div = <8>;
1004 clock-mult = <1>;
1005 };
1006 rclk_clk: rclk {
1007 compatible = "fixed-factor-clock";
1008 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1009 #clock-cells = <0>;
1010 clock-div = <(48 * 1024)>;
1011 clock-mult = <1>;
1012 };
1013 mp_clk: mp {
1014 compatible = "fixed-factor-clock";
1015 clocks = <&pll1_div2_clk>;
1016 #clock-cells = <0>;
1017 clock-div = <15>;
1018 clock-mult = <1>;
1019 };
1020 cp_clk: cp {
1021 compatible = "fixed-factor-clock";
1022 clocks = <&extal_clk>;
1023 #clock-cells = <0>;
1024 clock-div = <2>;
1025 clock-mult = <1>;
1026 };
1027
1028 /* Gate clocks */
1029 mstp1_clks: mstp1_clks@e6150134 {
1030 compatible = "renesas,r8a7793-mstp-clocks",
1031 "renesas,cpg-mstp-clocks";
1032 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1033 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1034 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
1035 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1036 <&zs_clk>, <&zs_clk>, <&zs_clk>;
1037 #clock-cells = <1>;
1038 clock-indices = <
1039 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
1040 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
1041 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
1042 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
1043 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
1044 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
1045 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
1046 R8A7793_CLK_VSP1_S
1047 >;
1048 clock-output-names =
1049 "vcp0", "vpc0", "ssp_dev", "tmu1",
1050 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
1051 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
1052 "vsp1-du0", "vsps";
1053 };
1054 mstp2_clks: mstp2_clks@e6150138 {
1055 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1056 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1057 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1058 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
1059 #clock-cells = <1>;
1060 clock-indices = <
1061 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
1062 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
1063 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
1064 >;
1065 clock-output-names =
1066 "scifa2", "scifa1", "scifa0", "scifb0",
1067 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1068 };
1069 mstp3_clks: mstp3_clks@e615013c {
1070 compatible = "renesas,r8a7793-mstp-clocks",
1071 "renesas,cpg-mstp-clocks";
1072 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1073 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1074 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1075 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1076 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1077 #clock-cells = <1>;
1078 clock-indices = <
1079 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1080 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1081 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1082 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1083 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1084 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1085 >;
1086 clock-output-names =
1087 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1088 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1089 "usbdmac0", "usbdmac1";
1090 };
1091 mstp4_clks: mstp4_clks@e6150140 {
1092 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1093 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1094 clocks = <&cp_clk>;
1095 #clock-cells = <1>;
1096 clock-indices = <R8A7793_CLK_IRQC>;
1097 clock-output-names = "irqc";
1098 };
1099 mstp5_clks: mstp5_clks@e6150144 {
1100 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1101 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1102 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1103 #clock-cells = <1>;
1104 clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1105 R8A7793_CLK_THERMAL>;
1106 clock-output-names = "audmac0", "audmac1", "thermal";
1107 };
1108 mstp7_clks: mstp7_clks@e615014c {
1109 compatible = "renesas,r8a7793-mstp-clocks",
1110 "renesas,cpg-mstp-clocks";
1111 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1112 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
1113 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1114 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1115 <&zx_clk>, <&zx_clk>;
1116 #clock-cells = <1>;
1117 clock-indices = <
1118 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1119 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1120 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1121 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1122 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1123 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1124 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1125 >;
1126 clock-output-names =
1127 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1128 "hscif1", "hscif0", "scif3", "scif2",
1129 "scif1", "scif0", "du1", "du0", "lvds0";
1130 };
1131 mstp8_clks: mstp8_clks@e6150990 {
1132 compatible = "renesas,r8a7793-mstp-clocks",
1133 "renesas,cpg-mstp-clocks";
1134 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1135 clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1136 <&p_clk>, <&zs_clk>, <&zs_clk>;
1137 #clock-cells = <1>;
1138 clock-indices = <
1139 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1140 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1141 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1142 R8A7793_CLK_SATA0
1143 >;
1144 clock-output-names =
1145 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1146 "sata1", "sata0";
1147 };
1148 mstp9_clks: mstp9_clks@e6150994 {
1149 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1150 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1151 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1152 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1153 <&p_clk>, <&p_clk>,
1154 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1155 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1156 <&hp_clk>, <&hp_clk>;
1157 #clock-cells = <1>;
1158 clock-indices = <
1159 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1160 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1161 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1162 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1163 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
1164 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
1165 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1166 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1167 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1168 >;
1169 clock-output-names =
1170 "gpio7", "gpio6", "gpio5", "gpio4",
1171 "gpio3", "gpio2", "gpio1", "gpio0",
1172 "rcan1", "rcan0", "qspi_mod", "i2c5",
1173 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
1174 "i2c0";
1175 };
1176 mstp10_clks: mstp10_clks@e6150998 {
1177 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1178 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1179 clocks = <&p_clk>,
1180 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1181 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1182 <&p_clk>,
1183 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1184 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1185 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1186 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1187 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1188 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1189 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1190
1191 #clock-cells = <1>;
1192 clock-indices = <
1193 R8A7793_CLK_SSI_ALL
1194 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1195 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1196 R8A7793_CLK_SCU_ALL
1197 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1198 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1199 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1200 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1201 >;
1202 clock-output-names =
1203 "ssi-all",
1204 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1205 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1206 "scu-all",
1207 "scu-dvc1", "scu-dvc0",
1208 "scu-ctu1-mix1", "scu-ctu0-mix0",
1209 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1210 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1211 };
1212 mstp11_clks: mstp11_clks@e615099c {
1213 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1214 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1215 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1216 #clock-cells = <1>;
1217 clock-indices = <
1218 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1219 >;
1220 clock-output-names = "scifa3", "scifa4", "scifa5";
1221 };
1222 };
1223
1224 ipmmu_sy0: mmu@e6280000 {
1225 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1226 reg = <0 0xe6280000 0 0x1000>;
1227 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1229 #iommu-cells = <1>;
1230 status = "disabled";
1231 };
1232
1233 ipmmu_sy1: mmu@e6290000 {
1234 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1235 reg = <0 0xe6290000 0 0x1000>;
1236 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1237 #iommu-cells = <1>;
1238 status = "disabled";
1239 };
1240
1241 ipmmu_ds: mmu@e6740000 {
1242 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1243 reg = <0 0xe6740000 0 0x1000>;
1244 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1246 #iommu-cells = <1>;
1247 status = "disabled";
1248 };
1249
1250 ipmmu_mp: mmu@ec680000 {
1251 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1252 reg = <0 0xec680000 0 0x1000>;
1253 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1254 #iommu-cells = <1>;
1255 status = "disabled";
1256 };
1257
1258 ipmmu_mx: mmu@fe951000 {
1259 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1260 reg = <0 0xfe951000 0 0x1000>;
1261 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1263 #iommu-cells = <1>;
1264 status = "disabled";
1265 };
1266
1267 ipmmu_rt: mmu@ffc80000 {
1268 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1269 reg = <0 0xffc80000 0 0x1000>;
1270 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1271 #iommu-cells = <1>;
1272 status = "disabled";
1273 };
1274
1275 ipmmu_gp: mmu@e62a0000 {
1276 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1277 reg = <0 0xe62a0000 0 0x1000>;
1278 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1279 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1280 #iommu-cells = <1>;
1281 status = "disabled";
1282 };
1283
1284 rcar_sound: sound@ec500000 {
1285 /*
1286 * #sound-dai-cells is required
1287 *
1288 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1289 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1290 */
1291 compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1292 reg = <0 0xec500000 0 0x1000>, /* SCU */
1293 <0 0xec5a0000 0 0x100>, /* ADG */
1294 <0 0xec540000 0 0x1000>, /* SSIU */
1295 <0 0xec541000 0 0x280>, /* SSI */
1296 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1297 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1298
1299 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1300 <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1301 <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1302 <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1303 <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1304 <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1305 <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1306 <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1307 <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1308 <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1309 <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1310 <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1311 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1312 clock-names = "ssi-all",
1313 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1314 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1315 "src.9", "src.8", "src.7", "src.6", "src.5",
1316 "src.4", "src.3", "src.2", "src.1", "src.0",
1317 "dvc.0", "dvc.1",
1318 "clk_a", "clk_b", "clk_c", "clk_i";
1319 power-domains = <&cpg_clocks>;
1320
1321 status = "disabled";
1322
1323 rcar_sound,dvc {
1324 dvc0: dvc@0 {
1325 dmas = <&audma0 0xbc>;
1326 dma-names = "tx";
1327 };
1328 dvc1: dvc@1 {
1329 dmas = <&audma0 0xbe>;
1330 dma-names = "tx";
1331 };
1332 };
1333
1334 rcar_sound,src {
1335 src0: src@0 {
1336 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1337 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1338 dma-names = "rx", "tx";
1339 };
1340 src1: src@1 {
1341 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1342 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1343 dma-names = "rx", "tx";
1344 };
1345 src2: src@2 {
1346 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1347 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1348 dma-names = "rx", "tx";
1349 };
1350 src3: src@3 {
1351 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1352 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1353 dma-names = "rx", "tx";
1354 };
1355 src4: src@4 {
1356 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1357 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1358 dma-names = "rx", "tx";
1359 };
1360 src5: src@5 {
1361 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1362 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1363 dma-names = "rx", "tx";
1364 };
1365 src6: src@6 {
1366 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1367 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1368 dma-names = "rx", "tx";
1369 };
1370 src7: src@7 {
1371 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1372 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1373 dma-names = "rx", "tx";
1374 };
1375 src8: src@8 {
1376 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1377 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1378 dma-names = "rx", "tx";
1379 };
1380 src9: src@9 {
1381 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1382 dmas = <&audma0 0x97>, <&audma1 0xba>;
1383 dma-names = "rx", "tx";
1384 };
1385 };
1386
1387 rcar_sound,ssi {
1388 ssi0: ssi@0 {
1389 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1391 dma-names = "rx", "tx", "rxu", "txu";
1392 };
1393 ssi1: ssi@1 {
1394 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1395 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1396 dma-names = "rx", "tx", "rxu", "txu";
1397 };
1398 ssi2: ssi@2 {
1399 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1400 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1401 dma-names = "rx", "tx", "rxu", "txu";
1402 };
1403 ssi3: ssi@3 {
1404 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1405 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1406 dma-names = "rx", "tx", "rxu", "txu";
1407 };
1408 ssi4: ssi@4 {
1409 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1410 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1411 dma-names = "rx", "tx", "rxu", "txu";
1412 };
1413 ssi5: ssi@5 {
1414 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1415 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1416 dma-names = "rx", "tx", "rxu", "txu";
1417 };
1418 ssi6: ssi@6 {
1419 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1420 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1421 dma-names = "rx", "tx", "rxu", "txu";
1422 };
1423 ssi7: ssi@7 {
1424 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1425 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1426 dma-names = "rx", "tx", "rxu", "txu";
1427 };
1428 ssi8: ssi@8 {
1429 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1430 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1431 dma-names = "rx", "tx", "rxu", "txu";
1432 };
1433 ssi9: ssi@9 {
1434 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1436 dma-names = "rx", "tx", "rxu", "txu";
1437 };
1438 };
1439 };
1440 };
Linux kernel - Deliverables
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