arch/arm/boot/dts/r8a7794.dtsi

   1 /*
   2  * Device Tree Source for the r8a7794 SoC
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2014 Ulrich Hecht
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7794-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7794";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 spi0 = &qspi;
  30                 vin0 = &vin0;
  31                 vin1 = &vin1;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a7";
  41                         reg = <0>;
  42                         clock-frequency = <1000000000>;
  43                         next-level-cache = <&L2_CA7>;
  44                 };
  45
  46                 cpu1: cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a7";
  49                         reg = <1>;
  50                         clock-frequency = <1000000000>;
  51                         next-level-cache = <&L2_CA7>;
  52                 };
  53         };
  54
  55         L2_CA7: cache-controller@1 {
  56                 compatible = "cache";
  57                 cache-unified;
  58                 cache-level = <2>;
  59         };
  60
  61         gic: interrupt-controller@f1001000 {
  62                 compatible = "arm,gic-400";
  63                 #interrupt-cells = <3>;
  64                 #address-cells = <0>;
  65                 interrupt-controller;
  66                 reg = <0 0xf1001000 0 0x1000>,
  67                         <0 0xf1002000 0 0x1000>,
  68                         <0 0xf1004000 0 0x2000>,
  69                         <0 0xf1006000 0 0x2000>;
  70                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  71         };
  72
  73         gpio0: gpio@e6050000 {
  74                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  75                 reg = <0 0xe6050000 0 0x50>;
  76                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  77                 #gpio-cells = <2>;
  78                 gpio-controller;
  79                 gpio-ranges = <&pfc 0 0 32>;
  80                 #interrupt-cells = <2>;
  81                 interrupt-controller;
  82                 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
  83                 power-domains = <&cpg_clocks>;
  84         };
  85
  86         gpio1: gpio@e6051000 {
  87                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
  88                 reg = <0 0xe6051000 0 0x50>;
  89                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  90                 #gpio-cells = <2>;
  91                 gpio-controller;
  92                 gpio-ranges = <&pfc 0 32 26>;
  93                 #interrupt-cells = <2>;
  94                 interrupt-controller;
  95                 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
  96                 power-domains = <&cpg_clocks>;
  97         };
  98
  99         gpio2: gpio@e6052000 {
 100                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 101                 reg = <0 0xe6052000 0 0x50>;
 102                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 103                 #gpio-cells = <2>;
 104                 gpio-controller;
 105                 gpio-ranges = <&pfc 0 64 32>;
 106                 #interrupt-cells = <2>;
 107                 interrupt-controller;
 108                 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
 109                 power-domains = <&cpg_clocks>;
 110         };
 111
 112         gpio3: gpio@e6053000 {
 113                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 114                 reg = <0 0xe6053000 0 0x50>;
 115                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 116                 #gpio-cells = <2>;
 117                 gpio-controller;
 118                 gpio-ranges = <&pfc 0 96 32>;
 119                 #interrupt-cells = <2>;
 120                 interrupt-controller;
 121                 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
 122                 power-domains = <&cpg_clocks>;
 123         };
 124
 125         gpio4: gpio@e6054000 {
 126                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 127                 reg = <0 0xe6054000 0 0x50>;
 128                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 129                 #gpio-cells = <2>;
 130                 gpio-controller;
 131                 gpio-ranges = <&pfc 0 128 32>;
 132                 #interrupt-cells = <2>;
 133                 interrupt-controller;
 134                 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
 135                 power-domains = <&cpg_clocks>;
 136         };
 137
 138         gpio5: gpio@e6055000 {
 139                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 140                 reg = <0 0xe6055000 0 0x50>;
 141                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 142                 #gpio-cells = <2>;
 143                 gpio-controller;
 144                 gpio-ranges = <&pfc 0 160 28>;
 145                 #interrupt-cells = <2>;
 146                 interrupt-controller;
 147                 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
 148                 power-domains = <&cpg_clocks>;
 149         };
 150
 151         gpio6: gpio@e6055400 {
 152                 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 153                 reg = <0 0xe6055400 0 0x50>;
 154                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 155                 #gpio-cells = <2>;
 156                 gpio-controller;
 157                 gpio-ranges = <&pfc 0 192 26>;
 158                 #interrupt-cells = <2>;
 159                 interrupt-controller;
 160                 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
 161                 power-domains = <&cpg_clocks>;
 162         };
 163
 164         cmt0: timer@ffca0000 {
 165                 compatible = "renesas,cmt-48-gen2";
 166                 reg = <0 0xffca0000 0 0x1004>;
 167                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 170                 clock-names = "fck";
 171                 power-domains = <&cpg_clocks>;
 172
 173                 renesas,channels-mask = <0x60>;
 174
 175                 status = "disabled";
 176         };
 177
 178         cmt1: timer@e6130000 {
 179                 compatible = "renesas,cmt-48-gen2";
 180                 reg = <0 0xe6130000 0 0x1004>;
 181                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 190                 clock-names = "fck";
 191                 power-domains = <&cpg_clocks>;
 192
 193                 renesas,channels-mask = <0xff>;
 194
 195                 status = "disabled";
 196         };
 197
 198         timer {
 199                 compatible = "arm,armv7-timer";
 200                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 201                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 202                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 203                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 204         };
 205
 206         irqc0: interrupt-controller@e61c0000 {
 207                 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
 208                 #interrupt-cells = <2>;
 209                 interrupt-controller;
 210                 reg = <0 0xe61c0000 0 0x200>;
 211                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
 222                 power-domains = <&cpg_clocks>;
 223         };
 224
 225         pfc: pin-controller@e6060000 {
 226                 compatible = "renesas,pfc-r8a7794";
 227                 reg = <0 0xe6060000 0 0x11c>;
 228         };
 229
 230         dmac0: dma-controller@e6700000 {
 231                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 232                 reg = <0 0xe6700000 0 0x20000>;
 233                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 234                               GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 235                               GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 236                               GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 237                               GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 238                               GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 239                               GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 240                               GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 241                               GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 242                               GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 243                               GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 244                               GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 245                               GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 248                               GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 249                 interrupt-names = "error",
 250                                 "ch0", "ch1", "ch2", "ch3",
 251                                 "ch4", "ch5", "ch6", "ch7",
 252                                 "ch8", "ch9", "ch10", "ch11",
 253                                 "ch12", "ch13", "ch14";
 254                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 255                 clock-names = "fck";
 256                 power-domains = <&cpg_clocks>;
 257                 #dma-cells = <1>;
 258                 dma-channels = <15>;
 259         };
 260
 261         dmac1: dma-controller@e6720000 {
 262                 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 263                 reg = <0 0xe6720000 0 0x20000>;
 264                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 265                               GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 266                               GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 267                               GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 268                               GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 269                               GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 270                               GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 271                               GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 272                               GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 273                               GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 274                               GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 275                               GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 276                               GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 277                               GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 278                               GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 279                               GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 280                 interrupt-names = "error",
 281                                 "ch0", "ch1", "ch2", "ch3",
 282                                 "ch4", "ch5", "ch6", "ch7",
 283                                 "ch8", "ch9", "ch10", "ch11",
 284                                 "ch12", "ch13", "ch14";
 285                 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 286                 clock-names = "fck";
 287                 power-domains = <&cpg_clocks>;
 288                 #dma-cells = <1>;
 289                 dma-channels = <15>;
 290         };
 291
 292         scifa0: serial@e6c40000 {
 293                 compatible = "renesas,scifa-r8a7794",
 294                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 295                 reg = <0 0xe6c40000 0 64>;
 296                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
 298                 clock-names = "fck";
 299                 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 300                 dma-names = "tx", "rx";
 301                 power-domains = <&cpg_clocks>;
 302                 status = "disabled";
 303         };
 304
 305         scifa1: serial@e6c50000 {
 306                 compatible = "renesas,scifa-r8a7794",
 307                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 308                 reg = <0 0xe6c50000 0 64>;
 309                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 310                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
 311                 clock-names = "fck";
 312                 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 313                 dma-names = "tx", "rx";
 314                 power-domains = <&cpg_clocks>;
 315                 status = "disabled";
 316         };
 317
 318         scifa2: serial@e6c60000 {
 319                 compatible = "renesas,scifa-r8a7794",
 320                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 321                 reg = <0 0xe6c60000 0 64>;
 322                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 323                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
 324                 clock-names = "fck";
 325                 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 326                 dma-names = "tx", "rx";
 327                 power-domains = <&cpg_clocks>;
 328                 status = "disabled";
 329         };
 330
 331         scifa3: serial@e6c70000 {
 332                 compatible = "renesas,scifa-r8a7794",
 333                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 334                 reg = <0 0xe6c70000 0 64>;
 335                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
 337                 clock-names = "fck";
 338                 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 339                 dma-names = "tx", "rx";
 340                 power-domains = <&cpg_clocks>;
 341                 status = "disabled";
 342         };
 343
 344         scifa4: serial@e6c78000 {
 345                 compatible = "renesas,scifa-r8a7794",
 346                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 347                 reg = <0 0xe6c78000 0 64>;
 348                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 349                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
 350                 clock-names = "fck";
 351                 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 352                 dma-names = "tx", "rx";
 353                 power-domains = <&cpg_clocks>;
 354                 status = "disabled";
 355         };
 356
 357         scifa5: serial@e6c80000 {
 358                 compatible = "renesas,scifa-r8a7794",
 359                              "renesas,rcar-gen2-scifa", "renesas,scifa";
 360                 reg = <0 0xe6c80000 0 64>;
 361                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
 363                 clock-names = "fck";
 364                 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 365                 dma-names = "tx", "rx";
 366                 power-domains = <&cpg_clocks>;
 367                 status = "disabled";
 368         };
 369
 370         scifb0: serial@e6c20000 {
 371                 compatible = "renesas,scifb-r8a7794",
 372                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 373                 reg = <0 0xe6c20000 0 64>;
 374                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
 376                 clock-names = "fck";
 377                 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 378                 dma-names = "tx", "rx";
 379                 power-domains = <&cpg_clocks>;
 380                 status = "disabled";
 381         };
 382
 383         scifb1: serial@e6c30000 {
 384                 compatible = "renesas,scifb-r8a7794",
 385                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 386                 reg = <0 0xe6c30000 0 64>;
 387                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
 389                 clock-names = "fck";
 390                 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 391                 dma-names = "tx", "rx";
 392                 power-domains = <&cpg_clocks>;
 393                 status = "disabled";
 394         };
 395
 396         scifb2: serial@e6ce0000 {
 397                 compatible = "renesas,scifb-r8a7794",
 398                              "renesas,rcar-gen2-scifb", "renesas,scifb";
 399                 reg = <0 0xe6ce0000 0 64>;
 400                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 401                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
 402                 clock-names = "fck";
 403                 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 404                 dma-names = "tx", "rx";
 405                 power-domains = <&cpg_clocks>;
 406                 status = "disabled";
 407         };
 408
 409         scif0: serial@e6e60000 {
 410                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 411                              "renesas,scif";
 412                 reg = <0 0xe6e60000 0 64>;
 413                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 414                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
 415                          <&scif_clk>;
 416                 clock-names = "fck", "brg_int", "scif_clk";
 417                 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 418                 dma-names = "tx", "rx";
 419                 power-domains = <&cpg_clocks>;
 420                 status = "disabled";
 421         };
 422
 423         scif1: serial@e6e68000 {
 424                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 425                              "renesas,scif";
 426                 reg = <0 0xe6e68000 0 64>;
 427                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
 429                          <&scif_clk>;
 430                 clock-names = "fck", "brg_int", "scif_clk";
 431                 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 432                 dma-names = "tx", "rx";
 433                 power-domains = <&cpg_clocks>;
 434                 status = "disabled";
 435         };
 436
 437         scif2: serial@e6e58000 {
 438                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 439                              "renesas,scif";
 440                 reg = <0 0xe6e58000 0 64>;
 441                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
 443                          <&scif_clk>;
 444                 clock-names = "fck", "brg_int", "scif_clk";
 445                 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 446                 dma-names = "tx", "rx";
 447                 power-domains = <&cpg_clocks>;
 448                 status = "disabled";
 449         };
 450
 451         scif3: serial@e6ea8000 {
 452                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 453                              "renesas,scif";
 454                 reg = <0 0xe6ea8000 0 64>;
 455                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 456                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
 457                          <&scif_clk>;
 458                 clock-names = "fck", "brg_int", "scif_clk";
 459                 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 460                 dma-names = "tx", "rx";
 461                 power-domains = <&cpg_clocks>;
 462                 status = "disabled";
 463         };
 464
 465         scif4: serial@e6ee0000 {
 466                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 467                              "renesas,scif";
 468                 reg = <0 0xe6ee0000 0 64>;
 469                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 470                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
 471                          <&scif_clk>;
 472                 clock-names = "fck", "brg_int", "scif_clk";
 473                 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 474                 dma-names = "tx", "rx";
 475                 power-domains = <&cpg_clocks>;
 476                 status = "disabled";
 477         };
 478
 479         scif5: serial@e6ee8000 {
 480                 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
 481                              "renesas,scif";
 482                 reg = <0 0xe6ee8000 0 64>;
 483                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 484                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
 485                          <&scif_clk>;
 486                 clock-names = "fck", "brg_int", "scif_clk";
 487                 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 488                 dma-names = "tx", "rx";
 489                 power-domains = <&cpg_clocks>;
 490                 status = "disabled";
 491         };
 492
 493         hscif0: serial@e62c0000 {
 494                 compatible = "renesas,hscif-r8a7794",
 495                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 496                 reg = <0 0xe62c0000 0 96>;
 497                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
 499                          <&scif_clk>;
 500                 clock-names = "fck", "brg_int", "scif_clk";
 501                 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 502                 dma-names = "tx", "rx";
 503                 power-domains = <&cpg_clocks>;
 504                 status = "disabled";
 505         };
 506
 507         hscif1: serial@e62c8000 {
 508                 compatible = "renesas,hscif-r8a7794",
 509                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 510                 reg = <0 0xe62c8000 0 96>;
 511                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
 513                          <&scif_clk>;
 514                 clock-names = "fck", "brg_int", "scif_clk";
 515                 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 516                 dma-names = "tx", "rx";
 517                 power-domains = <&cpg_clocks>;
 518                 status = "disabled";
 519         };
 520
 521         hscif2: serial@e62d0000 {
 522                 compatible = "renesas,hscif-r8a7794",
 523                              "renesas,rcar-gen2-hscif", "renesas,hscif";
 524                 reg = <0 0xe62d0000 0 96>;
 525                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 526                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
 527                          <&scif_clk>;
 528                 clock-names = "fck", "brg_int", "scif_clk";
 529                 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 530                 dma-names = "tx", "rx";
 531                 power-domains = <&cpg_clocks>;
 532                 status = "disabled";
 533         };
 534
 535         ether: ethernet@ee700000 {
 536                 compatible = "renesas,ether-r8a7794";
 537                 reg = <0 0xee700000 0 0x400>;
 538                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 539                 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
 540                 power-domains = <&cpg_clocks>;
 541                 phy-mode = "rmii";
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 status = "disabled";
 545         };
 546
 547         avb: ethernet@e6800000 {
 548                 compatible = "renesas,etheravb-r8a7794",
 549                              "renesas,etheravb-rcar-gen2";
 550                 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 551                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 552                 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
 553                 power-domains = <&cpg_clocks>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 status = "disabled";
 557         };
 558
 559         /* The memory map in the User's Manual maps the cores to bus numbers */
 560         i2c0: i2c@e6508000 {
 561                 compatible = "renesas,i2c-r8a7794";
 562                 reg = <0 0xe6508000 0 0x40>;
 563                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 564                 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
 565                 power-domains = <&cpg_clocks>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 i2c-scl-internal-delay-ns = <6>;
 569                 status = "disabled";
 570         };
 571
 572         i2c1: i2c@e6518000 {
 573                 compatible = "renesas,i2c-r8a7794";
 574                 reg = <0 0xe6518000 0 0x40>;
 575                 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 576                 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
 577                 power-domains = <&cpg_clocks>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 i2c-scl-internal-delay-ns = <6>;
 581                 status = "disabled";
 582         };
 583
 584         i2c2: i2c@e6530000 {
 585                 compatible = "renesas,i2c-r8a7794";
 586                 reg = <0 0xe6530000 0 0x40>;
 587                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 588                 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
 589                 power-domains = <&cpg_clocks>;
 590                 #address-cells = <1>;
 591                 #size-cells = <0>;
 592                 i2c-scl-internal-delay-ns = <6>;
 593                 status = "disabled";
 594         };
 595
 596         i2c3: i2c@e6540000 {
 597                 compatible = "renesas,i2c-r8a7794";
 598                 reg = <0 0xe6540000 0 0x40>;
 599                 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
 601                 power-domains = <&cpg_clocks>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 i2c-scl-internal-delay-ns = <6>;
 605                 status = "disabled";
 606         };
 607
 608         i2c4: i2c@e6520000 {
 609                 compatible = "renesas,i2c-r8a7794";
 610                 reg = <0 0xe6520000 0 0x40>;
 611                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 612                 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
 613                 power-domains = <&cpg_clocks>;
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 i2c-scl-internal-delay-ns = <6>;
 617                 status = "disabled";
 618         };
 619
 620         i2c5: i2c@e6528000 {
 621                 compatible = "renesas,i2c-r8a7794";
 622                 reg = <0 0xe6528000 0 0x40>;
 623                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
 625                 power-domains = <&cpg_clocks>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 i2c-scl-internal-delay-ns = <6>;
 629                 status = "disabled";
 630         };
 631
 632         mmcif0: mmc@ee200000 {
 633                 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 634                 reg = <0 0xee200000 0 0x80>;
 635                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 636                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 637                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 638                 dma-names = "tx", "rx";
 639                 power-domains = <&cpg_clocks>;
 640                 reg-io-width = <4>;
 641                 status = "disabled";
 642         };
 643
 644         sdhi0: sd@ee100000 {
 645                 compatible = "renesas,sdhi-r8a7794";
 646                 reg = <0 0xee100000 0 0x200>;
 647                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 648                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
 649                 power-domains = <&cpg_clocks>;
 650                 status = "disabled";
 651         };
 652
 653         sdhi1: sd@ee140000 {
 654                 compatible = "renesas,sdhi-r8a7794";
 655                 reg = <0 0xee140000 0 0x100>;
 656                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 657                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
 658                 power-domains = <&cpg_clocks>;
 659                 status = "disabled";
 660         };
 661
 662         sdhi2: sd@ee160000 {
 663                 compatible = "renesas,sdhi-r8a7794";
 664                 reg = <0 0xee160000 0 0x100>;
 665                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 666                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
 667                 power-domains = <&cpg_clocks>;
 668                 status = "disabled";
 669         };
 670
 671         qspi: spi@e6b10000 {
 672                 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 673                 reg = <0 0xe6b10000 0 0x2c>;
 674                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 675                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 676                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 677                 dma-names = "tx", "rx";
 678                 power-domains = <&cpg_clocks>;
 679                 num-cs = <1>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 status = "disabled";
 683         };
 684
 685         vin0: video@e6ef0000 {
 686                 compatible = "renesas,vin-r8a7794";
 687                 reg = <0 0xe6ef0000 0 0x1000>;
 688                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 689                 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
 690                 power-domains = <&cpg_clocks>;
 691                 status = "disabled";
 692         };
 693
 694         vin1: video@e6ef1000 {
 695                 compatible = "renesas,vin-r8a7794";
 696                 reg = <0 0xe6ef1000 0 0x1000>;
 697                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 698                 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
 699                 power-domains = <&cpg_clocks>;
 700                 status = "disabled";
 701         };
 702
 703         pci0: pci@ee090000 {
 704                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 705                 device_type = "pci";
 706                 reg = <0 0xee090000 0 0xc00>,
 707                       <0 0xee080000 0 0x1100>;
 708                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 709                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 710                 power-domains = <&cpg_clocks>;
 711                 status = "disabled";
 712
 713                 bus-range = <0 0>;
 714                 #address-cells = <3>;
 715                 #size-cells = <2>;
 716                 #interrupt-cells = <1>;
 717                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 718                 interrupt-map-mask = <0xff00 0 0 0x7>;
 719                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 720                                  0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
 721                                  0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 722
 723                 usb@0,1 {
 724                         reg = <0x800 0 0 0 0>;
 725                         device_type = "pci";
 726                         phys = <&usb0 0>;
 727                         phy-names = "usb";
 728                 };
 729
 730                 usb@0,2 {
 731                         reg = <0x1000 0 0 0 0>;
 732                         device_type = "pci";
 733                         phys = <&usb0 0>;
 734                         phy-names = "usb";
 735                 };
 736         };
 737
 738         pci1: pci@ee0d0000 {
 739                 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 740                 device_type = "pci";
 741                 reg = <0 0xee0d0000 0 0xc00>,
 742                       <0 0xee0c0000 0 0x1100>;
 743                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 744                 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
 745                 power-domains = <&cpg_clocks>;
 746                 status = "disabled";
 747
 748                 bus-range = <1 1>;
 749                 #address-cells = <3>;
 750                 #size-cells = <2>;
 751                 #interrupt-cells = <1>;
 752                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 753                 interrupt-map-mask = <0xff00 0 0 0x7>;
 754                 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 755                                  0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
 756                                  0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 757
 758                 usb@0,1 {
 759                         reg = <0x800 0 0 0 0>;
 760                         device_type = "pci";
 761                         phys = <&usb2 0>;
 762                         phy-names = "usb";
 763                 };
 764
 765                 usb@0,2 {
 766                         reg = <0x1000 0 0 0 0>;
 767                         device_type = "pci";
 768                         phys = <&usb2 0>;
 769                         phy-names = "usb";
 770                 };
 771         };
 772
 773         hsusb: usb@e6590000 {
 774                 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 775                 reg = <0 0xe6590000 0 0x100>;
 776                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 777                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 778                 power-domains = <&cpg_clocks>;
 779                 renesas,buswait = <4>;
 780                 phys = <&usb0 1>;
 781                 phy-names = "usb";
 782                 status = "disabled";
 783         };
 784
 785         usbphy: usb-phy@e6590100 {
 786                 compatible = "renesas,usb-phy-r8a7794";
 787                 reg = <0 0xe6590100 0 0x100>;
 788                 #address-cells = <1>;
 789                 #size-cells = <0>;
 790                 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 791                 clock-names = "usbhs";
 792                 power-domains = <&cpg_clocks>;
 793                 status = "disabled";
 794
 795                 usb0: usb-channel@0 {
 796                         reg = <0>;
 797                         #phy-cells = <1>;
 798                 };
 799                 usb2: usb-channel@2 {
 800                         reg = <2>;
 801                         #phy-cells = <1>;
 802                 };
 803         };
 804
 805         du: display@feb00000 {
 806                 compatible = "renesas,du-r8a7794";
 807                 reg = <0 0xfeb00000 0 0x40000>;
 808                 reg-names = "du";
 809                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 810                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 811                 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 812                          <&mstp7_clks R8A7794_CLK_DU0>;
 813                 clock-names = "du.0", "du.1";
 814                 status = "disabled";
 815
 816                 ports {
 817                         #address-cells = <1>;
 818                         #size-cells = <0>;
 819
 820                         port@0 {
 821                                 reg = <0>;
 822                                 du_out_rgb0: endpoint {
 823                                 };
 824                         };
 825                         port@1 {
 826                                 reg = <1>;
 827                                 du_out_rgb1: endpoint {
 828                                 };
 829                         };
 830                 };
 831         };
 832
 833         clocks {
 834                 #address-cells = <2>;
 835                 #size-cells = <2>;
 836                 ranges;
 837
 838                 /* External root clock */
 839                 extal_clk: extal_clk {
 840                         compatible = "fixed-clock";
 841                         #clock-cells = <0>;
 842                         /* This value must be overriden by the board. */
 843                         clock-frequency = <0>;
 844                         clock-output-names = "extal";
 845                 };
 846
 847                 /* External SCIF clock */
 848                 scif_clk: scif {
 849                         compatible = "fixed-clock";
 850                         #clock-cells = <0>;
 851                         /* This value must be overridden by the board. */
 852                         clock-frequency = <0>;
 853                         status = "disabled";
 854                 };
 855
 856                 /* Special CPG clocks */
 857                 cpg_clocks: cpg_clocks@e6150000 {
 858                         compatible = "renesas,r8a7794-cpg-clocks",
 859                                      "renesas,rcar-gen2-cpg-clocks";
 860                         reg = <0 0xe6150000 0 0x1000>;
 861                         clocks = <&extal_clk>;
 862                         #clock-cells = <1>;
 863                         clock-output-names = "main", "pll0", "pll1", "pll3",
 864                                              "lb", "qspi", "sdh", "sd0", "z";
 865                         #power-domain-cells = <0>;
 866                 };
 867                 /* Variable factor clocks */
 868                 sd2_clk: sd2_clk@e6150078 {
 869                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 870                         reg = <0 0xe6150078 0 4>;
 871                         clocks = <&pll1_div2_clk>;
 872                         #clock-cells = <0>;
 873                         clock-output-names = "sd2";
 874                 };
 875                 sd3_clk: sd3_clk@e615026c {
 876                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 877                         reg = <0 0xe615026c 0 4>;
 878                         clocks = <&pll1_div2_clk>;
 879                         #clock-cells = <0>;
 880                         clock-output-names = "sd3";
 881                 };
 882                 mmc0_clk: mmc0_clk@e6150240 {
 883                         compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 884                         reg = <0 0xe6150240 0 4>;
 885                         clocks = <&pll1_div2_clk>;
 886                         #clock-cells = <0>;
 887                         clock-output-names = "mmc0";
 888                 };
 889
 890                 /* Fixed factor clocks */
 891                 pll1_div2_clk: pll1_div2_clk {
 892                         compatible = "fixed-factor-clock";
 893                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 894                         #clock-cells = <0>;
 895                         clock-div = <2>;
 896                         clock-mult = <1>;
 897                         clock-output-names = "pll1_div2";
 898                 };
 899                 zg_clk: zg_clk {
 900                         compatible = "fixed-factor-clock";
 901                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 902                         #clock-cells = <0>;
 903                         clock-div = <6>;
 904                         clock-mult = <1>;
 905                         clock-output-names = "zg";
 906                 };
 907                 zx_clk: zx_clk {
 908                         compatible = "fixed-factor-clock";
 909                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 910                         #clock-cells = <0>;
 911                         clock-div = <3>;
 912                         clock-mult = <1>;
 913                         clock-output-names = "zx";
 914                 };
 915                 zs_clk: zs_clk {
 916                         compatible = "fixed-factor-clock";
 917                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 918                         #clock-cells = <0>;
 919                         clock-div = <6>;
 920                         clock-mult = <1>;
 921                         clock-output-names = "zs";
 922                 };
 923                 hp_clk: hp_clk {
 924                         compatible = "fixed-factor-clock";
 925                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 926                         #clock-cells = <0>;
 927                         clock-div = <12>;
 928                         clock-mult = <1>;
 929                         clock-output-names = "hp";
 930                 };
 931                 i_clk: i_clk {
 932                         compatible = "fixed-factor-clock";
 933                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 934                         #clock-cells = <0>;
 935                         clock-div = <2>;
 936                         clock-mult = <1>;
 937                         clock-output-names = "i";
 938                 };
 939                 b_clk: b_clk {
 940                         compatible = "fixed-factor-clock";
 941                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 942                         #clock-cells = <0>;
 943                         clock-div = <12>;
 944                         clock-mult = <1>;
 945                         clock-output-names = "b";
 946                 };
 947                 p_clk: p_clk {
 948                         compatible = "fixed-factor-clock";
 949                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 950                         #clock-cells = <0>;
 951                         clock-div = <24>;
 952                         clock-mult = <1>;
 953                         clock-output-names = "p";
 954                 };
 955                 cl_clk: cl_clk {
 956                         compatible = "fixed-factor-clock";
 957                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 958                         #clock-cells = <0>;
 959                         clock-div = <48>;
 960                         clock-mult = <1>;
 961                         clock-output-names = "cl";
 962                 };
 963                 m2_clk: m2_clk {
 964                         compatible = "fixed-factor-clock";
 965                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 966                         #clock-cells = <0>;
 967                         clock-div = <8>;
 968                         clock-mult = <1>;
 969                         clock-output-names = "m2";
 970                 };
 971                 rclk_clk: rclk_clk {
 972                         compatible = "fixed-factor-clock";
 973                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 974                         #clock-cells = <0>;
 975                         clock-div = <(48 * 1024)>;
 976                         clock-mult = <1>;
 977                         clock-output-names = "rclk";
 978                 };
 979                 oscclk_clk: oscclk_clk {
 980                         compatible = "fixed-factor-clock";
 981                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 982                         #clock-cells = <0>;
 983                         clock-div = <(12 * 1024)>;
 984                         clock-mult = <1>;
 985                         clock-output-names = "oscclk";
 986                 };
 987                 zb3_clk: zb3_clk {
 988                         compatible = "fixed-factor-clock";
 989                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 990                         #clock-cells = <0>;
 991                         clock-div = <4>;
 992                         clock-mult = <1>;
 993                         clock-output-names = "zb3";
 994                 };
 995                 zb3d2_clk: zb3d2_clk {
 996                         compatible = "fixed-factor-clock";
 997                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 998                         #clock-cells = <0>;
 999                         clock-div = <8>;
1000                         clock-mult = <1>;
1001                         clock-output-names = "zb3d2";
1002                 };
1003                 ddr_clk: ddr_clk {
1004                         compatible = "fixed-factor-clock";
1005                         clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1006                         #clock-cells = <0>;
1007                         clock-div = <8>;
1008                         clock-mult = <1>;
1009                         clock-output-names = "ddr";
1010                 };
1011                 mp_clk: mp_clk {
1012                         compatible = "fixed-factor-clock";
1013                         clocks = <&pll1_div2_clk>;
1014                         #clock-cells = <0>;
1015                         clock-div = <15>;
1016                         clock-mult = <1>;
1017                         clock-output-names = "mp";
1018                 };
1019                 cp_clk: cp_clk {
1020                         compatible = "fixed-factor-clock";
1021                         clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1022                         #clock-cells = <0>;
1023                         clock-div = <48>;
1024                         clock-mult = <1>;
1025                         clock-output-names = "cp";
1026                 };
1027
1028                 acp_clk: acp_clk {
1029                         compatible = "fixed-factor-clock";
1030                         clocks = <&extal_clk>;
1031                         #clock-cells = <0>;
1032                         clock-div = <2>;
1033                         clock-mult = <1>;
1034                         clock-output-names = "acp";
1035                 };
1036
1037                 /* Gate clocks */
1038                 mstp0_clks: mstp0_clks@e6150130 {
1039                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1040                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1041                         clocks = <&mp_clk>;
1042                         #clock-cells = <1>;
1043                         clock-indices = <R8A7794_CLK_MSIOF0>;
1044                         clock-output-names = "msiof0";
1045                 };
1046                 mstp1_clks: mstp1_clks@e6150134 {
1047                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1048                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1049                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1050                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1051                                  <&zs_clk>, <&zs_clk>;
1052                         #clock-cells = <1>;
1053                         clock-indices = <
1054                                 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1055                                 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1056                                 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1057                                 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1058                         >;
1059                         clock-output-names =
1060                                 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1061                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1062                 };
1063                 mstp2_clks: mstp2_clks@e6150138 {
1064                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1065                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1066                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1067                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1068                                  <&zs_clk>, <&zs_clk>;
1069                         #clock-cells = <1>;
1070                         clock-indices = <
1071                                 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1072                                 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1073                                 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1074                                 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1075                         >;
1076                         clock-output-names =
1077                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1078                                 "scifb1", "msiof1", "scifb2",
1079                                 "sys-dmac1", "sys-dmac0";
1080                 };
1081                 mstp3_clks: mstp3_clks@e615013c {
1082                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1083                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1084                         clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1085                                  <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1086                         #clock-cells = <1>;
1087                         clock-indices = <
1088                                 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1089                                 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
1090                                 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1091                         >;
1092                         clock-output-names =
1093                                 "sdhi2", "sdhi1", "sdhi0",
1094                                 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
1095                 };
1096                 mstp4_clks: mstp4_clks@e6150140 {
1097                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1098                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1099                         clocks = <&cp_clk>;
1100                         #clock-cells = <1>;
1101                         clock-indices = <R8A7794_CLK_IRQC>;
1102                         clock-output-names = "irqc";
1103                 };
1104                 mstp7_clks: mstp7_clks@e615014c {
1105                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1106                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1107                         clocks = <&mp_clk>, <&mp_clk>,
1108                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1109                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1110                                  <&zx_clk>;
1111                         #clock-cells = <1>;
1112                         clock-indices = <
1113                                 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1114                                 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1115                                 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1116                                 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1117                                 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1118                         >;
1119                         clock-output-names =
1120                                 "ehci", "hsusb",
1121                                 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1122                                 "scif3", "scif2", "scif1", "scif0", "du0";
1123                 };
1124                 mstp8_clks: mstp8_clks@e6150990 {
1125                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1126                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1127                         clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1128                         #clock-cells = <1>;
1129                         clock-indices = <
1130                                 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1131                                 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1132                         >;
1133                         clock-output-names =
1134                                 "vin1", "vin0", "etheravb", "ether";
1135                 };
1136                 mstp9_clks: mstp9_clks@e6150994 {
1137                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1138                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1139                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1140                                  <&cp_clk>, <&cp_clk>, <&cp_clk>,
1141                                  <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
1142                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1143                         #clock-cells = <1>;
1144                         clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1145                                          R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1146                                          R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1147                                          R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
1148                                          R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1149                                          R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1150                                          R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1151                         clock-output-names =
1152                                 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1153                                 "gpio1", "gpio0", "qspi_mod",
1154                                 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1155                 };
1156                 mstp11_clks: mstp11_clks@e615099c {
1157                         compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1158                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1159                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1160                         #clock-cells = <1>;
1161                         clock-indices = <
1162                                 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1163                         >;
1164                         clock-output-names = "scifa3", "scifa4", "scifa5";
1165                 };
1166         };
1167
1168         ipmmu_sy0: mmu@e6280000 {
1169                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1170                 reg = <0 0xe6280000 0 0x1000>;
1171                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1172                              <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1173                 #iommu-cells = <1>;
1174                 status = "disabled";
1175         };
1176
1177         ipmmu_sy1: mmu@e6290000 {
1178                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1179                 reg = <0 0xe6290000 0 0x1000>;
1180                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1181                 #iommu-cells = <1>;
1182                 status = "disabled";
1183         };
1184
1185         ipmmu_ds: mmu@e6740000 {
1186                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1187                 reg = <0 0xe6740000 0 0x1000>;
1188                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1189                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1190                 #iommu-cells = <1>;
1191                 status = "disabled";
1192         };
1193
1194         ipmmu_mp: mmu@ec680000 {
1195                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1196                 reg = <0 0xec680000 0 0x1000>;
1197                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1198                 #iommu-cells = <1>;
1199                 status = "disabled";
1200         };
1201
1202         ipmmu_mx: mmu@fe951000 {
1203                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1204                 reg = <0 0xfe951000 0 0x1000>;
1205                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1206                              <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1207                 #iommu-cells = <1>;
1208                 status = "disabled";
1209         };
1210
1211         ipmmu_gp: mmu@e62a0000 {
1212                 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1213                 reg = <0 0xe62a0000 0 0x1000>;
1214                 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1215                              <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1216                 #iommu-cells = <1>;
1217                 status = "disabled";
1218         };
1219 };