2 * Device Tree Source for the r8a7794 SoC
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a7794-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a7";
44 clock-frequency = <1000000000>;
45 next-level-cache = <&L2_CA7>;
50 compatible = "arm,cortex-a7";
52 clock-frequency = <1000000000>;
53 next-level-cache = <&L2_CA7>;
57 L2_CA7: cache-controller@1 {
63 gic: interrupt-controller@f1001000 {
64 compatible = "arm,gic-400";
65 #interrupt-cells = <3>;
68 reg = <0 0xf1001000 0 0x1000>,
69 <0 0xf1002000 0 0x1000>,
70 <0 0xf1004000 0 0x2000>,
71 <0 0xf1006000 0 0x2000>;
72 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
75 gpio0: gpio@e6050000 {
76 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
77 reg = <0 0xe6050000 0 0x50>;
78 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
81 gpio-ranges = <&pfc 0 0 32>;
82 #interrupt-cells = <2>;
84 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
85 power-domains = <&cpg_clocks>;
88 gpio1: gpio@e6051000 {
89 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
90 reg = <0 0xe6051000 0 0x50>;
91 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
94 gpio-ranges = <&pfc 0 32 26>;
95 #interrupt-cells = <2>;
97 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
98 power-domains = <&cpg_clocks>;
101 gpio2: gpio@e6052000 {
102 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
103 reg = <0 0xe6052000 0 0x50>;
104 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
107 gpio-ranges = <&pfc 0 64 32>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
111 power-domains = <&cpg_clocks>;
114 gpio3: gpio@e6053000 {
115 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
116 reg = <0 0xe6053000 0 0x50>;
117 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
120 gpio-ranges = <&pfc 0 96 32>;
121 #interrupt-cells = <2>;
122 interrupt-controller;
123 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
124 power-domains = <&cpg_clocks>;
127 gpio4: gpio@e6054000 {
128 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
129 reg = <0 0xe6054000 0 0x50>;
130 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
133 gpio-ranges = <&pfc 0 128 32>;
134 #interrupt-cells = <2>;
135 interrupt-controller;
136 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
137 power-domains = <&cpg_clocks>;
140 gpio5: gpio@e6055000 {
141 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
142 reg = <0 0xe6055000 0 0x50>;
143 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
146 gpio-ranges = <&pfc 0 160 28>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
149 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
150 power-domains = <&cpg_clocks>;
153 gpio6: gpio@e6055400 {
154 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
155 reg = <0 0xe6055400 0 0x50>;
156 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
159 gpio-ranges = <&pfc 0 192 26>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
163 power-domains = <&cpg_clocks>;
166 cmt0: timer@ffca0000 {
167 compatible = "renesas,cmt-48-gen2";
168 reg = <0 0xffca0000 0 0x1004>;
169 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
173 power-domains = <&cpg_clocks>;
175 renesas,channels-mask = <0x60>;
180 cmt1: timer@e6130000 {
181 compatible = "renesas,cmt-48-gen2";
182 reg = <0 0xe6130000 0 0x1004>;
183 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
193 power-domains = <&cpg_clocks>;
195 renesas,channels-mask = <0xff>;
201 compatible = "arm,armv7-timer";
202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
208 irqc0: interrupt-controller@e61c0000 {
209 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
210 #interrupt-cells = <2>;
211 interrupt-controller;
212 reg = <0 0xe61c0000 0 0x200>;
213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
224 power-domains = <&cpg_clocks>;
227 pfc: pin-controller@e6060000 {
228 compatible = "renesas,pfc-r8a7794";
229 reg = <0 0xe6060000 0 0x11c>;
232 dmac0: dma-controller@e6700000 {
233 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
234 reg = <0 0xe6700000 0 0x20000>;
235 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
236 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
237 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
238 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
239 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
240 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
241 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
243 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
246 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
247 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
248 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
249 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
250 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-names = "error",
252 "ch0", "ch1", "ch2", "ch3",
253 "ch4", "ch5", "ch6", "ch7",
254 "ch8", "ch9", "ch10", "ch11",
255 "ch12", "ch13", "ch14";
256 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
258 power-domains = <&cpg_clocks>;
263 dmac1: dma-controller@e6720000 {
264 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
265 reg = <0 0xe6720000 0 0x20000>;
266 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
267 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
268 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
269 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
271 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
272 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
273 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
274 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
275 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
277 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
280 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
282 interrupt-names = "error",
283 "ch0", "ch1", "ch2", "ch3",
284 "ch4", "ch5", "ch6", "ch7",
285 "ch8", "ch9", "ch10", "ch11",
286 "ch12", "ch13", "ch14";
287 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
289 power-domains = <&cpg_clocks>;
294 scifa0: serial@e6c40000 {
295 compatible = "renesas,scifa-r8a7794",
296 "renesas,rcar-gen2-scifa", "renesas,scifa";
297 reg = <0 0xe6c40000 0 64>;
298 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
301 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
302 dma-names = "tx", "rx";
303 power-domains = <&cpg_clocks>;
307 scifa1: serial@e6c50000 {
308 compatible = "renesas,scifa-r8a7794",
309 "renesas,rcar-gen2-scifa", "renesas,scifa";
310 reg = <0 0xe6c50000 0 64>;
311 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
314 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
315 dma-names = "tx", "rx";
316 power-domains = <&cpg_clocks>;
320 scifa2: serial@e6c60000 {
321 compatible = "renesas,scifa-r8a7794",
322 "renesas,rcar-gen2-scifa", "renesas,scifa";
323 reg = <0 0xe6c60000 0 64>;
324 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
327 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
328 dma-names = "tx", "rx";
329 power-domains = <&cpg_clocks>;
333 scifa3: serial@e6c70000 {
334 compatible = "renesas,scifa-r8a7794",
335 "renesas,rcar-gen2-scifa", "renesas,scifa";
336 reg = <0 0xe6c70000 0 64>;
337 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
340 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
341 dma-names = "tx", "rx";
342 power-domains = <&cpg_clocks>;
346 scifa4: serial@e6c78000 {
347 compatible = "renesas,scifa-r8a7794",
348 "renesas,rcar-gen2-scifa", "renesas,scifa";
349 reg = <0 0xe6c78000 0 64>;
350 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
353 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
354 dma-names = "tx", "rx";
355 power-domains = <&cpg_clocks>;
359 scifa5: serial@e6c80000 {
360 compatible = "renesas,scifa-r8a7794",
361 "renesas,rcar-gen2-scifa", "renesas,scifa";
362 reg = <0 0xe6c80000 0 64>;
363 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
366 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
367 dma-names = "tx", "rx";
368 power-domains = <&cpg_clocks>;
372 scifb0: serial@e6c20000 {
373 compatible = "renesas,scifb-r8a7794",
374 "renesas,rcar-gen2-scifb", "renesas,scifb";
375 reg = <0 0xe6c20000 0 64>;
376 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
379 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
380 dma-names = "tx", "rx";
381 power-domains = <&cpg_clocks>;
385 scifb1: serial@e6c30000 {
386 compatible = "renesas,scifb-r8a7794",
387 "renesas,rcar-gen2-scifb", "renesas,scifb";
388 reg = <0 0xe6c30000 0 64>;
389 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
392 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
393 dma-names = "tx", "rx";
394 power-domains = <&cpg_clocks>;
398 scifb2: serial@e6ce0000 {
399 compatible = "renesas,scifb-r8a7794",
400 "renesas,rcar-gen2-scifb", "renesas,scifb";
401 reg = <0 0xe6ce0000 0 64>;
402 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
405 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
406 dma-names = "tx", "rx";
407 power-domains = <&cpg_clocks>;
411 scif0: serial@e6e60000 {
412 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
414 reg = <0 0xe6e60000 0 64>;
415 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
418 clock-names = "fck", "brg_int", "scif_clk";
419 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
420 dma-names = "tx", "rx";
421 power-domains = <&cpg_clocks>;
425 scif1: serial@e6e68000 {
426 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
428 reg = <0 0xe6e68000 0 64>;
429 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
432 clock-names = "fck", "brg_int", "scif_clk";
433 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
434 dma-names = "tx", "rx";
435 power-domains = <&cpg_clocks>;
439 scif2: serial@e6e58000 {
440 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
442 reg = <0 0xe6e58000 0 64>;
443 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
446 clock-names = "fck", "brg_int", "scif_clk";
447 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
448 dma-names = "tx", "rx";
449 power-domains = <&cpg_clocks>;
453 scif3: serial@e6ea8000 {
454 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
456 reg = <0 0xe6ea8000 0 64>;
457 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
460 clock-names = "fck", "brg_int", "scif_clk";
461 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
462 dma-names = "tx", "rx";
463 power-domains = <&cpg_clocks>;
467 scif4: serial@e6ee0000 {
468 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
470 reg = <0 0xe6ee0000 0 64>;
471 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
474 clock-names = "fck", "brg_int", "scif_clk";
475 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
476 dma-names = "tx", "rx";
477 power-domains = <&cpg_clocks>;
481 scif5: serial@e6ee8000 {
482 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
484 reg = <0 0xe6ee8000 0 64>;
485 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
488 clock-names = "fck", "brg_int", "scif_clk";
489 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
490 dma-names = "tx", "rx";
491 power-domains = <&cpg_clocks>;
495 hscif0: serial@e62c0000 {
496 compatible = "renesas,hscif-r8a7794",
497 "renesas,rcar-gen2-hscif", "renesas,hscif";
498 reg = <0 0xe62c0000 0 96>;
499 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
502 clock-names = "fck", "brg_int", "scif_clk";
503 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
504 dma-names = "tx", "rx";
505 power-domains = <&cpg_clocks>;
509 hscif1: serial@e62c8000 {
510 compatible = "renesas,hscif-r8a7794",
511 "renesas,rcar-gen2-hscif", "renesas,hscif";
512 reg = <0 0xe62c8000 0 96>;
513 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
516 clock-names = "fck", "brg_int", "scif_clk";
517 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
518 dma-names = "tx", "rx";
519 power-domains = <&cpg_clocks>;
523 hscif2: serial@e62d0000 {
524 compatible = "renesas,hscif-r8a7794",
525 "renesas,rcar-gen2-hscif", "renesas,hscif";
526 reg = <0 0xe62d0000 0 96>;
527 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
530 clock-names = "fck", "brg_int", "scif_clk";
531 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
532 dma-names = "tx", "rx";
533 power-domains = <&cpg_clocks>;
537 ether: ethernet@ee700000 {
538 compatible = "renesas,ether-r8a7794";
539 reg = <0 0xee700000 0 0x400>;
540 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
542 power-domains = <&cpg_clocks>;
544 #address-cells = <1>;
549 avb: ethernet@e6800000 {
550 compatible = "renesas,etheravb-r8a7794",
551 "renesas,etheravb-rcar-gen2";
552 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
553 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
555 power-domains = <&cpg_clocks>;
556 #address-cells = <1>;
561 /* The memory map in the User's Manual maps the cores to bus numbers */
563 compatible = "renesas,i2c-r8a7794";
564 reg = <0 0xe6508000 0 0x40>;
565 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
567 power-domains = <&cpg_clocks>;
568 #address-cells = <1>;
570 i2c-scl-internal-delay-ns = <6>;
575 compatible = "renesas,i2c-r8a7794";
576 reg = <0 0xe6518000 0 0x40>;
577 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
579 power-domains = <&cpg_clocks>;
580 #address-cells = <1>;
582 i2c-scl-internal-delay-ns = <6>;
587 compatible = "renesas,i2c-r8a7794";
588 reg = <0 0xe6530000 0 0x40>;
589 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
591 power-domains = <&cpg_clocks>;
592 #address-cells = <1>;
594 i2c-scl-internal-delay-ns = <6>;
599 compatible = "renesas,i2c-r8a7794";
600 reg = <0 0xe6540000 0 0x40>;
601 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
603 power-domains = <&cpg_clocks>;
604 #address-cells = <1>;
606 i2c-scl-internal-delay-ns = <6>;
611 compatible = "renesas,i2c-r8a7794";
612 reg = <0 0xe6520000 0 0x40>;
613 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
615 power-domains = <&cpg_clocks>;
616 #address-cells = <1>;
618 i2c-scl-internal-delay-ns = <6>;
623 compatible = "renesas,i2c-r8a7794";
624 reg = <0 0xe6528000 0 0x40>;
625 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
627 power-domains = <&cpg_clocks>;
628 #address-cells = <1>;
630 i2c-scl-internal-delay-ns = <6>;
635 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
636 reg = <0 0xe6500000 0 0x425>;
637 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
639 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
640 dma-names = "tx", "rx";
641 power-domains = <&cpg_clocks>;
642 #address-cells = <1>;
648 compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
649 reg = <0 0xe6510000 0 0x425>;
650 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
652 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
653 dma-names = "tx", "rx";
654 power-domains = <&cpg_clocks>;
655 #address-cells = <1>;
660 mmcif0: mmc@ee200000 {
661 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
662 reg = <0 0xee200000 0 0x80>;
663 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
665 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
666 dma-names = "tx", "rx";
667 power-domains = <&cpg_clocks>;
673 compatible = "renesas,sdhi-r8a7794";
674 reg = <0 0xee100000 0 0x200>;
675 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
677 power-domains = <&cpg_clocks>;
682 compatible = "renesas,sdhi-r8a7794";
683 reg = <0 0xee140000 0 0x100>;
684 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
686 power-domains = <&cpg_clocks>;
691 compatible = "renesas,sdhi-r8a7794";
692 reg = <0 0xee160000 0 0x100>;
693 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
695 power-domains = <&cpg_clocks>;
700 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
701 reg = <0 0xe6b10000 0 0x2c>;
702 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
704 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
705 dma-names = "tx", "rx";
706 power-domains = <&cpg_clocks>;
708 #address-cells = <1>;
713 vin0: video@e6ef0000 {
714 compatible = "renesas,vin-r8a7794";
715 reg = <0 0xe6ef0000 0 0x1000>;
716 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
718 power-domains = <&cpg_clocks>;
722 vin1: video@e6ef1000 {
723 compatible = "renesas,vin-r8a7794";
724 reg = <0 0xe6ef1000 0 0x1000>;
725 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
727 power-domains = <&cpg_clocks>;
732 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
734 reg = <0 0xee090000 0 0xc00>,
735 <0 0xee080000 0 0x1100>;
736 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
738 power-domains = <&cpg_clocks>;
742 #address-cells = <3>;
744 #interrupt-cells = <1>;
745 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
746 interrupt-map-mask = <0xff00 0 0 0x7>;
747 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
748 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
749 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
752 reg = <0x800 0 0 0 0>;
759 reg = <0x1000 0 0 0 0>;
767 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
769 reg = <0 0xee0d0000 0 0xc00>,
770 <0 0xee0c0000 0 0x1100>;
771 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
773 power-domains = <&cpg_clocks>;
777 #address-cells = <3>;
779 #interrupt-cells = <1>;
780 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
781 interrupt-map-mask = <0xff00 0 0 0x7>;
782 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
783 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
784 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
787 reg = <0x800 0 0 0 0>;
794 reg = <0x1000 0 0 0 0>;
801 hsusb: usb@e6590000 {
802 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
803 reg = <0 0xe6590000 0 0x100>;
804 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
806 power-domains = <&cpg_clocks>;
807 renesas,buswait = <4>;
813 usbphy: usb-phy@e6590100 {
814 compatible = "renesas,usb-phy-r8a7794";
815 reg = <0 0xe6590100 0 0x100>;
816 #address-cells = <1>;
818 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
819 clock-names = "usbhs";
820 power-domains = <&cpg_clocks>;
823 usb0: usb-channel@0 {
827 usb2: usb-channel@2 {
833 du: display@feb00000 {
834 compatible = "renesas,du-r8a7794";
835 reg = <0 0xfeb00000 0 0x40000>;
837 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
838 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
840 <&mstp7_clks R8A7794_CLK_DU0>;
841 clock-names = "du.0", "du.1";
845 #address-cells = <1>;
850 du_out_rgb0: endpoint {
855 du_out_rgb1: endpoint {
862 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
863 reg = <0 0xe6e80000 0 0x1000>;
864 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
866 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
867 clock-names = "clkp1", "clkp2", "can_clk";
868 power-domains = <&cpg_clocks>;
873 compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
874 reg = <0 0xe6e88000 0 0x1000>;
875 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
877 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
878 clock-names = "clkp1", "clkp2", "can_clk";
879 power-domains = <&cpg_clocks>;
884 #address-cells = <2>;
888 /* External root clock */
890 compatible = "fixed-clock";
892 /* This value must be overriden by the board. */
893 clock-frequency = <0>;
896 /* External USB clock - can be overridden by the board */
897 usb_extal_clk: usb_extal {
898 compatible = "fixed-clock";
900 clock-frequency = <48000000>;
903 /* External CAN clock */
905 compatible = "fixed-clock";
907 /* This value must be overridden by the board. */
908 clock-frequency = <0>;
911 /* External SCIF clock */
913 compatible = "fixed-clock";
915 /* This value must be overridden by the board. */
916 clock-frequency = <0>;
919 /* Special CPG clocks */
920 cpg_clocks: cpg_clocks@e6150000 {
921 compatible = "renesas,r8a7794-cpg-clocks",
922 "renesas,rcar-gen2-cpg-clocks";
923 reg = <0 0xe6150000 0 0x1000>;
924 clocks = <&extal_clk &usb_extal_clk>;
926 clock-output-names = "main", "pll0", "pll1", "pll3",
927 "lb", "qspi", "sdh", "sd0", "z",
929 #power-domain-cells = <0>;
931 /* Variable factor clocks */
932 sd2_clk: sd2@e6150078 {
933 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
934 reg = <0 0xe6150078 0 4>;
935 clocks = <&pll1_div2_clk>;
938 sd3_clk: sd3@e615026c {
939 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
940 reg = <0 0xe615026c 0 4>;
941 clocks = <&pll1_div2_clk>;
944 mmc0_clk: mmc0@e6150240 {
945 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
946 reg = <0 0xe6150240 0 4>;
947 clocks = <&pll1_div2_clk>;
951 /* Fixed factor clocks */
952 pll1_div2_clk: pll1_div2 {
953 compatible = "fixed-factor-clock";
954 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
960 compatible = "fixed-factor-clock";
961 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
967 compatible = "fixed-factor-clock";
968 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
974 compatible = "fixed-factor-clock";
975 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
981 compatible = "fixed-factor-clock";
982 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
988 compatible = "fixed-factor-clock";
989 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
995 compatible = "fixed-factor-clock";
996 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1002 compatible = "fixed-factor-clock";
1003 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1009 compatible = "fixed-factor-clock";
1010 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1016 compatible = "fixed-factor-clock";
1017 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1023 compatible = "fixed-factor-clock";
1024 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1026 clock-div = <(48 * 1024)>;
1029 oscclk_clk: oscclk {
1030 compatible = "fixed-factor-clock";
1031 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1033 clock-div = <(12 * 1024)>;
1037 compatible = "fixed-factor-clock";
1038 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1044 compatible = "fixed-factor-clock";
1045 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1051 compatible = "fixed-factor-clock";
1052 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1058 compatible = "fixed-factor-clock";
1059 clocks = <&pll1_div2_clk>;
1065 compatible = "fixed-factor-clock";
1066 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1073 compatible = "fixed-factor-clock";
1074 clocks = <&extal_clk>;
1081 mstp0_clks: mstp0_clks@e6150130 {
1082 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1083 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1086 clock-indices = <R8A7794_CLK_MSIOF0>;
1087 clock-output-names = "msiof0";
1089 mstp1_clks: mstp1_clks@e6150134 {
1090 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1091 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1092 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1093 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1094 <&zs_clk>, <&zs_clk>;
1097 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1098 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1099 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1100 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1102 clock-output-names =
1103 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1104 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1106 mstp2_clks: mstp2_clks@e6150138 {
1107 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1108 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1109 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1110 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1111 <&zs_clk>, <&zs_clk>;
1114 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1115 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1116 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1117 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1119 clock-output-names =
1120 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1121 "scifb1", "msiof1", "scifb2",
1122 "sys-dmac1", "sys-dmac0";
1124 mstp3_clks: mstp3_clks@e615013c {
1125 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1126 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1127 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1128 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
1129 <&hp_clk>, <&hp_clk>;
1132 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1133 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
1134 R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
1135 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1137 clock-output-names =
1138 "sdhi2", "sdhi1", "sdhi0",
1139 "mmcif0", "i2c6", "i2c7",
1140 "cmt1", "usbdmac0", "usbdmac1";
1142 mstp4_clks: mstp4_clks@e6150140 {
1143 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1144 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1147 clock-indices = <R8A7794_CLK_IRQC>;
1148 clock-output-names = "irqc";
1150 mstp7_clks: mstp7_clks@e615014c {
1151 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1152 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1153 clocks = <&mp_clk>, <&mp_clk>,
1154 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1155 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1159 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1160 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1161 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1162 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1163 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1165 clock-output-names =
1167 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1168 "scif3", "scif2", "scif1", "scif0", "du0";
1170 mstp8_clks: mstp8_clks@e6150990 {
1171 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1172 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1173 clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1176 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1177 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1179 clock-output-names =
1180 "vin1", "vin0", "etheravb", "ether";
1182 mstp9_clks: mstp9_clks@e6150994 {
1183 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1184 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1185 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1186 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
1187 <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
1188 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1189 <&hp_clk>, <&hp_clk>;
1191 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1192 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1193 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1194 R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
1195 R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
1196 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1197 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1198 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1199 clock-output-names =
1200 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1201 "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
1202 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1204 mstp11_clks: mstp11_clks@e615099c {
1205 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1206 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1207 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1210 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1212 clock-output-names = "scifa3", "scifa4", "scifa5";
1216 ipmmu_sy0: mmu@e6280000 {
1217 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1218 reg = <0 0xe6280000 0 0x1000>;
1219 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1222 status = "disabled";
1225 ipmmu_sy1: mmu@e6290000 {
1226 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1227 reg = <0 0xe6290000 0 0x1000>;
1228 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1230 status = "disabled";
1233 ipmmu_ds: mmu@e6740000 {
1234 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1235 reg = <0 0xe6740000 0 0x1000>;
1236 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1239 status = "disabled";
1242 ipmmu_mp: mmu@ec680000 {
1243 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1244 reg = <0 0xec680000 0 0x1000>;
1245 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1247 status = "disabled";
1250 ipmmu_mx: mmu@fe951000 {
1251 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1252 reg = <0 0xfe951000 0 0x1000>;
1253 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1256 status = "disabled";
1259 ipmmu_gp: mmu@e62a0000 {
1260 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1261 reg = <0 0xe62a0000 0 0x1000>;
1262 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1265 status = "disabled";