2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/rockchip.h>
18 #include <dt-bindings/clock/rk3188-cru.h>
19 #include "rk3xxx.dtsi"
22 compatible = "rockchip,rk3188";
27 enable-method = "rockchip,rk3066-smp";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
43 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "mmio-sram";
57 reg = <0x10080000 0x8000>;
60 ranges = <0 0x10080000 0x8000>;
63 compatible = "rockchip,rk3066-smp-sram";
68 cru: clock-controller@20000000 {
69 compatible = "rockchip,rk3188-cru";
70 reg = <0x20000000 0x1000>;
71 rockchip,grf = <&grf>;
78 compatible = "rockchip,rk3188-pinctrl";
79 rockchip,grf = <&grf>;
80 rockchip,pmu = <&pmu>;
86 gpio0: gpio0@0x2000a000 {
87 compatible = "rockchip,rk3188-gpio-bank0";
88 reg = <0x2000a000 0x100>;
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&cru PCLK_GPIO0>;
96 #interrupt-cells = <2>;
99 gpio1: gpio1@0x2003c000 {
100 compatible = "rockchip,gpio-bank";
101 reg = <0x2003c000 0x100>;
102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&cru PCLK_GPIO1>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
112 gpio2: gpio2@2003e000 {
113 compatible = "rockchip,gpio-bank";
114 reg = <0x2003e000 0x100>;
115 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cru PCLK_GPIO2>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
125 gpio3: gpio3@20080000 {
126 compatible = "rockchip,gpio-bank";
127 reg = <0x20080000 0x100>;
128 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&cru PCLK_GPIO3>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
138 pcfg_pull_up: pcfg_pull_up {
142 pcfg_pull_down: pcfg_pull_down {
146 pcfg_pull_none: pcfg_pull_none {
152 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
156 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
160 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
164 * The data pins are shared between nandc and emmc and
165 * not accessible through pinctrl. Also they should've
166 * been already set correctly by firmware, as
167 * flash/emmc is the boot-device.
172 i2c0_xfer: i2c0-xfer {
173 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
174 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
179 i2c1_xfer: i2c1-xfer {
180 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
181 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
186 i2c2_xfer: i2c2-xfer {
187 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
188 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
193 i2c3_xfer: i2c3-xfer {
194 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
195 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
200 i2c4_xfer: i2c4-xfer {
201 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
202 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
208 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
214 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
220 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
226 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
232 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
235 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
238 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
241 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
244 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
250 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
253 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
256 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
259 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
262 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
267 uart0_xfer: uart0-xfer {
268 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
269 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
272 uart0_cts: uart0-cts {
273 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
276 uart0_rts: uart0-rts {
277 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
282 uart1_xfer: uart1-xfer {
283 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
284 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
287 uart1_cts: uart1-cts {
288 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
291 uart1_rts: uart1-rts {
292 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
297 uart2_xfer: uart2-xfer {
298 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
299 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
301 /* no rts / cts for uart2 */
305 uart3_xfer: uart3-xfer {
306 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
307 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
310 uart3_cts: uart3-cts {
311 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
314 uart3_rts: uart3-rts {
315 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
321 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
325 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
329 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
333 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
337 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
340 sd0_bus1: sd0-bus-width1 {
341 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
344 sd0_bus4: sd0-bus-width4 {
345 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
346 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
347 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
348 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
354 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
358 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
362 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
366 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
369 sd1_bus1: sd1-bus-width1 {
370 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
373 sd1_bus4: sd1-bus-width4 {
374 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
375 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
376 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
377 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
384 interrupts = <GIC_PPI 11 0xf04>;
388 interrupts = <GIC_PPI 13 0xf04>;
392 compatible = "rockchip,rk3188-i2c";
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c0_xfer>;
398 compatible = "rockchip,rk3188-i2c";
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2c1_xfer>;
404 compatible = "rockchip,rk3188-i2c";
405 pinctrl-names = "default";
406 pinctrl-0 = <&i2c2_xfer>;
410 compatible = "rockchip,rk3188-i2c";
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c3_xfer>;
416 compatible = "rockchip,rk3188-i2c";
417 pinctrl-names = "default";
418 pinctrl-0 = <&i2c4_xfer>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&pwm0_out>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pwm1_out>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&pwm2_out>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&pwm3_out>;
442 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
443 pinctrl-names = "default";
444 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
448 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
449 pinctrl-names = "default";
450 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&uart0_xfer>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&uart1_xfer>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&uart2_xfer>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&uart3_xfer>;
474 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";