arch/arm/boot/dts/rk3288-veyron.dtsi

   1 /*
   2  * Google Veyron (and derivatives) board device tree source
   3  *
   4  * Copyright 2015 Google, Inc
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *  Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/rockchip,rk808.h>
  46 #include <dt-bindings/input/input.h>
  47 #include "rk3288.dtsi"
  48
  49 / {
  50         memory {
  51                 device_type = "memory";
  52                 reg = <0x0 0x80000000>;
  53         };
  54
  55         gpio_keys: gpio-keys {
  56                 compatible = "gpio-keys";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pwr_key_l>;
  62                 power {
  63                         label = "Power";
  64                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
  65                         linux,code = <KEY_POWER>;
  66                         debounce-interval = <100>;
  67                         wakeup-source;
  68                 };
  69         };
  70
  71         gpio-restart {
  72                 compatible = "gpio-restart";
  73                 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&ap_warm_reset_h>;
  76                 priority = <200>;
  77         };
  78
  79         emmc_pwrseq: emmc-pwrseq {
  80                 compatible = "mmc-pwrseq-emmc";
  81                 pinctrl-0 = <&emmc_reset>;
  82                 pinctrl-names = "default";
  83                 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
  84         };
  85
  86         io_domains: io-domains {
  87                 compatible = "rockchip,rk3288-io-voltage-domain";
  88                 rockchip,grf = <&grf>;
  89
  90                 bb-supply = <&vcc33_io>;
  91                 dvp-supply = <&vcc_18>;
  92                 flash0-supply = <&vcc18_flashio>;
  93                 gpio1830-supply = <&vcc33_io>;
  94                 gpio30-supply = <&vcc33_io>;
  95                 lcdc-supply = <&vcc33_lcd>;
  96                 wifi-supply = <&vcc18_wl>;
  97         };
  98
  99         sdio_pwrseq: sdio-pwrseq {
 100                 compatible = "mmc-pwrseq-simple";
 101                 clocks = <&rk808 RK808_CLKOUT1>;
 102                 clock-names = "ext_clock";
 103                 pinctrl-names = "default";
 104                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
 105
 106                 /*
 107                  * On the module itself this is one of these (depending
 108                  * on the actual card populated):
 109                  * - SDIO_RESET_L_WL_REG_ON
 110                  * - PDN (power down when low)
 111                  */
 112                 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 113         };
 114
 115         vcc_5v: vcc-5v {
 116                 compatible = "regulator-fixed";
 117                 regulator-name = "vcc_5v";
 118                 regulator-always-on;
 119                 regulator-boot-on;
 120                 regulator-min-microvolt = <5000000>;
 121                 regulator-max-microvolt = <5000000>;
 122         };
 123
 124         vcc33_sys: vcc33-sys {
 125                 compatible = "regulator-fixed";
 126                 regulator-name = "vcc33_sys";
 127                 regulator-always-on;
 128                 regulator-boot-on;
 129                 regulator-min-microvolt = <3300000>;
 130                 regulator-max-microvolt = <3300000>;
 131         };
 132
 133         vcc50_hdmi: vcc50-hdmi {
 134                 compatible = "regulator-fixed";
 135                 regulator-name = "vcc50_hdmi";
 136                 regulator-always-on;
 137                 regulator-boot-on;
 138                 vin-supply = <&vcc_5v>;
 139         };
 140 };
 141
 142 &cpu0 {
 143         cpu0-supply = <&vdd_cpu>;
 144         operating-points = <
 145                 /* KHz    uV */
 146                 1800000 1400000
 147                 1704000 1350000
 148                 1608000 1300000
 149                 1512000 1250000
 150                 1416000 1200000
 151                 1200000 1100000
 152                 1008000 1050000
 153                  816000 1000000
 154                  696000  950000
 155                  600000  900000
 156                  408000  900000
 157                  216000  900000
 158                  126000  900000
 159         >;
 160 };
 161
 162 &emmc {
 163         status = "okay";
 164
 165         bus-width = <8>;
 166         cap-mmc-highspeed;
 167         rockchip,default-sample-phase = <158>;
 168         disable-wp;
 169         mmc-hs200-1_8v;
 170         mmc-pwrseq = <&emmc_pwrseq>;
 171         non-removable;
 172         num-slots = <1>;
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 175 };
 176
 177 &hdmi {
 178         ddc-i2c-bus = <&i2c5>;
 179         status = "okay";
 180 };
 181
 182 &i2c0 {
 183         status = "okay";
 184
 185         clock-frequency = <400000>;
 186         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 187         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 188
 189         rk808: pmic@1b {
 190                 compatible = "rockchip,rk808";
 191                 reg = <0x1b>;
 192                 clock-output-names = "xin32k", "wifibt_32kin";
 193                 interrupt-parent = <&gpio0>;
 194                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 195                 pinctrl-names = "default";
 196                 pinctrl-0 = <&pmic_int_l>;
 197                 rockchip,system-power-controller;
 198                 wakeup-source;
 199                 #clock-cells = <1>;
 200
 201                 vcc1-supply = <&vcc33_sys>;
 202                 vcc2-supply = <&vcc33_sys>;
 203                 vcc3-supply = <&vcc33_sys>;
 204                 vcc4-supply = <&vcc33_sys>;
 205                 vcc6-supply = <&vcc_5v>;
 206                 vcc7-supply = <&vcc33_sys>;
 207                 vcc8-supply = <&vcc33_sys>;
 208                 vcc12-supply = <&vcc_18>;
 209                 vddio-supply = <&vcc33_io>;
 210
 211                 regulators {
 212                         vdd_cpu: DCDC_REG1 {
 213                                 regulator-name = "vdd_arm";
 214                                 regulator-always-on;
 215                                 regulator-boot-on;
 216                                 regulator-min-microvolt = <750000>;
 217                                 regulator-max-microvolt = <1450000>;
 218                                 regulator-ramp-delay = <6001>;
 219                                 regulator-state-mem {
 220                                         regulator-off-in-suspend;
 221                                 };
 222                         };
 223
 224                         vdd_gpu: DCDC_REG2 {
 225                                 regulator-name = "vdd_gpu";
 226                                 regulator-always-on;
 227                                 regulator-boot-on;
 228                                 regulator-min-microvolt = <800000>;
 229                                 regulator-max-microvolt = <1250000>;
 230                                 regulator-ramp-delay = <6001>;
 231                                 regulator-state-mem {
 232                                         regulator-on-in-suspend;
 233                                         regulator-suspend-microvolt = <1000000>;
 234                                 };
 235                         };
 236
 237                         vcc135_ddr: DCDC_REG3 {
 238                                 regulator-name = "vcc135_ddr";
 239                                 regulator-always-on;
 240                                 regulator-boot-on;
 241                                 regulator-state-mem {
 242                                         regulator-on-in-suspend;
 243                                 };
 244                         };
 245
 246                         /*
 247                          * vcc_18 has several aliases.  (vcc18_flashio and
 248                          * vcc18_wl).  We'll add those aliases here just to
 249                          * make it easier to follow the schematic.  The signals
 250                          * are actually hooked together and only separated for
 251                          * power measurement purposes).
 252                          */
 253                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 254                                 regulator-name = "vcc_18";
 255                                 regulator-always-on;
 256                                 regulator-boot-on;
 257                                 regulator-min-microvolt = <1800000>;
 258                                 regulator-max-microvolt = <1800000>;
 259                                 regulator-state-mem {
 260                                         regulator-on-in-suspend;
 261                                         regulator-suspend-microvolt = <1800000>;
 262                                 };
 263                         };
 264
 265                         /*
 266                          * Note that both vcc33_io and vcc33_pmuio are always
 267                          * powered together. To simplify the logic in the dts
 268                          * we just refer to vcc33_io every time something is
 269                          * powered from vcc33_pmuio. In fact, on later boards
 270                          * (such as danger) they're the same net.
 271                          */
 272                         vcc33_io: LDO_REG1 {
 273                                 regulator-name = "vcc33_io";
 274                                 regulator-always-on;
 275                                 regulator-boot-on;
 276                                 regulator-min-microvolt = <3300000>;
 277                                 regulator-max-microvolt = <3300000>;
 278                                 regulator-state-mem {
 279                                         regulator-on-in-suspend;
 280                                         regulator-suspend-microvolt = <3300000>;
 281                                 };
 282                         };
 283
 284                         vdd_10: LDO_REG3 {
 285                                 regulator-name = "vdd_10";
 286                                 regulator-always-on;
 287                                 regulator-boot-on;
 288                                 regulator-min-microvolt = <1000000>;
 289                                 regulator-max-microvolt = <1000000>;
 290                                 regulator-state-mem {
 291                                         regulator-on-in-suspend;
 292                                         regulator-suspend-microvolt = <1000000>;
 293                                 };
 294                         };
 295
 296                         vdd10_lcd_pwren_h: LDO_REG7 {
 297                                 regulator-name = "vdd10_lcd_pwren_h";
 298                                 regulator-always-on;
 299                                 regulator-boot-on;
 300                                 regulator-min-microvolt = <2500000>;
 301                                 regulator-max-microvolt = <2500000>;
 302                                 regulator-state-mem {
 303                                         regulator-off-in-suspend;
 304                                 };
 305                         };
 306
 307                         vcc33_lcd: SWITCH_REG1 {
 308                                 regulator-name = "vcc33_lcd";
 309                                 regulator-always-on;
 310                                 regulator-boot-on;
 311                                 regulator-state-mem {
 312                                         regulator-off-in-suspend;
 313                                 };
 314                         };
 315                 };
 316         };
 317 };
 318
 319 &i2c1 {
 320         status = "okay";
 321
 322         clock-frequency = <400000>;
 323         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 324         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 325
 326         tpm: tpm@20 {
 327                 compatible = "infineon,slb9645tt";
 328                 reg = <0x20>;
 329                 powered-while-suspended;
 330         };
 331 };
 332
 333 &i2c2 {
 334         status = "okay";
 335
 336         /* 100kHz since 4.7k resistors don't rise fast enough */
 337         clock-frequency = <100000>;
 338         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 339         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 340 };
 341
 342 &i2c4 {
 343         status = "okay";
 344
 345         clock-frequency = <400000>;
 346         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 347         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 348 };
 349
 350 &i2c5 {
 351         status = "okay";
 352
 353         clock-frequency = <100000>;
 354         i2c-scl-falling-time-ns = <300>;
 355         i2c-scl-rising-time-ns = <1000>;
 356 };
 357
 358 &pwm1 {
 359         status = "okay";
 360 };
 361
 362 &sdio0 {
 363         status = "okay";
 364
 365         bus-width = <4>;
 366         cap-sd-highspeed;
 367         cap-sdio-irq;
 368         keep-power-in-suspend;
 369         mmc-pwrseq = <&sdio_pwrseq>;
 370         non-removable;
 371         num-slots = <1>;
 372         pinctrl-names = "default";
 373         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 374         sd-uhs-sdr12;
 375         sd-uhs-sdr25;
 376         sd-uhs-sdr50;
 377         sd-uhs-sdr104;
 378         vmmc-supply = <&vcc33_sys>;
 379         vqmmc-supply = <&vcc18_wl>;
 380 };
 381
 382 &spi2 {
 383         status = "okay";
 384
 385         rx-sample-delay-ns = <12>;
 386 };
 387
 388 &tsadc {
 389         status = "okay";
 390
 391         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 392         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 393 };
 394
 395 &uart0 {
 396         status = "okay";
 397
 398         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 399         assigned-clocks = <&cru SCLK_UART0>;
 400         assigned-clock-rates = <48000000>;
 401
 402         /* Pins don't include flow control by default; add that in */
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 405 };
 406
 407 &uart1 {
 408         status = "okay";
 409 };
 410
 411 &uart2 {
 412         status = "okay";
 413 };
 414
 415 &usbphy {
 416         status = "okay";
 417 };
 418
 419 &usb_host0_ehci {
 420         status = "okay";
 421
 422         needs-reset-on-resume;
 423 };
 424
 425 &usb_host1 {
 426         status = "okay";
 427 };
 428
 429 &usb_otg {
 430         status = "okay";
 431
 432         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 433         assigned-clock-parents = <&usbphy0>;
 434         dr_mode = "host";
 435 };
 436
 437 &vopb {
 438         status = "okay";
 439 };
 440
 441 &vopb_mmu {
 442         status = "okay";
 443 };
 444
 445 &wdt {
 446         status = "okay";
 447 };
 448
 449 &pinctrl {
 450         pinctrl-names = "default", "sleep";
 451         pinctrl-0 = <
 452                 /* Common for sleep and wake, but no owners */
 453                 &global_pwroff
 454         >;
 455         pinctrl-1 = <
 456                 /* Common for sleep and wake, but no owners */
 457                 &global_pwroff
 458         >;
 459
 460         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 461                 bias-disable;
 462                 drive-strength = <8>;
 463         };
 464
 465         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 466                 bias-pull-up;
 467                 drive-strength = <8>;
 468         };
 469
 470         pcfg_output_high: pcfg-output-high {
 471                 output-high;
 472         };
 473
 474         pcfg_output_low: pcfg-output-low {
 475                 output-low;
 476         };
 477
 478         buttons {
 479                 pwr_key_l: pwr-key-l {
 480                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
 481                 };
 482         };
 483
 484         emmc {
 485                 emmc_reset: emmc-reset {
 486                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 487                 };
 488
 489                 /*
 490                  * We run eMMC at max speed; bump up drive strength.
 491                  * We also have external pulls, so disable the internal ones.
 492                  */
 493                 emmc_clk: emmc-clk {
 494                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 495                 };
 496
 497                 emmc_cmd: emmc-cmd {
 498                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 499                 };
 500
 501                 emmc_bus8: emmc-bus8 {
 502                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 503                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 504                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 505                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 506                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 507                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 508                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 509                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 510                 };
 511         };
 512
 513         pmic {
 514                 pmic_int_l: pmic-int-l {
 515                         rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 516                 };
 517         };
 518
 519         reboot {
 520                 ap_warm_reset_h: ap-warm-reset-h {
 521                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 522                 };
 523         };
 524
 525         recovery-switch {
 526                 rec_mode_l: rec-mode-l {
 527                         rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
 528                 };
 529         };
 530
 531         sdio0 {
 532                 wifi_enable_h: wifienable-h {
 533                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 534                 };
 535
 536                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 537                 bt_enable_l: bt-enable-l {
 538                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 539                 };
 540
 541                 /*
 542                  * We run sdio0 at max speed; bump up drive strength.
 543                  * We also have external pulls, so disable the internal ones.
 544                  */
 545                 sdio0_bus4: sdio0-bus4 {
 546                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 547                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 548                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 549                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 550                 };
 551
 552                 sdio0_cmd: sdio0-cmd {
 553                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 554                 };
 555
 556                 sdio0_clk: sdio0-clk {
 557                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 558                 };
 559         };
 560
 561         tpm {
 562                 tpm_int_h: tpm-int-h {
 563                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 564                 };
 565         };
 566
 567         write-protect {
 568                 fw_wp_ap: fw-wp-ap {
 569                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 570                 };
 571         };
 572 };