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ARM: dts: rockchip: add eFuse config of rk3288 SoC
[deliverable/linux.git] / arch / arm / boot / dts / rk3288.dtsi
1 /*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include "skeleton.dtsi"
49
50 / {
51 compatible = "rockchip,rk3288";
52
53 interrupt-parent = <&gic>;
54
55 aliases {
56 ethernet0 = &gmac;
57 i2c0 = &i2c0;
58 i2c1 = &i2c1;
59 i2c2 = &i2c2;
60 i2c3 = &i2c3;
61 i2c4 = &i2c4;
62 i2c5 = &i2c5;
63 mshc0 = &emmc;
64 mshc1 = &sdmmc;
65 mshc2 = &sdio0;
66 mshc3 = &sdio1;
67 serial0 = &uart0;
68 serial1 = &uart1;
69 serial2 = &uart2;
70 serial3 = &uart3;
71 serial4 = &uart4;
72 spi0 = &spi0;
73 spi1 = &spi1;
74 spi2 = &spi2;
75 };
76
77 arm-pmu {
78 compatible = "arm,cortex-a12-pmu";
79 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
84 };
85
86 cpus {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 enable-method = "rockchip,rk3066-smp";
90 rockchip,pmu = <&pmu>;
91
92 cpu0: cpu@500 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a12";
95 reg = <0x500>;
96 resets = <&cru SRST_CORE0>;
97 operating-points = <
98 /* KHz uV */
99 1608000 1350000
100 1512000 1300000
101 1416000 1200000
102 1200000 1100000
103 1008000 1050000
104 816000 1000000
105 696000 950000
106 600000 900000
107 408000 900000
108 312000 900000
109 216000 900000
110 126000 900000
111 >;
112 #cooling-cells = <2>; /* min followed by max */
113 clock-latency = <40000>;
114 clocks = <&cru ARMCLK>;
115 };
116 cpu1: cpu@501 {
117 device_type = "cpu";
118 compatible = "arm,cortex-a12";
119 reg = <0x501>;
120 resets = <&cru SRST_CORE1>;
121 };
122 cpu2: cpu@502 {
123 device_type = "cpu";
124 compatible = "arm,cortex-a12";
125 reg = <0x502>;
126 resets = <&cru SRST_CORE2>;
127 };
128 cpu3: cpu@503 {
129 device_type = "cpu";
130 compatible = "arm,cortex-a12";
131 reg = <0x503>;
132 resets = <&cru SRST_CORE3>;
133 };
134 };
135
136 amba {
137 compatible = "arm,amba-bus";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges;
141
142 dmac_peri: dma-controller@ff250000 {
143 compatible = "arm,pl330", "arm,primecell";
144 reg = <0xff250000 0x4000>;
145 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
147 #dma-cells = <1>;
148 clocks = <&cru ACLK_DMAC2>;
149 clock-names = "apb_pclk";
150 };
151
152 dmac_bus_ns: dma-controller@ff600000 {
153 compatible = "arm,pl330", "arm,primecell";
154 reg = <0xff600000 0x4000>;
155 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
157 #dma-cells = <1>;
158 clocks = <&cru ACLK_DMAC1>;
159 clock-names = "apb_pclk";
160 status = "disabled";
161 };
162
163 dmac_bus_s: dma-controller@ffb20000 {
164 compatible = "arm,pl330", "arm,primecell";
165 reg = <0xffb20000 0x4000>;
166 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
168 #dma-cells = <1>;
169 clocks = <&cru ACLK_DMAC1>;
170 clock-names = "apb_pclk";
171 };
172 };
173
174 reserved-memory {
175 #address-cells = <1>;
176 #size-cells = <1>;
177 ranges;
178
179 /*
180 * The rk3288 cannot use the memory area above 0xfe000000
181 * for dma operations for some reason. While there is
182 * probably a better solution available somewhere, we
183 * haven't found it yet and while devices with 2GB of ram
184 * are not affected, this issue prevents 4GB from booting.
185 * So to make these devices at least bootable, block
186 * this area for the time being until the real solution
187 * is found.
188 */
189 dma-unusable@fe000000 {
190 reg = <0xfe000000 0x1000000>;
191 };
192 };
193
194 xin24m: oscillator {
195 compatible = "fixed-clock";
196 clock-frequency = <24000000>;
197 clock-output-names = "xin24m";
198 #clock-cells = <0>;
199 };
200
201 timer {
202 compatible = "arm,armv7-timer";
203 arm,cpu-registers-not-fw-configured;
204 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
206 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
208 clock-frequency = <24000000>;
209 };
210
211 timer: timer@ff810000 {
212 compatible = "rockchip,rk3288-timer";
213 reg = <0xff810000 0x20>;
214 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&xin24m>, <&cru PCLK_TIMER>;
216 clock-names = "timer", "pclk";
217 };
218
219 display-subsystem {
220 compatible = "rockchip,display-subsystem";
221 ports = <&vopl_out>, <&vopb_out>;
222 };
223
224 sdmmc: dwmmc@ff0c0000 {
225 compatible = "rockchip,rk3288-dw-mshc";
226 clock-freq-min-max = <400000 150000000>;
227 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
228 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
229 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
230 fifo-depth = <0x100>;
231 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
232 reg = <0xff0c0000 0x4000>;
233 status = "disabled";
234 };
235
236 sdio0: dwmmc@ff0d0000 {
237 compatible = "rockchip,rk3288-dw-mshc";
238 clock-freq-min-max = <400000 150000000>;
239 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
240 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
242 fifo-depth = <0x100>;
243 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
244 reg = <0xff0d0000 0x4000>;
245 status = "disabled";
246 };
247
248 sdio1: dwmmc@ff0e0000 {
249 compatible = "rockchip,rk3288-dw-mshc";
250 clock-freq-min-max = <400000 150000000>;
251 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
252 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
253 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
254 fifo-depth = <0x100>;
255 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
256 reg = <0xff0e0000 0x4000>;
257 status = "disabled";
258 };
259
260 emmc: dwmmc@ff0f0000 {
261 compatible = "rockchip,rk3288-dw-mshc";
262 clock-freq-min-max = <400000 150000000>;
263 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
264 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
265 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
266 fifo-depth = <0x100>;
267 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
268 reg = <0xff0f0000 0x4000>;
269 status = "disabled";
270 };
271
272 saradc: saradc@ff100000 {
273 compatible = "rockchip,saradc";
274 reg = <0xff100000 0x100>;
275 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
276 #io-channel-cells = <1>;
277 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
278 clock-names = "saradc", "apb_pclk";
279 status = "disabled";
280 };
281
282 spi0: spi@ff110000 {
283 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
284 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
285 clock-names = "spiclk", "apb_pclk";
286 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
287 dma-names = "tx", "rx";
288 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
291 reg = <0xff110000 0x1000>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 status = "disabled";
295 };
296
297 spi1: spi@ff120000 {
298 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
299 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
300 clock-names = "spiclk", "apb_pclk";
301 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
302 dma-names = "tx", "rx";
303 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
306 reg = <0xff120000 0x1000>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 status = "disabled";
310 };
311
312 spi2: spi@ff130000 {
313 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
314 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
315 clock-names = "spiclk", "apb_pclk";
316 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
317 dma-names = "tx", "rx";
318 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
321 reg = <0xff130000 0x1000>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 status = "disabled";
325 };
326
327 i2c1: i2c@ff140000 {
328 compatible = "rockchip,rk3288-i2c";
329 reg = <0xff140000 0x1000>;
330 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 clock-names = "i2c";
334 clocks = <&cru PCLK_I2C1>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&i2c1_xfer>;
337 status = "disabled";
338 };
339
340 i2c3: i2c@ff150000 {
341 compatible = "rockchip,rk3288-i2c";
342 reg = <0xff150000 0x1000>;
343 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clock-names = "i2c";
347 clocks = <&cru PCLK_I2C3>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c3_xfer>;
350 status = "disabled";
351 };
352
353 i2c4: i2c@ff160000 {
354 compatible = "rockchip,rk3288-i2c";
355 reg = <0xff160000 0x1000>;
356 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 clock-names = "i2c";
360 clocks = <&cru PCLK_I2C4>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c4_xfer>;
363 status = "disabled";
364 };
365
366 i2c5: i2c@ff170000 {
367 compatible = "rockchip,rk3288-i2c";
368 reg = <0xff170000 0x1000>;
369 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 clock-names = "i2c";
373 clocks = <&cru PCLK_I2C5>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c5_xfer>;
376 status = "disabled";
377 };
378
379 uart0: serial@ff180000 {
380 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
381 reg = <0xff180000 0x100>;
382 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
383 reg-shift = <2>;
384 reg-io-width = <4>;
385 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
386 clock-names = "baudclk", "apb_pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&uart0_xfer>;
389 status = "disabled";
390 };
391
392 uart1: serial@ff190000 {
393 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
394 reg = <0xff190000 0x100>;
395 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
396 reg-shift = <2>;
397 reg-io-width = <4>;
398 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
399 clock-names = "baudclk", "apb_pclk";
400 pinctrl-names = "default";
401 pinctrl-0 = <&uart1_xfer>;
402 status = "disabled";
403 };
404
405 uart2: serial@ff690000 {
406 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
407 reg = <0xff690000 0x100>;
408 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
409 reg-shift = <2>;
410 reg-io-width = <4>;
411 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
412 clock-names = "baudclk", "apb_pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&uart2_xfer>;
415 status = "disabled";
416 };
417
418 uart3: serial@ff1b0000 {
419 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
420 reg = <0xff1b0000 0x100>;
421 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
422 reg-shift = <2>;
423 reg-io-width = <4>;
424 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
425 clock-names = "baudclk", "apb_pclk";
426 pinctrl-names = "default";
427 pinctrl-0 = <&uart3_xfer>;
428 status = "disabled";
429 };
430
431 uart4: serial@ff1c0000 {
432 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
433 reg = <0xff1c0000 0x100>;
434 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
435 reg-shift = <2>;
436 reg-io-width = <4>;
437 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
438 clock-names = "baudclk", "apb_pclk";
439 pinctrl-names = "default";
440 pinctrl-0 = <&uart4_xfer>;
441 status = "disabled";
442 };
443
444 thermal-zones {
445 #include "rk3288-thermal.dtsi"
446 };
447
448 tsadc: tsadc@ff280000 {
449 compatible = "rockchip,rk3288-tsadc";
450 reg = <0xff280000 0x100>;
451 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
453 clock-names = "tsadc", "apb_pclk";
454 resets = <&cru SRST_TSADC>;
455 reset-names = "tsadc-apb";
456 pinctrl-names = "default";
457 pinctrl-0 = <&otp_out>;
458 #thermal-sensor-cells = <1>;
459 rockchip,hw-tshut-temp = <95000>;
460 status = "disabled";
461 };
462
463 gmac: ethernet@ff290000 {
464 compatible = "rockchip,rk3288-gmac";
465 reg = <0xff290000 0x10000>;
466 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-names = "macirq";
468 rockchip,grf = <&grf>;
469 clocks = <&cru SCLK_MAC>,
470 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
471 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
472 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
473 clock-names = "stmmaceth",
474 "mac_clk_rx", "mac_clk_tx",
475 "clk_mac_ref", "clk_mac_refout",
476 "aclk_mac", "pclk_mac";
477 resets = <&cru SRST_MAC>;
478 reset-names = "stmmaceth";
479 status = "disabled";
480 };
481
482 usb_host0_ehci: usb@ff500000 {
483 compatible = "generic-ehci";
484 reg = <0xff500000 0x100>;
485 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&cru HCLK_USBHOST0>;
487 clock-names = "usbhost";
488 phys = <&usbphy1>;
489 phy-names = "usb";
490 status = "disabled";
491 };
492
493 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
494
495 usb_host1: usb@ff540000 {
496 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
497 "snps,dwc2";
498 reg = <0xff540000 0x40000>;
499 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cru HCLK_USBHOST1>;
501 clock-names = "otg";
502 dr_mode = "host";
503 phys = <&usbphy2>;
504 phy-names = "usb2-phy";
505 status = "disabled";
506 };
507
508 usb_otg: usb@ff580000 {
509 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
510 "snps,dwc2";
511 reg = <0xff580000 0x40000>;
512 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cru HCLK_OTG0>;
514 clock-names = "otg";
515 dr_mode = "otg";
516 g-np-tx-fifo-size = <16>;
517 g-rx-fifo-size = <275>;
518 g-tx-fifo-size = <256 128 128 64 64 32>;
519 g-use-dma;
520 phys = <&usbphy0>;
521 phy-names = "usb2-phy";
522 status = "disabled";
523 };
524
525 usb_hsic: usb@ff5c0000 {
526 compatible = "generic-ehci";
527 reg = <0xff5c0000 0x100>;
528 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&cru HCLK_HSIC>;
530 clock-names = "usbhost";
531 status = "disabled";
532 };
533
534 i2c0: i2c@ff650000 {
535 compatible = "rockchip,rk3288-i2c";
536 reg = <0xff650000 0x1000>;
537 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
538 #address-cells = <1>;
539 #size-cells = <0>;
540 clock-names = "i2c";
541 clocks = <&cru PCLK_I2C0>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&i2c0_xfer>;
544 status = "disabled";
545 };
546
547 i2c2: i2c@ff660000 {
548 compatible = "rockchip,rk3288-i2c";
549 reg = <0xff660000 0x1000>;
550 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
551 #address-cells = <1>;
552 #size-cells = <0>;
553 clock-names = "i2c";
554 clocks = <&cru PCLK_I2C2>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2c2_xfer>;
557 status = "disabled";
558 };
559
560 pwm0: pwm@ff680000 {
561 compatible = "rockchip,rk3288-pwm";
562 reg = <0xff680000 0x10>;
563 #pwm-cells = <3>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&pwm0_pin>;
566 clocks = <&cru PCLK_PWM>;
567 clock-names = "pwm";
568 status = "disabled";
569 };
570
571 pwm1: pwm@ff680010 {
572 compatible = "rockchip,rk3288-pwm";
573 reg = <0xff680010 0x10>;
574 #pwm-cells = <3>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&pwm1_pin>;
577 clocks = <&cru PCLK_PWM>;
578 clock-names = "pwm";
579 status = "disabled";
580 };
581
582 pwm2: pwm@ff680020 {
583 compatible = "rockchip,rk3288-pwm";
584 reg = <0xff680020 0x10>;
585 #pwm-cells = <3>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&pwm2_pin>;
588 clocks = <&cru PCLK_PWM>;
589 clock-names = "pwm";
590 status = "disabled";
591 };
592
593 pwm3: pwm@ff680030 {
594 compatible = "rockchip,rk3288-pwm";
595 reg = <0xff680030 0x10>;
596 #pwm-cells = <2>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&pwm3_pin>;
599 clocks = <&cru PCLK_PWM>;
600 clock-names = "pwm";
601 status = "disabled";
602 };
603
604 bus_intmem@ff700000 {
605 compatible = "mmio-sram";
606 reg = <0xff700000 0x18000>;
607 #address-cells = <1>;
608 #size-cells = <1>;
609 ranges = <0 0xff700000 0x18000>;
610 smp-sram@0 {
611 compatible = "rockchip,rk3066-smp-sram";
612 reg = <0x00 0x10>;
613 };
614 };
615
616 sram@ff720000 {
617 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
618 reg = <0xff720000 0x1000>;
619 };
620
621 pmu: power-management@ff730000 {
622 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
623 reg = <0xff730000 0x100>;
624
625 power: power-controller {
626 compatible = "rockchip,rk3288-power-controller";
627 #power-domain-cells = <1>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630
631 /*
632 * Note: Although SCLK_* are the working clocks
633 * of device without including on the NOC, needed for
634 * synchronous reset.
635 *
636 * The clocks on the which NOC:
637 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
638 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
639 * ACLK_RGA is on ACLK_RGA_NIU.
640 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
641 *
642 * Which clock are device clocks:
643 * clocks devices
644 * *_IEP IEP:Image Enhancement Processor
645 * *_ISP ISP:Image Signal Processing
646 * *_VIP VIP:Video Input Processor
647 * *_VOP* VOP:Visual Output Processor
648 * *_RGA RGA
649 * *_EDP* EDP
650 * *_LVDS_* LVDS
651 * *_HDMI HDMI
652 * *_MIPI_* MIPI
653 */
654 pd_vio {
655 reg = <RK3288_PD_VIO>;
656 clocks = <&cru ACLK_IEP>,
657 <&cru ACLK_ISP>,
658 <&cru ACLK_RGA>,
659 <&cru ACLK_VIP>,
660 <&cru ACLK_VOP0>,
661 <&cru ACLK_VOP1>,
662 <&cru DCLK_VOP0>,
663 <&cru DCLK_VOP1>,
664 <&cru HCLK_IEP>,
665 <&cru HCLK_ISP>,
666 <&cru HCLK_RGA>,
667 <&cru HCLK_VIP>,
668 <&cru HCLK_VOP0>,
669 <&cru HCLK_VOP1>,
670 <&cru PCLK_EDP_CTRL>,
671 <&cru PCLK_HDMI_CTRL>,
672 <&cru PCLK_LVDS_PHY>,
673 <&cru PCLK_MIPI_CSI>,
674 <&cru PCLK_MIPI_DSI0>,
675 <&cru PCLK_MIPI_DSI1>,
676 <&cru SCLK_EDP_24M>,
677 <&cru SCLK_EDP>,
678 <&cru SCLK_ISP_JPE>,
679 <&cru SCLK_ISP>,
680 <&cru SCLK_RGA>;
681 };
682
683 /*
684 * Note: The following 3 are HEVC(H.265) clocks,
685 * and on the ACLK_HEVC_NIU (NOC).
686 */
687 pd_hevc {
688 reg = <RK3288_PD_HEVC>;
689 clocks = <&cru ACLK_HEVC>,
690 <&cru SCLK_HEVC_CABAC>,
691 <&cru SCLK_HEVC_CORE>;
692 };
693
694 /*
695 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
696 * (video endecoder & decoder) clocks that on the
697 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
698 */
699 pd_video {
700 reg = <RK3288_PD_VIDEO>;
701 clocks = <&cru ACLK_VCODEC>,
702 <&cru HCLK_VCODEC>;
703 };
704
705 /*
706 * Note: ACLK_GPU is the GPU clock,
707 * and on the ACLK_GPU_NIU (NOC).
708 */
709 pd_gpu {
710 reg = <RK3288_PD_GPU>;
711 clocks = <&cru ACLK_GPU>;
712 };
713 };
714 };
715
716 sgrf: syscon@ff740000 {
717 compatible = "rockchip,rk3288-sgrf", "syscon";
718 reg = <0xff740000 0x1000>;
719 };
720
721 cru: clock-controller@ff760000 {
722 compatible = "rockchip,rk3288-cru";
723 reg = <0xff760000 0x1000>;
724 rockchip,grf = <&grf>;
725 #clock-cells = <1>;
726 #reset-cells = <1>;
727 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
728 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
729 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
730 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
731 <&cru PCLK_PERI>;
732 assigned-clock-rates = <594000000>, <400000000>,
733 <500000000>, <300000000>,
734 <150000000>, <75000000>,
735 <300000000>, <150000000>,
736 <75000000>;
737 };
738
739 grf: syscon@ff770000 {
740 compatible = "rockchip,rk3288-grf", "syscon";
741 reg = <0xff770000 0x1000>;
742 };
743
744 wdt: watchdog@ff800000 {
745 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
746 reg = <0xff800000 0x100>;
747 clocks = <&cru PCLK_WDT>;
748 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
749 status = "disabled";
750 };
751
752 spdif: sound@ff88b0000 {
753 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
754 reg = <0xff8b0000 0x10000>;
755 #sound-dai-cells = <0>;
756 clock-names = "hclk", "mclk";
757 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
758 dmas = <&dmac_bus_s 3>;
759 dma-names = "tx";
760 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
761 pinctrl-names = "default";
762 pinctrl-0 = <&spdif_tx>;
763 rockchip,grf = <&grf>;
764 status = "disabled";
765 };
766
767 i2s: i2s@ff890000 {
768 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
769 reg = <0xff890000 0x10000>;
770 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
771 #address-cells = <1>;
772 #size-cells = <0>;
773 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
774 dma-names = "tx", "rx";
775 clock-names = "i2s_hclk", "i2s_clk";
776 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
777 pinctrl-names = "default";
778 pinctrl-0 = <&i2s0_bus>;
779 rockchip,playback-channels = <8>;
780 rockchip,capture-channels = <2>;
781 status = "disabled";
782 };
783
784 crypto: cypto-controller@ff8a0000 {
785 compatible = "rockchip,rk3288-crypto";
786 reg = <0xff8a0000 0x4000>;
787 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
789 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
790 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
791 resets = <&cru SRST_CRYPTO>;
792 reset-names = "crypto-rst";
793 status = "okay";
794 };
795
796 vopb: vop@ff930000 {
797 compatible = "rockchip,rk3288-vop";
798 reg = <0xff930000 0x19c>;
799 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
801 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
802 power-domains = <&power RK3288_PD_VIO>;
803 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
804 reset-names = "axi", "ahb", "dclk";
805 iommus = <&vopb_mmu>;
806 status = "disabled";
807
808 vopb_out: port {
809 #address-cells = <1>;
810 #size-cells = <0>;
811
812 vopb_out_hdmi: endpoint@0 {
813 reg = <0>;
814 remote-endpoint = <&hdmi_in_vopb>;
815 };
816 };
817 };
818
819 vopb_mmu: iommu@ff930300 {
820 compatible = "rockchip,iommu";
821 reg = <0xff930300 0x100>;
822 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
823 interrupt-names = "vopb_mmu";
824 power-domains = <&power RK3288_PD_VIO>;
825 #iommu-cells = <0>;
826 status = "disabled";
827 };
828
829 vopl: vop@ff940000 {
830 compatible = "rockchip,rk3288-vop";
831 reg = <0xff940000 0x19c>;
832 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
834 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
835 power-domains = <&power RK3288_PD_VIO>;
836 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
837 reset-names = "axi", "ahb", "dclk";
838 iommus = <&vopl_mmu>;
839 status = "disabled";
840
841 vopl_out: port {
842 #address-cells = <1>;
843 #size-cells = <0>;
844
845 vopl_out_hdmi: endpoint@0 {
846 reg = <0>;
847 remote-endpoint = <&hdmi_in_vopl>;
848 };
849 };
850 };
851
852 vopl_mmu: iommu@ff940300 {
853 compatible = "rockchip,iommu";
854 reg = <0xff940300 0x100>;
855 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
856 interrupt-names = "vopl_mmu";
857 power-domains = <&power RK3288_PD_VIO>;
858 #iommu-cells = <0>;
859 status = "disabled";
860 };
861
862 hdmi: hdmi@ff980000 {
863 compatible = "rockchip,rk3288-dw-hdmi";
864 reg = <0xff980000 0x20000>;
865 reg-io-width = <4>;
866 rockchip,grf = <&grf>;
867 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
869 clock-names = "iahb", "isfr";
870 power-domains = <&power RK3288_PD_VIO>;
871 status = "disabled";
872
873 ports {
874 hdmi_in: port {
875 #address-cells = <1>;
876 #size-cells = <0>;
877 hdmi_in_vopb: endpoint@0 {
878 reg = <0>;
879 remote-endpoint = <&vopb_out_hdmi>;
880 };
881 hdmi_in_vopl: endpoint@1 {
882 reg = <1>;
883 remote-endpoint = <&vopl_out_hdmi>;
884 };
885 };
886 };
887 };
888
889 gic: interrupt-controller@ffc01000 {
890 compatible = "arm,gic-400";
891 interrupt-controller;
892 #interrupt-cells = <3>;
893 #address-cells = <0>;
894
895 reg = <0xffc01000 0x1000>,
896 <0xffc02000 0x1000>,
897 <0xffc04000 0x2000>,
898 <0xffc06000 0x2000>;
899 interrupts = <GIC_PPI 9 0xf04>;
900 };
901
902 efuse: efuse@ffb40000 {
903 compatible = "rockchip,rockchip-efuse";
904 reg = <0xffb40000 0x20>;
905 #address-cells = <1>;
906 #size-cells = <1>;
907 clocks = <&cru PCLK_EFUSE256>;
908 clock-names = "pclk_efuse";
909
910 cpu_leakage: cpu_leakage@17 {
911 reg = <0x17 0x1>;
912 };
913 };
914
915 usbphy: phy {
916 compatible = "rockchip,rk3288-usb-phy";
917 rockchip,grf = <&grf>;
918 #address-cells = <1>;
919 #size-cells = <0>;
920 status = "disabled";
921
922 usbphy0: usb-phy0 {
923 #phy-cells = <0>;
924 reg = <0x320>;
925 clocks = <&cru SCLK_OTGPHY0>;
926 clock-names = "phyclk";
927 };
928
929 usbphy1: usb-phy1 {
930 #phy-cells = <0>;
931 reg = <0x334>;
932 clocks = <&cru SCLK_OTGPHY1>;
933 clock-names = "phyclk";
934 };
935
936 usbphy2: usb-phy2 {
937 #phy-cells = <0>;
938 reg = <0x348>;
939 clocks = <&cru SCLK_OTGPHY2>;
940 clock-names = "phyclk";
941 };
942 };
943
944 pinctrl: pinctrl {
945 compatible = "rockchip,rk3288-pinctrl";
946 rockchip,grf = <&grf>;
947 rockchip,pmu = <&pmu>;
948 #address-cells = <1>;
949 #size-cells = <1>;
950 ranges;
951
952 gpio0: gpio0@ff750000 {
953 compatible = "rockchip,gpio-bank";
954 reg = <0xff750000 0x100>;
955 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&cru PCLK_GPIO0>;
957
958 gpio-controller;
959 #gpio-cells = <2>;
960
961 interrupt-controller;
962 #interrupt-cells = <2>;
963 };
964
965 gpio1: gpio1@ff780000 {
966 compatible = "rockchip,gpio-bank";
967 reg = <0xff780000 0x100>;
968 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&cru PCLK_GPIO1>;
970
971 gpio-controller;
972 #gpio-cells = <2>;
973
974 interrupt-controller;
975 #interrupt-cells = <2>;
976 };
977
978 gpio2: gpio2@ff790000 {
979 compatible = "rockchip,gpio-bank";
980 reg = <0xff790000 0x100>;
981 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&cru PCLK_GPIO2>;
983
984 gpio-controller;
985 #gpio-cells = <2>;
986
987 interrupt-controller;
988 #interrupt-cells = <2>;
989 };
990
991 gpio3: gpio3@ff7a0000 {
992 compatible = "rockchip,gpio-bank";
993 reg = <0xff7a0000 0x100>;
994 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&cru PCLK_GPIO3>;
996
997 gpio-controller;
998 #gpio-cells = <2>;
999
1000 interrupt-controller;
1001 #interrupt-cells = <2>;
1002 };
1003
1004 gpio4: gpio4@ff7b0000 {
1005 compatible = "rockchip,gpio-bank";
1006 reg = <0xff7b0000 0x100>;
1007 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&cru PCLK_GPIO4>;
1009
1010 gpio-controller;
1011 #gpio-cells = <2>;
1012
1013 interrupt-controller;
1014 #interrupt-cells = <2>;
1015 };
1016
1017 gpio5: gpio5@ff7c0000 {
1018 compatible = "rockchip,gpio-bank";
1019 reg = <0xff7c0000 0x100>;
1020 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&cru PCLK_GPIO5>;
1022
1023 gpio-controller;
1024 #gpio-cells = <2>;
1025
1026 interrupt-controller;
1027 #interrupt-cells = <2>;
1028 };
1029
1030 gpio6: gpio6@ff7d0000 {
1031 compatible = "rockchip,gpio-bank";
1032 reg = <0xff7d0000 0x100>;
1033 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1034 clocks = <&cru PCLK_GPIO6>;
1035
1036 gpio-controller;
1037 #gpio-cells = <2>;
1038
1039 interrupt-controller;
1040 #interrupt-cells = <2>;
1041 };
1042
1043 gpio7: gpio7@ff7e0000 {
1044 compatible = "rockchip,gpio-bank";
1045 reg = <0xff7e0000 0x100>;
1046 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&cru PCLK_GPIO7>;
1048
1049 gpio-controller;
1050 #gpio-cells = <2>;
1051
1052 interrupt-controller;
1053 #interrupt-cells = <2>;
1054 };
1055
1056 gpio8: gpio8@ff7f0000 {
1057 compatible = "rockchip,gpio-bank";
1058 reg = <0xff7f0000 0x100>;
1059 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&cru PCLK_GPIO8>;
1061
1062 gpio-controller;
1063 #gpio-cells = <2>;
1064
1065 interrupt-controller;
1066 #interrupt-cells = <2>;
1067 };
1068
1069 hdmi {
1070 hdmi_ddc: hdmi-ddc {
1071 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1072 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1073 };
1074 };
1075
1076 pcfg_pull_up: pcfg-pull-up {
1077 bias-pull-up;
1078 };
1079
1080 pcfg_pull_down: pcfg-pull-down {
1081 bias-pull-down;
1082 };
1083
1084 pcfg_pull_none: pcfg-pull-none {
1085 bias-disable;
1086 };
1087
1088 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1089 bias-disable;
1090 drive-strength = <12>;
1091 };
1092
1093 sleep {
1094 global_pwroff: global-pwroff {
1095 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1096 };
1097
1098 ddrio_pwroff: ddrio-pwroff {
1099 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1100 };
1101
1102 ddr0_retention: ddr0-retention {
1103 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1104 };
1105
1106 ddr1_retention: ddr1-retention {
1107 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1108 };
1109 };
1110
1111 i2c0 {
1112 i2c0_xfer: i2c0-xfer {
1113 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1114 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1115 };
1116 };
1117
1118 i2c1 {
1119 i2c1_xfer: i2c1-xfer {
1120 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1121 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1122 };
1123 };
1124
1125 i2c2 {
1126 i2c2_xfer: i2c2-xfer {
1127 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1128 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1129 };
1130 };
1131
1132 i2c3 {
1133 i2c3_xfer: i2c3-xfer {
1134 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1135 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1136 };
1137 };
1138
1139 i2c4 {
1140 i2c4_xfer: i2c4-xfer {
1141 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1142 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1143 };
1144 };
1145
1146 i2c5 {
1147 i2c5_xfer: i2c5-xfer {
1148 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1149 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1150 };
1151 };
1152
1153 i2s0 {
1154 i2s0_bus: i2s0-bus {
1155 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1156 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1157 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1158 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1159 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1160 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1161 };
1162 };
1163
1164 sdmmc {
1165 sdmmc_clk: sdmmc-clk {
1166 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1167 };
1168
1169 sdmmc_cmd: sdmmc-cmd {
1170 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1171 };
1172
1173 sdmmc_cd: sdmmc-cd {
1174 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1175 };
1176
1177 sdmmc_bus1: sdmmc-bus1 {
1178 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1179 };
1180
1181 sdmmc_bus4: sdmmc-bus4 {
1182 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1183 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1184 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1185 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1186 };
1187 };
1188
1189 sdio0 {
1190 sdio0_bus1: sdio0-bus1 {
1191 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1192 };
1193
1194 sdio0_bus4: sdio0-bus4 {
1195 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1196 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1197 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1198 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1199 };
1200
1201 sdio0_cmd: sdio0-cmd {
1202 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1203 };
1204
1205 sdio0_clk: sdio0-clk {
1206 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1207 };
1208
1209 sdio0_cd: sdio0-cd {
1210 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1211 };
1212
1213 sdio0_wp: sdio0-wp {
1214 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1215 };
1216
1217 sdio0_pwr: sdio0-pwr {
1218 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1219 };
1220
1221 sdio0_bkpwr: sdio0-bkpwr {
1222 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1223 };
1224
1225 sdio0_int: sdio0-int {
1226 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1227 };
1228 };
1229
1230 sdio1 {
1231 sdio1_bus1: sdio1-bus1 {
1232 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1233 };
1234
1235 sdio1_bus4: sdio1-bus4 {
1236 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1237 <3 25 4 &pcfg_pull_up>,
1238 <3 26 4 &pcfg_pull_up>,
1239 <3 27 4 &pcfg_pull_up>;
1240 };
1241
1242 sdio1_cd: sdio1-cd {
1243 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1244 };
1245
1246 sdio1_wp: sdio1-wp {
1247 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1248 };
1249
1250 sdio1_bkpwr: sdio1-bkpwr {
1251 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1252 };
1253
1254 sdio1_int: sdio1-int {
1255 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1256 };
1257
1258 sdio1_cmd: sdio1-cmd {
1259 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1260 };
1261
1262 sdio1_clk: sdio1-clk {
1263 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1264 };
1265
1266 sdio1_pwr: sdio1-pwr {
1267 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1268 };
1269 };
1270
1271 emmc {
1272 emmc_clk: emmc-clk {
1273 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1274 };
1275
1276 emmc_cmd: emmc-cmd {
1277 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1278 };
1279
1280 emmc_pwr: emmc-pwr {
1281 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1282 };
1283
1284 emmc_bus1: emmc-bus1 {
1285 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1286 };
1287
1288 emmc_bus4: emmc-bus4 {
1289 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1290 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1291 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1292 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1293 };
1294
1295 emmc_bus8: emmc-bus8 {
1296 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1297 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1298 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1299 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1300 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1301 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1302 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1303 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1304 };
1305 };
1306
1307 spi0 {
1308 spi0_clk: spi0-clk {
1309 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1310 };
1311 spi0_cs0: spi0-cs0 {
1312 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1313 };
1314 spi0_tx: spi0-tx {
1315 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1316 };
1317 spi0_rx: spi0-rx {
1318 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1319 };
1320 spi0_cs1: spi0-cs1 {
1321 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1322 };
1323 };
1324 spi1 {
1325 spi1_clk: spi1-clk {
1326 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1327 };
1328 spi1_cs0: spi1-cs0 {
1329 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1330 };
1331 spi1_rx: spi1-rx {
1332 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1333 };
1334 spi1_tx: spi1-tx {
1335 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1336 };
1337 };
1338
1339 spi2 {
1340 spi2_cs1: spi2-cs1 {
1341 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1342 };
1343 spi2_clk: spi2-clk {
1344 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1345 };
1346 spi2_cs0: spi2-cs0 {
1347 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1348 };
1349 spi2_rx: spi2-rx {
1350 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1351 };
1352 spi2_tx: spi2-tx {
1353 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1354 };
1355 };
1356
1357 uart0 {
1358 uart0_xfer: uart0-xfer {
1359 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1360 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1361 };
1362
1363 uart0_cts: uart0-cts {
1364 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1365 };
1366
1367 uart0_rts: uart0-rts {
1368 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1369 };
1370 };
1371
1372 uart1 {
1373 uart1_xfer: uart1-xfer {
1374 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1375 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1376 };
1377
1378 uart1_cts: uart1-cts {
1379 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1380 };
1381
1382 uart1_rts: uart1-rts {
1383 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1384 };
1385 };
1386
1387 uart2 {
1388 uart2_xfer: uart2-xfer {
1389 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1390 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1391 };
1392 /* no rts / cts for uart2 */
1393 };
1394
1395 uart3 {
1396 uart3_xfer: uart3-xfer {
1397 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1398 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1399 };
1400
1401 uart3_cts: uart3-cts {
1402 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1403 };
1404
1405 uart3_rts: uart3-rts {
1406 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1407 };
1408 };
1409
1410 uart4 {
1411 uart4_xfer: uart4-xfer {
1412 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1413 <5 13 3 &pcfg_pull_none>;
1414 };
1415
1416 uart4_cts: uart4-cts {
1417 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1418 };
1419
1420 uart4_rts: uart4-rts {
1421 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1422 };
1423 };
1424
1425 tsadc {
1426 otp_out: otp-out {
1427 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1428 };
1429 };
1430
1431 pwm0 {
1432 pwm0_pin: pwm0-pin {
1433 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1434 };
1435 };
1436
1437 pwm1 {
1438 pwm1_pin: pwm1-pin {
1439 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1440 };
1441 };
1442
1443 pwm2 {
1444 pwm2_pin: pwm2-pin {
1445 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1446 };
1447 };
1448
1449 pwm3 {
1450 pwm3_pin: pwm3-pin {
1451 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1452 };
1453 };
1454
1455 gmac {
1456 rgmii_pins: rgmii-pins {
1457 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1458 <3 31 3 &pcfg_pull_none>,
1459 <3 26 3 &pcfg_pull_none>,
1460 <3 27 3 &pcfg_pull_none>,
1461 <3 28 3 &pcfg_pull_none_12ma>,
1462 <3 29 3 &pcfg_pull_none_12ma>,
1463 <3 24 3 &pcfg_pull_none_12ma>,
1464 <3 25 3 &pcfg_pull_none_12ma>,
1465 <4 0 3 &pcfg_pull_none>,
1466 <4 5 3 &pcfg_pull_none>,
1467 <4 6 3 &pcfg_pull_none>,
1468 <4 9 3 &pcfg_pull_none_12ma>,
1469 <4 4 3 &pcfg_pull_none_12ma>,
1470 <4 1 3 &pcfg_pull_none>,
1471 <4 3 3 &pcfg_pull_none>;
1472 };
1473
1474 rmii_pins: rmii-pins {
1475 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1476 <3 31 3 &pcfg_pull_none>,
1477 <3 28 3 &pcfg_pull_none>,
1478 <3 29 3 &pcfg_pull_none>,
1479 <4 0 3 &pcfg_pull_none>,
1480 <4 5 3 &pcfg_pull_none>,
1481 <4 4 3 &pcfg_pull_none>,
1482 <4 1 3 &pcfg_pull_none>,
1483 <4 2 3 &pcfg_pull_none>,
1484 <4 3 3 &pcfg_pull_none>;
1485 };
1486 };
1487
1488 spdif {
1489 spdif_tx: spdif-tx {
1490 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1491 };
1492 };
1493 };
1494 };
Linux kernel - Deliverables
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