arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         interrupt-parent = <&gic>;
  50
  51         aliases {
  52                 i2c0 = &i2c0;
  53                 i2c1 = &i2c1;
  54                 i2c2 = &i2c2;
  55                 i2c3 = &i2c3;
  56                 i2c4 = &i2c4;
  57                 mshc0 = &emmc;
  58                 mshc1 = &mmc0;
  59                 mshc2 = &mmc1;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 serial3 = &uart3;
  64                 spi0 = &spi0;
  65                 spi1 = &spi1;
  66         };
  67
  68         amba {
  69                 compatible = "arm,amba-bus";
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72                 ranges;
  73
  74                 dmac1_s: dma-controller@20018000 {
  75                         compatible = "arm,pl330", "arm,primecell";
  76                         reg = <0x20018000 0x4000>;
  77                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  78                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  79                         #dma-cells = <1>;
  80                         clocks = <&cru ACLK_DMA1>;
  81                         clock-names = "apb_pclk";
  82                 };
  83
  84                 dmac1_ns: dma-controller@2001c000 {
  85                         compatible = "arm,pl330", "arm,primecell";
  86                         reg = <0x2001c000 0x4000>;
  87                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  88                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  89                         #dma-cells = <1>;
  90                         clocks = <&cru ACLK_DMA1>;
  91                         clock-names = "apb_pclk";
  92                         status = "disabled";
  93                 };
  94
  95                 dmac2: dma-controller@20078000 {
  96                         compatible = "arm,pl330", "arm,primecell";
  97                         reg = <0x20078000 0x4000>;
  98                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  99                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 100                         #dma-cells = <1>;
 101                         clocks = <&cru ACLK_DMA2>;
 102                         clock-names = "apb_pclk";
 103                 };
 104         };
 105
 106         xin24m: oscillator {
 107                 compatible = "fixed-clock";
 108                 clock-frequency = <24000000>;
 109                 #clock-cells = <0>;
 110                 clock-output-names = "xin24m";
 111         };
 112
 113         L2: l2-cache-controller@10138000 {
 114                 compatible = "arm,pl310-cache";
 115                 reg = <0x10138000 0x1000>;
 116                 cache-unified;
 117                 cache-level = <2>;
 118         };
 119
 120         scu@1013c000 {
 121                 compatible = "arm,cortex-a9-scu";
 122                 reg = <0x1013c000 0x100>;
 123         };
 124
 125         global_timer: global-timer@1013c200 {
 126                 compatible = "arm,cortex-a9-global-timer";
 127                 reg = <0x1013c200 0x20>;
 128                 interrupts = <GIC_PPI 11 0x304>;
 129                 clocks = <&cru CORE_PERI>;
 130         };
 131
 132         local_timer: local-timer@1013c600 {
 133                 compatible = "arm,cortex-a9-twd-timer";
 134                 reg = <0x1013c600 0x20>;
 135                 interrupts = <GIC_PPI 13 0x304>;
 136                 clocks = <&cru CORE_PERI>;
 137         };
 138
 139         gic: interrupt-controller@1013d000 {
 140                 compatible = "arm,cortex-a9-gic";
 141                 interrupt-controller;
 142                 #interrupt-cells = <3>;
 143                 reg = <0x1013d000 0x1000>,
 144                       <0x1013c100 0x0100>;
 145         };
 146
 147         uart0: serial@10124000 {
 148                 compatible = "snps,dw-apb-uart";
 149                 reg = <0x10124000 0x400>;
 150                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 151                 reg-shift = <2>;
 152                 reg-io-width = <1>;
 153                 clock-names = "baudclk", "apb_pclk";
 154                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 155                 status = "disabled";
 156         };
 157
 158         uart1: serial@10126000 {
 159                 compatible = "snps,dw-apb-uart";
 160                 reg = <0x10126000 0x400>;
 161                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 162                 reg-shift = <2>;
 163                 reg-io-width = <1>;
 164                 clock-names = "baudclk", "apb_pclk";
 165                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 166                 status = "disabled";
 167         };
 168
 169         usb_otg: usb@10180000 {
 170                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 171                 reg = <0x10180000 0x40000>;
 172                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 173                 clocks = <&cru HCLK_OTG0>;
 174                 clock-names = "otg";
 175                 dr_mode = "otg";
 176                 g-np-tx-fifo-size = <16>;
 177                 g-rx-fifo-size = <275>;
 178                 g-tx-fifo-size = <256 128 128 64 64 32>;
 179                 g-use-dma;
 180                 status = "disabled";
 181         };
 182
 183         usb_host: usb@101c0000 {
 184                 compatible = "snps,dwc2";
 185                 reg = <0x101c0000 0x40000>;
 186                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 187                 clocks = <&cru HCLK_OTG1>;
 188                 clock-names = "otg";
 189                 dr_mode = "host";
 190                 status = "disabled";
 191         };
 192
 193         emac: ethernet@10204000 {
 194                 compatible = "snps,arc-emac";
 195                 reg = <0x10204000 0x3c>;
 196                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199
 200                 rockchip,grf = <&grf>;
 201
 202                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 203                 clock-names = "hclk", "macref";
 204                 max-speed = <100>;
 205                 phy-mode = "rmii";
 206
 207                 status = "disabled";
 208         };
 209
 210         mmc0: dwmmc@10214000 {
 211                 compatible = "rockchip,rk2928-dw-mshc";
 212                 reg = <0x10214000 0x1000>;
 213                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 215                 clock-names = "biu", "ciu";
 216                 fifo-depth = <256>;
 217                 status = "disabled";
 218         };
 219
 220         mmc1: dwmmc@10218000 {
 221                 compatible = "rockchip,rk2928-dw-mshc";
 222                 reg = <0x10218000 0x1000>;
 223                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 224                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 225                 clock-names = "biu", "ciu";
 226                 fifo-depth = <256>;
 227                 status = "disabled";
 228         };
 229
 230         emmc: dwmmc@1021c000 {
 231                 compatible = "rockchip,rk2928-dw-mshc";
 232                 reg = <0x1021c000 0x1000>;
 233                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 235                 clock-names = "biu", "ciu";
 236                 fifo-depth = <256>;
 237                 status = "disabled";
 238         };
 239
 240         pmu: pmu@20004000 {
 241                 compatible = "rockchip,rk3066-pmu", "syscon";
 242                 reg = <0x20004000 0x100>;
 243         };
 244
 245         grf: grf@20008000 {
 246                 compatible = "syscon";
 247                 reg = <0x20008000 0x200>;
 248         };
 249
 250         i2c0: i2c@2002d000 {
 251                 compatible = "rockchip,rk3066-i2c";
 252                 reg = <0x2002d000 0x1000>;
 253                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256
 257                 rockchip,grf = <&grf>;
 258
 259                 clock-names = "i2c";
 260                 clocks = <&cru PCLK_I2C0>;
 261
 262                 status = "disabled";
 263         };
 264
 265         i2c1: i2c@2002f000 {
 266                 compatible = "rockchip,rk3066-i2c";
 267                 reg = <0x2002f000 0x1000>;
 268                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271
 272                 rockchip,grf = <&grf>;
 273
 274                 clocks = <&cru PCLK_I2C1>;
 275                 clock-names = "i2c";
 276
 277                 status = "disabled";
 278         };
 279
 280         pwm0: pwm@20030000 {
 281                 compatible = "rockchip,rk2928-pwm";
 282                 reg = <0x20030000 0x10>;
 283                 #pwm-cells = <2>;
 284                 clocks = <&cru PCLK_PWM01>;
 285                 status = "disabled";
 286         };
 287
 288         pwm1: pwm@20030010 {
 289                 compatible = "rockchip,rk2928-pwm";
 290                 reg = <0x20030010 0x10>;
 291                 #pwm-cells = <2>;
 292                 clocks = <&cru PCLK_PWM01>;
 293                 status = "disabled";
 294         };
 295
 296         wdt: watchdog@2004c000 {
 297                 compatible = "snps,dw-wdt";
 298                 reg = <0x2004c000 0x100>;
 299                 clocks = <&cru PCLK_WDT>;
 300                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 301                 status = "disabled";
 302         };
 303
 304         pwm2: pwm@20050020 {
 305                 compatible = "rockchip,rk2928-pwm";
 306                 reg = <0x20050020 0x10>;
 307                 #pwm-cells = <2>;
 308                 clocks = <&cru PCLK_PWM23>;
 309                 status = "disabled";
 310         };
 311
 312         pwm3: pwm@20050030 {
 313                 compatible = "rockchip,rk2928-pwm";
 314                 reg = <0x20050030 0x10>;
 315                 #pwm-cells = <2>;
 316                 clocks = <&cru PCLK_PWM23>;
 317                 status = "disabled";
 318         };
 319
 320         i2c2: i2c@20056000 {
 321                 compatible = "rockchip,rk3066-i2c";
 322                 reg = <0x20056000 0x1000>;
 323                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326
 327                 rockchip,grf = <&grf>;
 328
 329                 clocks = <&cru PCLK_I2C2>;
 330                 clock-names = "i2c";
 331
 332                 status = "disabled";
 333         };
 334
 335         i2c3: i2c@2005a000 {
 336                 compatible = "rockchip,rk3066-i2c";
 337                 reg = <0x2005a000 0x1000>;
 338                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341
 342                 rockchip,grf = <&grf>;
 343
 344                 clocks = <&cru PCLK_I2C3>;
 345                 clock-names = "i2c";
 346
 347                 status = "disabled";
 348         };
 349
 350         i2c4: i2c@2005e000 {
 351                 compatible = "rockchip,rk3066-i2c";
 352                 reg = <0x2005e000 0x1000>;
 353                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356
 357                 rockchip,grf = <&grf>;
 358
 359                 clocks = <&cru PCLK_I2C4>;
 360                 clock-names = "i2c";
 361
 362                 status = "disabled";
 363         };
 364
 365         uart2: serial@20064000 {
 366                 compatible = "snps,dw-apb-uart";
 367                 reg = <0x20064000 0x400>;
 368                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 369                 reg-shift = <2>;
 370                 reg-io-width = <1>;
 371                 clock-names = "baudclk", "apb_pclk";
 372                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 373                 status = "disabled";
 374         };
 375
 376         uart3: serial@20068000 {
 377                 compatible = "snps,dw-apb-uart";
 378                 reg = <0x20068000 0x400>;
 379                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 380                 reg-shift = <2>;
 381                 reg-io-width = <1>;
 382                 clock-names = "baudclk", "apb_pclk";
 383                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 384                 status = "disabled";
 385         };
 386
 387         saradc: saradc@2006c000 {
 388                 compatible = "rockchip,saradc";
 389                 reg = <0x2006c000 0x100>;
 390                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 391                 #io-channel-cells = <1>;
 392                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 393                 clock-names = "saradc", "apb_pclk";
 394                 status = "disabled";
 395         };
 396
 397         spi0: spi@20070000 {
 398                 compatible = "rockchip,rk3066-spi";
 399                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 400                 clock-names = "spiclk", "apb_pclk";
 401                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 402                 reg = <0x20070000 0x1000>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 dmas = <&dmac2 10>, <&dmac2 11>;
 406                 dma-names = "tx", "rx";
 407                 status = "disabled";
 408         };
 409
 410         spi1: spi@20074000 {
 411                 compatible = "rockchip,rk3066-spi";
 412                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 413                 clock-names = "spiclk", "apb_pclk";
 414                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 415                 reg = <0x20074000 0x1000>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 dmas = <&dmac2 12>, <&dmac2 13>;
 419                 dma-names = "tx", "rx";
 420                 status = "disabled";
 421         };
 422 };