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Merge tag 'for-linus-4.6-rc0-tag' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / boot / dts / sama5d2.dtsi
1 /*
2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46 #include "skeleton.dtsi"
47 #include <dt-bindings/dma/at91.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/clock/at91.h>
50
51 / {
52 model = "Atmel SAMA5D2 family SoC";
53 compatible = "atmel,sama5d2";
54 interrupt-parent = <&aic>;
55
56 aliases {
57 serial0 = &uart1;
58 serial1 = &uart3;
59 tcb0 = &tcb0;
60 tcb1 = &tcb1;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu@0 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a5";
70 reg = <0>;
71 next-level-cache = <&L2>;
72 };
73 };
74
75 memory {
76 reg = <0x20000000 0x20000000>;
77 };
78
79 clocks {
80 slow_xtal: slow_xtal {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <0>;
84 };
85
86 main_xtal: main_xtal {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <0>;
90 };
91 };
92
93 ns_sram: sram@00200000 {
94 compatible = "mmio-sram";
95 reg = <0x00200000 0x20000>;
96 };
97
98 ahb {
99 compatible = "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103
104 usb0: gadget@00300000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 compatible = "atmel,sama5d3-udc";
108 reg = <0x00300000 0x100000
109 0xfc02c000 0x400>;
110 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
111 clocks = <&udphs_clk>, <&utmi>;
112 clock-names = "pclk", "hclk";
113 status = "disabled";
114
115 ep0 {
116 reg = <0>;
117 atmel,fifo-size = <64>;
118 atmel,nb-banks = <1>;
119 };
120
121 ep1 {
122 reg = <1>;
123 atmel,fifo-size = <1024>;
124 atmel,nb-banks = <3>;
125 atmel,can-dma;
126 atmel,can-isoc;
127 };
128
129 ep2 {
130 reg = <2>;
131 atmel,fifo-size = <1024>;
132 atmel,nb-banks = <3>;
133 atmel,can-dma;
134 atmel,can-isoc;
135 };
136
137 ep3 {
138 reg = <3>;
139 atmel,fifo-size = <1024>;
140 atmel,nb-banks = <2>;
141 atmel,can-dma;
142 atmel,can-isoc;
143 };
144
145 ep4 {
146 reg = <4>;
147 atmel,fifo-size = <1024>;
148 atmel,nb-banks = <2>;
149 atmel,can-dma;
150 atmel,can-isoc;
151 };
152
153 ep5 {
154 reg = <5>;
155 atmel,fifo-size = <1024>;
156 atmel,nb-banks = <2>;
157 atmel,can-dma;
158 atmel,can-isoc;
159 };
160
161 ep6 {
162 reg = <6>;
163 atmel,fifo-size = <1024>;
164 atmel,nb-banks = <2>;
165 atmel,can-dma;
166 atmel,can-isoc;
167 };
168
169 ep7 {
170 reg = <7>;
171 atmel,fifo-size = <1024>;
172 atmel,nb-banks = <2>;
173 atmel,can-dma;
174 atmel,can-isoc;
175 };
176
177 ep8 {
178 reg = <8>;
179 atmel,fifo-size = <1024>;
180 atmel,nb-banks = <2>;
181 atmel,can-isoc;
182 };
183
184 ep9 {
185 reg = <9>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
188 atmel,can-isoc;
189 };
190
191 ep10 {
192 reg = <10>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
195 atmel,can-isoc;
196 };
197
198 ep11 {
199 reg = <11>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
202 atmel,can-isoc;
203 };
204
205 ep12 {
206 reg = <12>;
207 atmel,fifo-size = <1024>;
208 atmel,nb-banks = <2>;
209 atmel,can-isoc;
210 };
211
212 ep13 {
213 reg = <13>;
214 atmel,fifo-size = <1024>;
215 atmel,nb-banks = <2>;
216 atmel,can-isoc;
217 };
218
219 ep14 {
220 reg = <14>;
221 atmel,fifo-size = <1024>;
222 atmel,nb-banks = <2>;
223 atmel,can-isoc;
224 };
225
226 ep15 {
227 reg = <15>;
228 atmel,fifo-size = <1024>;
229 atmel,nb-banks = <2>;
230 atmel,can-isoc;
231 };
232 };
233
234 usb1: ohci@00400000 {
235 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
236 reg = <0x00400000 0x100000>;
237 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
238 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
239 clock-names = "ohci_clk", "hclk", "uhpck";
240 status = "disabled";
241 };
242
243 usb2: ehci@00500000 {
244 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
245 reg = <0x00500000 0x100000>;
246 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
247 clocks = <&utmi>, <&uhphs_clk>;
248 clock-names = "usb_clk", "ehci_clk";
249 status = "disabled";
250 };
251
252 L2: cache-controller@00a00000 {
253 compatible = "arm,pl310-cache";
254 reg = <0x00a00000 0x1000>;
255 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
256 cache-unified;
257 cache-level = <2>;
258 };
259
260 nand0: nand@80000000 {
261 compatible = "atmel,sama5d2-nand";
262 #address-cells = <1>;
263 #size-cells = <1>;
264 ranges;
265 reg = < /* EBI CS3 */
266 0x80000000 0x08000000
267 /* SMC PMECC regs */
268 0xf8014070 0x00000490
269 /* SMC PMECC Error Location regs */
270 0xf8014500 0x00000200
271 /* ROM Galois tables */
272 0x00040000 0x00018000
273 >;
274 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
275 atmel,nand-addr-offset = <21>;
276 atmel,nand-cmd-offset = <22>;
277 atmel,nand-has-dma;
278 atmel,has-pmecc;
279 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
280 status = "disabled";
281
282 nfc@c0000000 {
283 compatible = "atmel,sama5d4-nfc";
284 #address-cells = <1>;
285 #size-cells = <1>;
286 reg = < /* NFC Command Registers */
287 0xc0000000 0x08000000
288 /* NFC HSMC regs */
289 0xf8014000 0x00000070
290 /* NFC SRAM banks */
291 0x00100000 0x00100000
292 >;
293 clocks = <&hsmc_clk>;
294 atmel,write-by-sram;
295 };
296 };
297
298 sdmmc0: sdio-host@a0000000 {
299 compatible = "atmel,sama5d2-sdhci";
300 reg = <0xa0000000 0x300>;
301 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
302 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
303 clock-names = "hclock", "multclk", "baseclk";
304 status = "disabled";
305 };
306
307 sdmmc1: sdio-host@b0000000 {
308 compatible = "atmel,sama5d2-sdhci";
309 reg = <0xb0000000 0x300>;
310 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
311 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
312 clock-names = "hclock", "multclk", "baseclk";
313 status = "disabled";
314 };
315
316 apb {
317 compatible = "simple-bus";
318 #address-cells = <1>;
319 #size-cells = <1>;
320 ranges;
321
322 ramc0: ramc@f000c000 {
323 compatible = "atmel,sama5d3-ddramc";
324 reg = <0xf000c000 0x200>;
325 clocks = <&ddrck>, <&mpddr_clk>;
326 clock-names = "ddrck", "mpddr";
327 };
328
329 dma0: dma-controller@f0010000 {
330 compatible = "atmel,sama5d4-dma";
331 reg = <0xf0010000 0x1000>;
332 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
333 #dma-cells = <1>;
334 clocks = <&dma0_clk>;
335 clock-names = "dma_clk";
336 };
337
338 pmc: pmc@f0014000 {
339 compatible = "atmel,sama5d2-pmc", "syscon";
340 reg = <0xf0014000 0x160>;
341 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
342 interrupt-controller;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 #interrupt-cells = <1>;
346
347 main_rc_osc: main_rc_osc {
348 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
349 #clock-cells = <0>;
350 interrupt-parent = <&pmc>;
351 interrupts = <AT91_PMC_MOSCRCS>;
352 clock-frequency = <12000000>;
353 clock-accuracy = <100000000>;
354 };
355
356 main_osc: main_osc {
357 compatible = "atmel,at91rm9200-clk-main-osc";
358 #clock-cells = <0>;
359 interrupt-parent = <&pmc>;
360 interrupts = <AT91_PMC_MOSCS>;
361 clocks = <&main_xtal>;
362 };
363
364 main: mainck {
365 compatible = "atmel,at91sam9x5-clk-main";
366 #clock-cells = <0>;
367 interrupt-parent = <&pmc>;
368 interrupts = <AT91_PMC_MOSCSELS>;
369 clocks = <&main_rc_osc &main_osc>;
370 };
371
372 plla: pllack {
373 compatible = "atmel,sama5d3-clk-pll";
374 #clock-cells = <0>;
375 interrupt-parent = <&pmc>;
376 interrupts = <AT91_PMC_LOCKA>;
377 clocks = <&main>;
378 reg = <0>;
379 atmel,clk-input-range = <12000000 12000000>;
380 #atmel,pll-clk-output-range-cells = <4>;
381 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
382 };
383
384 plladiv: plladivck {
385 compatible = "atmel,at91sam9x5-clk-plldiv";
386 #clock-cells = <0>;
387 clocks = <&plla>;
388 };
389
390 utmi: utmick {
391 compatible = "atmel,at91sam9x5-clk-utmi";
392 #clock-cells = <0>;
393 interrupt-parent = <&pmc>;
394 interrupts = <AT91_PMC_LOCKU>;
395 clocks = <&main>;
396 };
397
398 mck: masterck {
399 compatible = "atmel,at91sam9x5-clk-master";
400 #clock-cells = <0>;
401 interrupt-parent = <&pmc>;
402 interrupts = <AT91_PMC_MCKRDY>;
403 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
404 atmel,clk-output-range = <124000000 166000000>;
405 atmel,clk-divisors = <1 2 4 3>;
406 };
407
408 h32ck: h32mxck {
409 #clock-cells = <0>;
410 compatible = "atmel,sama5d4-clk-h32mx";
411 clocks = <&mck>;
412 };
413
414 usb: usbck {
415 compatible = "atmel,at91sam9x5-clk-usb";
416 #clock-cells = <0>;
417 clocks = <&plladiv>, <&utmi>;
418 };
419
420 prog: progck {
421 compatible = "atmel,at91sam9x5-clk-programmable";
422 #address-cells = <1>;
423 #size-cells = <0>;
424 interrupt-parent = <&pmc>;
425 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
426
427 prog0: prog0 {
428 #clock-cells = <0>;
429 reg = <0>;
430 interrupts = <AT91_PMC_PCKRDY(0)>;
431 };
432
433 prog1: prog1 {
434 #clock-cells = <0>;
435 reg = <1>;
436 interrupts = <AT91_PMC_PCKRDY(1)>;
437 };
438
439 prog2: prog2 {
440 #clock-cells = <0>;
441 reg = <2>;
442 interrupts = <AT91_PMC_PCKRDY(2)>;
443 };
444 };
445
446 systemck {
447 compatible = "atmel,at91rm9200-clk-system";
448 #address-cells = <1>;
449 #size-cells = <0>;
450
451 ddrck: ddrck {
452 #clock-cells = <0>;
453 reg = <2>;
454 clocks = <&mck>;
455 };
456
457 lcdck: lcdck {
458 #clock-cells = <0>;
459 reg = <3>;
460 clocks = <&mck>;
461 };
462
463 uhpck: uhpck {
464 #clock-cells = <0>;
465 reg = <6>;
466 clocks = <&usb>;
467 };
468
469 udpck: udpck {
470 #clock-cells = <0>;
471 reg = <7>;
472 clocks = <&usb>;
473 };
474
475 pck0: pck0 {
476 #clock-cells = <0>;
477 reg = <8>;
478 clocks = <&prog0>;
479 };
480
481 pck1: pck1 {
482 #clock-cells = <0>;
483 reg = <9>;
484 clocks = <&prog1>;
485 };
486
487 pck2: pck2 {
488 #clock-cells = <0>;
489 reg = <10>;
490 clocks = <&prog2>;
491 };
492
493 iscck: iscck {
494 #clock-cells = <0>;
495 reg = <18>;
496 clocks = <&mck>;
497 };
498 };
499
500 periph32ck {
501 compatible = "atmel,at91sam9x5-clk-peripheral";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 clocks = <&h32ck>;
505
506 macb0_clk: macb0_clk {
507 #clock-cells = <0>;
508 reg = <5>;
509 atmel,clk-output-range = <0 83000000>;
510 };
511
512 tdes_clk: tdes_clk {
513 #clock-cells = <0>;
514 reg = <11>;
515 atmel,clk-output-range = <0 83000000>;
516 };
517
518 matrix1_clk: matrix1_clk {
519 #clock-cells = <0>;
520 reg = <14>;
521 };
522
523 hsmc_clk: hsmc_clk {
524 #clock-cells = <0>;
525 reg = <17>;
526 };
527
528 pioA_clk: pioA_clk {
529 #clock-cells = <0>;
530 reg = <18>;
531 atmel,clk-output-range = <0 83000000>;
532 };
533
534 flx0_clk: flx0_clk {
535 #clock-cells = <0>;
536 reg = <19>;
537 atmel,clk-output-range = <0 83000000>;
538 };
539
540 flx1_clk: flx1_clk {
541 #clock-cells = <0>;
542 reg = <20>;
543 atmel,clk-output-range = <0 83000000>;
544 };
545
546 flx2_clk: flx2_clk {
547 #clock-cells = <0>;
548 reg = <21>;
549 atmel,clk-output-range = <0 83000000>;
550 };
551
552 flx3_clk: flx3_clk {
553 #clock-cells = <0>;
554 reg = <22>;
555 atmel,clk-output-range = <0 83000000>;
556 };
557
558 flx4_clk: flx4_clk {
559 #clock-cells = <0>;
560 reg = <23>;
561 atmel,clk-output-range = <0 83000000>;
562 };
563
564 uart0_clk: uart0_clk {
565 #clock-cells = <0>;
566 reg = <24>;
567 atmel,clk-output-range = <0 83000000>;
568 };
569
570 uart1_clk: uart1_clk {
571 #clock-cells = <0>;
572 reg = <25>;
573 atmel,clk-output-range = <0 83000000>;
574 };
575
576 uart2_clk: uart2_clk {
577 #clock-cells = <0>;
578 reg = <26>;
579 atmel,clk-output-range = <0 83000000>;
580 };
581
582 uart3_clk: uart3_clk {
583 #clock-cells = <0>;
584 reg = <27>;
585 atmel,clk-output-range = <0 83000000>;
586 };
587
588 uart4_clk: uart4_clk {
589 #clock-cells = <0>;
590 reg = <28>;
591 atmel,clk-output-range = <0 83000000>;
592 };
593
594 twi0_clk: twi0_clk {
595 reg = <29>;
596 #clock-cells = <0>;
597 atmel,clk-output-range = <0 83000000>;
598 };
599
600 twi1_clk: twi1_clk {
601 #clock-cells = <0>;
602 reg = <30>;
603 atmel,clk-output-range = <0 83000000>;
604 };
605
606 spi0_clk: spi0_clk {
607 #clock-cells = <0>;
608 reg = <33>;
609 atmel,clk-output-range = <0 83000000>;
610 };
611
612 spi1_clk: spi1_clk {
613 #clock-cells = <0>;
614 reg = <34>;
615 atmel,clk-output-range = <0 83000000>;
616 };
617
618 tcb0_clk: tcb0_clk {
619 #clock-cells = <0>;
620 reg = <35>;
621 atmel,clk-output-range = <0 83000000>;
622 };
623
624 tcb1_clk: tcb1_clk {
625 #clock-cells = <0>;
626 reg = <36>;
627 atmel,clk-output-range = <0 83000000>;
628 };
629
630 pwm_clk: pwm_clk {
631 #clock-cells = <0>;
632 reg = <38>;
633 atmel,clk-output-range = <0 83000000>;
634 };
635
636 adc_clk: adc_clk {
637 #clock-cells = <0>;
638 reg = <40>;
639 atmel,clk-output-range = <0 83000000>;
640 };
641
642 uhphs_clk: uhphs_clk {
643 #clock-cells = <0>;
644 reg = <41>;
645 atmel,clk-output-range = <0 83000000>;
646 };
647
648 udphs_clk: udphs_clk {
649 #clock-cells = <0>;
650 reg = <42>;
651 atmel,clk-output-range = <0 83000000>;
652 };
653
654 ssc0_clk: ssc0_clk {
655 #clock-cells = <0>;
656 reg = <43>;
657 atmel,clk-output-range = <0 83000000>;
658 };
659
660 ssc1_clk: ssc1_clk {
661 #clock-cells = <0>;
662 reg = <44>;
663 atmel,clk-output-range = <0 83000000>;
664 };
665
666 trng_clk: trng_clk {
667 #clock-cells = <0>;
668 reg = <47>;
669 atmel,clk-output-range = <0 83000000>;
670 };
671
672 pdmic_clk: pdmic_clk {
673 #clock-cells = <0>;
674 reg = <48>;
675 atmel,clk-output-range = <0 83000000>;
676 };
677
678 i2s0_clk: i2s0_clk {
679 #clock-cells = <0>;
680 reg = <54>;
681 atmel,clk-output-range = <0 83000000>;
682 };
683
684 i2s1_clk: i2s1_clk {
685 #clock-cells = <0>;
686 reg = <55>;
687 atmel,clk-output-range = <0 83000000>;
688 };
689
690 classd_clk: classd_clk {
691 #clock-cells = <0>;
692 reg = <59>;
693 atmel,clk-output-range = <0 83000000>;
694 };
695 };
696
697 periph64ck {
698 compatible = "atmel,at91sam9x5-clk-peripheral";
699 #address-cells = <1>;
700 #size-cells = <0>;
701 clocks = <&mck>;
702
703 dma0_clk: dma0_clk {
704 #clock-cells = <0>;
705 reg = <6>;
706 };
707
708 dma1_clk: dma1_clk {
709 #clock-cells = <0>;
710 reg = <7>;
711 };
712
713 aes_clk: aes_clk {
714 #clock-cells = <0>;
715 reg = <9>;
716 };
717
718 aesb_clk: aesb_clk {
719 #clock-cells = <0>;
720 reg = <10>;
721 };
722
723 sha_clk: sha_clk {
724 #clock-cells = <0>;
725 reg = <12>;
726 };
727
728 mpddr_clk: mpddr_clk {
729 #clock-cells = <0>;
730 reg = <13>;
731 };
732
733 matrix0_clk: matrix0_clk {
734 #clock-cells = <0>;
735 reg = <15>;
736 };
737
738 sdmmc0_hclk: sdmmc0_hclk {
739 #clock-cells = <0>;
740 reg = <31>;
741 };
742
743 sdmmc1_hclk: sdmmc1_hclk {
744 #clock-cells = <0>;
745 reg = <32>;
746 };
747
748 lcdc_clk: lcdc_clk {
749 #clock-cells = <0>;
750 reg = <45>;
751 };
752
753 isc_clk: isc_clk {
754 #clock-cells = <0>;
755 reg = <46>;
756 };
757
758 qspi0_clk: qspi0_clk {
759 #clock-cells = <0>;
760 reg = <52>;
761 };
762
763 qspi1_clk: qspi1_clk {
764 #clock-cells = <0>;
765 reg = <53>;
766 };
767 };
768
769 gck {
770 compatible = "atmel,sama5d2-clk-generated";
771 #address-cells = <1>;
772 #size-cells = <0>;
773 interrupt-parent = <&pmc>;
774 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
775
776 sdmmc0_gclk: sdmmc0_gclk {
777 #clock-cells = <0>;
778 reg = <31>;
779 };
780
781 sdmmc1_gclk: sdmmc1_gclk {
782 #clock-cells = <0>;
783 reg = <32>;
784 };
785
786 tcb0_gclk: tcb0_gclk {
787 #clock-cells = <0>;
788 reg = <35>;
789 atmel,clk-output-range = <0 83000000>;
790 };
791
792 tcb1_gclk: tcb1_gclk {
793 #clock-cells = <0>;
794 reg = <36>;
795 atmel,clk-output-range = <0 83000000>;
796 };
797
798 pwm_gclk: pwm_gclk {
799 #clock-cells = <0>;
800 reg = <38>;
801 atmel,clk-output-range = <0 83000000>;
802 };
803
804 pdmic_gclk: pdmic_gclk {
805 #clock-cells = <0>;
806 reg = <48>;
807 };
808
809 i2s0_gclk: i2s0_gclk {
810 #clock-cells = <0>;
811 reg = <54>;
812 };
813
814 i2s1_gclk: i2s1_gclk {
815 #clock-cells = <0>;
816 reg = <55>;
817 };
818 };
819 };
820
821 sha@f0028000 {
822 compatible = "atmel,at91sam9g46-sha";
823 reg = <0xf0028000 0x100>;
824 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
825 dmas = <&dma0
826 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
827 AT91_XDMAC_DT_PERID(30))>;
828 dma-names = "tx";
829 clocks = <&sha_clk>;
830 clock-names = "sha_clk";
831 status = "okay";
832 };
833
834 aes@f002c000 {
835 compatible = "atmel,at91sam9g46-aes";
836 reg = <0xf002c000 0x100>;
837 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
838 dmas = <&dma0
839 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
840 AT91_XDMAC_DT_PERID(26))>,
841 <&dma0
842 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
843 AT91_XDMAC_DT_PERID(27))>;
844 dma-names = "tx", "rx";
845 clocks = <&aes_clk>;
846 clock-names = "aes_clk";
847 status = "okay";
848 };
849
850 spi0: spi@f8000000 {
851 compatible = "atmel,at91rm9200-spi";
852 reg = <0xf8000000 0x100>;
853 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
854 dmas = <&dma0
855 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
856 AT91_XDMAC_DT_PERID(6))>,
857 <&dma0
858 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
859 AT91_XDMAC_DT_PERID(7))>;
860 dma-names = "tx", "rx";
861 clocks = <&spi0_clk>;
862 clock-names = "spi_clk";
863 atmel,fifo-size = <16>;
864 #address-cells = <1>;
865 #size-cells = <0>;
866 status = "disabled";
867 };
868
869 macb0: ethernet@f8008000 {
870 compatible = "atmel,sama5d2-gem";
871 reg = <0xf8008000 0x1000>;
872 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
873 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
874 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
875 #address-cells = <1>;
876 #size-cells = <0>;
877 clocks = <&macb0_clk>, <&macb0_clk>;
878 clock-names = "hclk", "pclk";
879 status = "disabled";
880 };
881
882 tcb0: timer@f800c000 {
883 compatible = "atmel,at91sam9x5-tcb";
884 reg = <0xf800c000 0x100>;
885 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
886 clocks = <&tcb0_clk>, <&clk32k>;
887 clock-names = "t0_clk", "slow_clk";
888 };
889
890 tcb1: timer@f8010000 {
891 compatible = "atmel,at91sam9x5-tcb";
892 reg = <0xf8010000 0x100>;
893 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
894 clocks = <&tcb1_clk>, <&clk32k>;
895 clock-names = "t0_clk", "slow_clk";
896 };
897
898 pdmic: pdmic@f8018000 {
899 compatible = "atmel,sama5d2-pdmic";
900 reg = <0xf8018000 0x124>;
901 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
902 dmas = <&dma0
903 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
904 | AT91_XDMAC_DT_PERID(50))>;
905 dma-names = "rx";
906 clocks = <&pdmic_clk>, <&pdmic_gclk>;
907 clock-names = "pclk", "gclk";
908 status = "disabled";
909 };
910
911 uart0: serial@f801c000 {
912 compatible = "atmel,at91sam9260-usart";
913 reg = <0xf801c000 0x100>;
914 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
915 dmas = <&dma0
916 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
917 AT91_XDMAC_DT_PERID(35))>,
918 <&dma0
919 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
920 AT91_XDMAC_DT_PERID(36))>;
921 dma-names = "tx", "rx";
922 clocks = <&uart0_clk>;
923 clock-names = "usart";
924 status = "disabled";
925 };
926
927 uart1: serial@f8020000 {
928 compatible = "atmel,at91sam9260-usart";
929 reg = <0xf8020000 0x100>;
930 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
931 dmas = <&dma0
932 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
933 AT91_XDMAC_DT_PERID(37))>,
934 <&dma0
935 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
936 AT91_XDMAC_DT_PERID(38))>;
937 dma-names = "tx", "rx";
938 clocks = <&uart1_clk>;
939 clock-names = "usart";
940 status = "disabled";
941 };
942
943 uart2: serial@f8024000 {
944 compatible = "atmel,at91sam9260-usart";
945 reg = <0xf8024000 0x100>;
946 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
947 dmas = <&dma0
948 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
949 AT91_XDMAC_DT_PERID(39))>,
950 <&dma0
951 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
952 AT91_XDMAC_DT_PERID(40))>;
953 dma-names = "tx", "rx";
954 clocks = <&uart2_clk>;
955 clock-names = "usart";
956 status = "disabled";
957 };
958
959 i2c0: i2c@f8028000 {
960 compatible = "atmel,sama5d2-i2c";
961 reg = <0xf8028000 0x100>;
962 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
963 dmas = <&dma0
964 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
965 AT91_XDMAC_DT_PERID(0))>,
966 <&dma0
967 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
968 AT91_XDMAC_DT_PERID(1))>;
969 dma-names = "tx", "rx";
970 #address-cells = <1>;
971 #size-cells = <0>;
972 clocks = <&twi0_clk>;
973 status = "disabled";
974 };
975
976 flx0: flexcom@f8034000 {
977 compatible = "atmel,sama5d2-flexcom";
978 reg = <0xf8034000 0x200>;
979 clocks = <&flx0_clk>;
980 #address-cells = <1>;
981 #size-cells = <1>;
982 ranges = <0x0 0xf8034000 0x800>;
983 status = "disabled";
984 };
985
986 flx1: flexcom@f8038000 {
987 compatible = "atmel,sama5d2-flexcom";
988 reg = <0xf8038000 0x200>;
989 clocks = <&flx1_clk>;
990 #address-cells = <1>;
991 #size-cells = <1>;
992 ranges = <0x0 0xf8038000 0x800>;
993 status = "disabled";
994 };
995
996 rstc@f8048000 {
997 compatible = "atmel,sama5d3-rstc";
998 reg = <0xf8048000 0x10>;
999 clocks = <&clk32k>;
1000 };
1001
1002 pit: timer@f8048030 {
1003 compatible = "atmel,at91sam9260-pit";
1004 reg = <0xf8048030 0x10>;
1005 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1006 clocks = <&h32ck>;
1007 };
1008
1009 watchdog@f8048040 {
1010 compatible = "atmel,sama5d4-wdt";
1011 reg = <0xf8048040 0x10>;
1012 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1013 status = "disabled";
1014 };
1015
1016 sckc@f8048050 {
1017 compatible = "atmel,at91sam9x5-sckc";
1018 reg = <0xf8048050 0x4>;
1019
1020 slow_rc_osc: slow_rc_osc {
1021 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1022 #clock-cells = <0>;
1023 clock-frequency = <32768>;
1024 clock-accuracy = <250000000>;
1025 atmel,startup-time-usec = <75>;
1026 };
1027
1028 slow_osc: slow_osc {
1029 compatible = "atmel,at91sam9x5-clk-slow-osc";
1030 #clock-cells = <0>;
1031 clocks = <&slow_xtal>;
1032 atmel,startup-time-usec = <1200000>;
1033 };
1034
1035 clk32k: slowck {
1036 compatible = "atmel,at91sam9x5-clk-slow";
1037 #clock-cells = <0>;
1038 clocks = <&slow_rc_osc &slow_osc>;
1039 };
1040 };
1041
1042 rtc@f80480b0 {
1043 compatible = "atmel,at91rm9200-rtc";
1044 reg = <0xf80480b0 0x30>;
1045 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1046 clocks = <&clk32k>;
1047 };
1048
1049 spi1: spi@fc000000 {
1050 compatible = "atmel,at91rm9200-spi";
1051 reg = <0xfc000000 0x100>;
1052 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1053 dmas = <&dma0
1054 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1055 AT91_XDMAC_DT_PERID(8))>,
1056 <&dma0
1057 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1058 AT91_XDMAC_DT_PERID(9))>;
1059 dma-names = "tx", "rx";
1060 clocks = <&spi1_clk>;
1061 clock-names = "spi_clk";
1062 atmel,fifo-size = <16>;
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 status = "disabled";
1066 };
1067
1068 uart3: serial@fc008000 {
1069 compatible = "atmel,at91sam9260-usart";
1070 reg = <0xfc008000 0x100>;
1071 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1072 dmas = <&dma0
1073 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1074 AT91_XDMAC_DT_PERID(41))>,
1075 <&dma0
1076 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1077 AT91_XDMAC_DT_PERID(42))>;
1078 dma-names = "tx", "rx";
1079 clocks = <&uart3_clk>;
1080 clock-names = "usart";
1081 status = "disabled";
1082 };
1083
1084 uart4: serial@fc00c000 {
1085 compatible = "atmel,at91sam9260-usart";
1086 reg = <0xfc00c000 0x100>;
1087 dmas = <&dma0
1088 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1089 AT91_XDMAC_DT_PERID(43))>,
1090 <&dma0
1091 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1092 AT91_XDMAC_DT_PERID(44))>;
1093 dma-names = "tx", "rx";
1094 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1095 clocks = <&uart4_clk>;
1096 clock-names = "usart";
1097 status = "disabled";
1098 };
1099
1100 flx2: flexcom@fc010000 {
1101 compatible = "atmel,sama5d2-flexcom";
1102 reg = <0xfc010000 0x200>;
1103 clocks = <&flx2_clk>;
1104 #address-cells = <1>;
1105 #size-cells = <1>;
1106 ranges = <0x0 0xfc010000 0x800>;
1107 status = "disabled";
1108 };
1109
1110 flx3: flexcom@fc014000 {
1111 compatible = "atmel,sama5d2-flexcom";
1112 reg = <0xfc014000 0x200>;
1113 clocks = <&flx3_clk>;
1114 #address-cells = <1>;
1115 #size-cells = <1>;
1116 ranges = <0x0 0xfc014000 0x800>;
1117 status = "disabled";
1118 };
1119
1120 flx4: flexcom@fc018000 {
1121 compatible = "atmel,sama5d2-flexcom";
1122 reg = <0xfc018000 0x200>;
1123 clocks = <&flx4_clk>;
1124 #address-cells = <1>;
1125 #size-cells = <1>;
1126 ranges = <0x0 0xfc018000 0x800>;
1127 status = "disabled";
1128 };
1129
1130 aic: interrupt-controller@fc020000 {
1131 #interrupt-cells = <3>;
1132 compatible = "atmel,sama5d2-aic";
1133 interrupt-controller;
1134 reg = <0xfc020000 0x200>;
1135 atmel,external-irqs = <49>;
1136 };
1137
1138 i2c1: i2c@fc028000 {
1139 compatible = "atmel,sama5d2-i2c";
1140 reg = <0xfc028000 0x100>;
1141 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1142 dmas = <&dma0
1143 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1144 AT91_XDMAC_DT_PERID(2))>,
1145 <&dma0
1146 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1147 AT91_XDMAC_DT_PERID(3))>;
1148 dma-names = "tx", "rx";
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 clocks = <&twi1_clk>;
1152 status = "disabled";
1153 };
1154
1155 adc: adc@fc030000 {
1156 compatible = "atmel,sama5d2-adc";
1157 reg = <0xfc030000 0x100>;
1158 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1159 clocks = <&adc_clk>;
1160 clock-names = "adc_clk";
1161 atmel,min-sample-rate-hz = <200000>;
1162 atmel,max-sample-rate-hz = <20000000>;
1163 atmel,startup-time-ms = <4>;
1164 status = "disabled";
1165 };
1166
1167 pioA: pinctrl@fc038000 {
1168 compatible = "atmel,sama5d2-pinctrl";
1169 reg = <0xfc038000 0x600>;
1170 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1171 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1172 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1173 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1174 interrupt-controller;
1175 #interrupt-cells = <2>;
1176 gpio-controller;
1177 #gpio-cells = <2>;
1178 clocks = <&pioA_clk>;
1179 };
1180
1181 tdes@fc044000 {
1182 compatible = "atmel,at91sam9g46-tdes";
1183 reg = <0xfc044000 0x100>;
1184 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1185 dmas = <&dma0
1186 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1187 AT91_XDMAC_DT_PERID(28))>,
1188 <&dma0
1189 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1190 AT91_XDMAC_DT_PERID(29))>;
1191 dma-names = "tx", "rx";
1192 clocks = <&tdes_clk>;
1193 clock-names = "tdes_clk";
1194 status = "okay";
1195 };
1196 };
1197 };
1198 };
Linux kernel - Deliverables
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