2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/dma/at91.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/clock/at91.h>
52 model = "Atmel SAMA5D2 family SoC";
53 compatible = "atmel,sama5d2";
54 interrupt-parent = <&aic>;
69 compatible = "arm,cortex-a5";
71 next-level-cache = <&L2>;
76 reg = <0x20000000 0x20000000>;
80 slow_xtal: slow_xtal {
81 compatible = "fixed-clock";
83 clock-frequency = <0>;
86 main_xtal: main_xtal {
87 compatible = "fixed-clock";
89 clock-frequency = <0>;
93 ns_sram: sram@00200000 {
94 compatible = "mmio-sram";
95 reg = <0x00200000 0x20000>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
104 usb0: gadget@00300000 {
105 #address-cells = <1>;
107 compatible = "atmel,sama5d3-udc";
108 reg = <0x00300000 0x100000
110 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
111 clocks = <&udphs_clk>, <&utmi>;
112 clock-names = "pclk", "hclk";
117 atmel,fifo-size = <64>;
118 atmel,nb-banks = <1>;
123 atmel,fifo-size = <1024>;
124 atmel,nb-banks = <3>;
131 atmel,fifo-size = <1024>;
132 atmel,nb-banks = <3>;
139 atmel,fifo-size = <1024>;
140 atmel,nb-banks = <2>;
147 atmel,fifo-size = <1024>;
148 atmel,nb-banks = <2>;
155 atmel,fifo-size = <1024>;
156 atmel,nb-banks = <2>;
163 atmel,fifo-size = <1024>;
164 atmel,nb-banks = <2>;
171 atmel,fifo-size = <1024>;
172 atmel,nb-banks = <2>;
179 atmel,fifo-size = <1024>;
180 atmel,nb-banks = <2>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
207 atmel,fifo-size = <1024>;
208 atmel,nb-banks = <2>;
214 atmel,fifo-size = <1024>;
215 atmel,nb-banks = <2>;
221 atmel,fifo-size = <1024>;
222 atmel,nb-banks = <2>;
228 atmel,fifo-size = <1024>;
229 atmel,nb-banks = <2>;
234 usb1: ohci@00400000 {
235 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
236 reg = <0x00400000 0x100000>;
237 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
238 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
239 clock-names = "ohci_clk", "hclk", "uhpck";
243 usb2: ehci@00500000 {
244 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
245 reg = <0x00500000 0x100000>;
246 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
247 clocks = <&utmi>, <&uhphs_clk>;
248 clock-names = "usb_clk", "ehci_clk";
252 L2: cache-controller@00a00000 {
253 compatible = "arm,pl310-cache";
254 reg = <0x00a00000 0x1000>;
255 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
260 nand0: nand@80000000 {
261 compatible = "atmel,sama5d2-nand";
262 #address-cells = <1>;
265 reg = < /* EBI CS3 */
266 0x80000000 0x08000000
268 0xf8014070 0x00000490
269 /* SMC PMECC Error Location regs */
270 0xf8014500 0x00000200
271 /* ROM Galois tables */
272 0x00040000 0x00018000
274 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
275 atmel,nand-addr-offset = <21>;
276 atmel,nand-cmd-offset = <22>;
279 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
283 compatible = "atmel,sama5d3-nfc";
284 #address-cells = <1>;
286 reg = < /* NFC Command Registers */
287 0xc0000000 0x08000000
289 0xf8014000 0x00000070
291 0x00100000 0x00100000
293 clocks = <&hsmc_clk>;
298 sdmmc0: sdio-host@a0000000 {
299 compatible = "atmel,sama5d2-sdhci";
300 reg = <0xa0000000 0x300>;
301 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
302 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
303 clock-names = "hclock", "multclk", "baseclk";
307 sdmmc1: sdio-host@b0000000 {
308 compatible = "atmel,sama5d2-sdhci";
309 reg = <0xb0000000 0x300>;
310 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
311 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
312 clock-names = "hclock", "multclk", "baseclk";
317 compatible = "simple-bus";
318 #address-cells = <1>;
322 hlcdc: hlcdc@f0000000 {
323 compatible = "atmel,sama5d2-hlcdc";
324 reg = <0xf0000000 0x2000>;
325 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
326 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
327 clock-names = "periph_clk","sys_clk", "slow_clk";
330 hlcdc-display-controller {
331 compatible = "atmel,hlcdc-display-controller";
332 #address-cells = <1>;
336 #address-cells = <1>;
342 hlcdc_pwm: hlcdc-pwm {
343 compatible = "atmel,hlcdc-pwm";
348 ramc0: ramc@f000c000 {
349 compatible = "atmel,sama5d3-ddramc";
350 reg = <0xf000c000 0x200>;
351 clocks = <&ddrck>, <&mpddr_clk>;
352 clock-names = "ddrck", "mpddr";
355 dma0: dma-controller@f0010000 {
356 compatible = "atmel,sama5d4-dma";
357 reg = <0xf0010000 0x1000>;
358 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
360 clocks = <&dma0_clk>;
361 clock-names = "dma_clk";
365 compatible = "atmel,sama5d2-pmc", "syscon";
366 reg = <0xf0014000 0x160>;
367 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
368 interrupt-controller;
369 #address-cells = <1>;
371 #interrupt-cells = <1>;
373 main_rc_osc: main_rc_osc {
374 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
376 interrupt-parent = <&pmc>;
377 interrupts = <AT91_PMC_MOSCRCS>;
378 clock-frequency = <12000000>;
379 clock-accuracy = <100000000>;
383 compatible = "atmel,at91rm9200-clk-main-osc";
385 interrupt-parent = <&pmc>;
386 interrupts = <AT91_PMC_MOSCS>;
387 clocks = <&main_xtal>;
391 compatible = "atmel,at91sam9x5-clk-main";
393 interrupt-parent = <&pmc>;
394 interrupts = <AT91_PMC_MOSCSELS>;
395 clocks = <&main_rc_osc &main_osc>;
399 compatible = "atmel,sama5d3-clk-pll";
401 interrupt-parent = <&pmc>;
402 interrupts = <AT91_PMC_LOCKA>;
405 atmel,clk-input-range = <12000000 12000000>;
406 #atmel,pll-clk-output-range-cells = <4>;
407 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
411 compatible = "atmel,at91sam9x5-clk-plldiv";
417 compatible = "atmel,at91sam9x5-clk-utmi";
419 interrupt-parent = <&pmc>;
420 interrupts = <AT91_PMC_LOCKU>;
425 compatible = "atmel,at91sam9x5-clk-master";
427 interrupt-parent = <&pmc>;
428 interrupts = <AT91_PMC_MCKRDY>;
429 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
430 atmel,clk-output-range = <124000000 166000000>;
431 atmel,clk-divisors = <1 2 4 3>;
436 compatible = "atmel,sama5d4-clk-h32mx";
441 compatible = "atmel,at91sam9x5-clk-usb";
443 clocks = <&plladiv>, <&utmi>;
447 compatible = "atmel,at91sam9x5-clk-programmable";
448 #address-cells = <1>;
450 interrupt-parent = <&pmc>;
451 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
456 interrupts = <AT91_PMC_PCKRDY(0)>;
462 interrupts = <AT91_PMC_PCKRDY(1)>;
468 interrupts = <AT91_PMC_PCKRDY(2)>;
473 compatible = "atmel,at91rm9200-clk-system";
474 #address-cells = <1>;
527 compatible = "atmel,at91sam9x5-clk-peripheral";
528 #address-cells = <1>;
532 macb0_clk: macb0_clk {
535 atmel,clk-output-range = <0 83000000>;
541 atmel,clk-output-range = <0 83000000>;
544 matrix1_clk: matrix1_clk {
557 atmel,clk-output-range = <0 83000000>;
563 atmel,clk-output-range = <0 83000000>;
569 atmel,clk-output-range = <0 83000000>;
575 atmel,clk-output-range = <0 83000000>;
581 atmel,clk-output-range = <0 83000000>;
587 atmel,clk-output-range = <0 83000000>;
590 uart0_clk: uart0_clk {
593 atmel,clk-output-range = <0 83000000>;
596 uart1_clk: uart1_clk {
599 atmel,clk-output-range = <0 83000000>;
602 uart2_clk: uart2_clk {
605 atmel,clk-output-range = <0 83000000>;
608 uart3_clk: uart3_clk {
611 atmel,clk-output-range = <0 83000000>;
614 uart4_clk: uart4_clk {
617 atmel,clk-output-range = <0 83000000>;
623 atmel,clk-output-range = <0 83000000>;
629 atmel,clk-output-range = <0 83000000>;
635 atmel,clk-output-range = <0 83000000>;
641 atmel,clk-output-range = <0 83000000>;
647 atmel,clk-output-range = <0 83000000>;
653 atmel,clk-output-range = <0 83000000>;
659 atmel,clk-output-range = <0 83000000>;
665 atmel,clk-output-range = <0 83000000>;
668 uhphs_clk: uhphs_clk {
671 atmel,clk-output-range = <0 83000000>;
674 udphs_clk: udphs_clk {
677 atmel,clk-output-range = <0 83000000>;
683 atmel,clk-output-range = <0 83000000>;
689 atmel,clk-output-range = <0 83000000>;
695 atmel,clk-output-range = <0 83000000>;
698 pdmic_clk: pdmic_clk {
701 atmel,clk-output-range = <0 83000000>;
707 atmel,clk-output-range = <0 83000000>;
713 atmel,clk-output-range = <0 83000000>;
716 classd_clk: classd_clk {
719 atmel,clk-output-range = <0 83000000>;
724 compatible = "atmel,at91sam9x5-clk-peripheral";
725 #address-cells = <1>;
754 mpddr_clk: mpddr_clk {
759 matrix0_clk: matrix0_clk {
764 sdmmc0_hclk: sdmmc0_hclk {
769 sdmmc1_hclk: sdmmc1_hclk {
784 qspi0_clk: qspi0_clk {
789 qspi1_clk: qspi1_clk {
796 compatible = "atmel,sama5d2-clk-generated";
797 #address-cells = <1>;
799 interrupt-parent = <&pmc>;
800 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
802 sdmmc0_gclk: sdmmc0_gclk {
807 sdmmc1_gclk: sdmmc1_gclk {
812 tcb0_gclk: tcb0_gclk {
815 atmel,clk-output-range = <0 83000000>;
818 tcb1_gclk: tcb1_gclk {
821 atmel,clk-output-range = <0 83000000>;
827 atmel,clk-output-range = <0 83000000>;
830 pdmic_gclk: pdmic_gclk {
835 i2s0_gclk: i2s0_gclk {
840 i2s1_gclk: i2s1_gclk {
848 compatible = "atmel,at91sam9g46-sha";
849 reg = <0xf0028000 0x100>;
850 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
852 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
853 AT91_XDMAC_DT_PERID(30))>;
856 clock-names = "sha_clk";
861 compatible = "atmel,at91sam9g46-aes";
862 reg = <0xf002c000 0x100>;
863 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
865 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
866 AT91_XDMAC_DT_PERID(26))>,
868 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
869 AT91_XDMAC_DT_PERID(27))>;
870 dma-names = "tx", "rx";
872 clock-names = "aes_clk";
877 compatible = "atmel,at91rm9200-spi";
878 reg = <0xf8000000 0x100>;
879 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
881 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
882 AT91_XDMAC_DT_PERID(6))>,
884 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
885 AT91_XDMAC_DT_PERID(7))>;
886 dma-names = "tx", "rx";
887 clocks = <&spi0_clk>;
888 clock-names = "spi_clk";
889 atmel,fifo-size = <16>;
890 #address-cells = <1>;
895 macb0: ethernet@f8008000 {
896 compatible = "atmel,sama5d2-gem";
897 reg = <0xf8008000 0x1000>;
898 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
899 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
900 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
901 #address-cells = <1>;
903 clocks = <&macb0_clk>, <&macb0_clk>;
904 clock-names = "hclk", "pclk";
908 tcb0: timer@f800c000 {
909 compatible = "atmel,at91sam9x5-tcb";
910 reg = <0xf800c000 0x100>;
911 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
912 clocks = <&tcb0_clk>, <&clk32k>;
913 clock-names = "t0_clk", "slow_clk";
916 tcb1: timer@f8010000 {
917 compatible = "atmel,at91sam9x5-tcb";
918 reg = <0xf8010000 0x100>;
919 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
920 clocks = <&tcb1_clk>, <&clk32k>;
921 clock-names = "t0_clk", "slow_clk";
924 pdmic: pdmic@f8018000 {
925 compatible = "atmel,sama5d2-pdmic";
926 reg = <0xf8018000 0x124>;
927 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
929 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
930 | AT91_XDMAC_DT_PERID(50))>;
932 clocks = <&pdmic_clk>, <&pdmic_gclk>;
933 clock-names = "pclk", "gclk";
937 uart0: serial@f801c000 {
938 compatible = "atmel,at91sam9260-usart";
939 reg = <0xf801c000 0x100>;
940 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
942 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
943 AT91_XDMAC_DT_PERID(35))>,
945 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
946 AT91_XDMAC_DT_PERID(36))>;
947 dma-names = "tx", "rx";
948 clocks = <&uart0_clk>;
949 clock-names = "usart";
953 uart1: serial@f8020000 {
954 compatible = "atmel,at91sam9260-usart";
955 reg = <0xf8020000 0x100>;
956 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
958 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
959 AT91_XDMAC_DT_PERID(37))>,
961 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
962 AT91_XDMAC_DT_PERID(38))>;
963 dma-names = "tx", "rx";
964 clocks = <&uart1_clk>;
965 clock-names = "usart";
969 uart2: serial@f8024000 {
970 compatible = "atmel,at91sam9260-usart";
971 reg = <0xf8024000 0x100>;
972 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
974 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
975 AT91_XDMAC_DT_PERID(39))>,
977 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
978 AT91_XDMAC_DT_PERID(40))>;
979 dma-names = "tx", "rx";
980 clocks = <&uart2_clk>;
981 clock-names = "usart";
986 compatible = "atmel,sama5d2-i2c";
987 reg = <0xf8028000 0x100>;
988 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
990 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
991 AT91_XDMAC_DT_PERID(0))>,
993 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
994 AT91_XDMAC_DT_PERID(1))>;
995 dma-names = "tx", "rx";
996 #address-cells = <1>;
998 clocks = <&twi0_clk>;
1003 compatible = "atmel,sama5d2-sfr", "syscon";
1004 reg = <0xf8030000 0x98>;
1007 flx0: flexcom@f8034000 {
1008 compatible = "atmel,sama5d2-flexcom";
1009 reg = <0xf8034000 0x200>;
1010 clocks = <&flx0_clk>;
1011 #address-cells = <1>;
1013 ranges = <0x0 0xf8034000 0x800>;
1014 status = "disabled";
1017 flx1: flexcom@f8038000 {
1018 compatible = "atmel,sama5d2-flexcom";
1019 reg = <0xf8038000 0x200>;
1020 clocks = <&flx1_clk>;
1021 #address-cells = <1>;
1023 ranges = <0x0 0xf8038000 0x800>;
1024 status = "disabled";
1028 compatible = "atmel,sama5d3-rstc";
1029 reg = <0xf8048000 0x10>;
1034 compatible = "atmel,sama5d2-shdwc";
1035 reg = <0xf8048010 0x10>;
1037 #address-cells = <1>;
1039 atmel,wakeup-rtc-timer;
1042 pit: timer@f8048030 {
1043 compatible = "atmel,at91sam9260-pit";
1044 reg = <0xf8048030 0x10>;
1045 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1050 compatible = "atmel,sama5d4-wdt";
1051 reg = <0xf8048040 0x10>;
1052 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1054 status = "disabled";
1058 compatible = "atmel,at91sam9x5-sckc";
1059 reg = <0xf8048050 0x4>;
1061 slow_rc_osc: slow_rc_osc {
1062 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1064 clock-frequency = <32768>;
1065 clock-accuracy = <250000000>;
1066 atmel,startup-time-usec = <75>;
1069 slow_osc: slow_osc {
1070 compatible = "atmel,at91sam9x5-clk-slow-osc";
1072 clocks = <&slow_xtal>;
1073 atmel,startup-time-usec = <1200000>;
1077 compatible = "atmel,at91sam9x5-clk-slow";
1079 clocks = <&slow_rc_osc &slow_osc>;
1084 compatible = "atmel,at91rm9200-rtc";
1085 reg = <0xf80480b0 0x30>;
1086 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1090 spi1: spi@fc000000 {
1091 compatible = "atmel,at91rm9200-spi";
1092 reg = <0xfc000000 0x100>;
1093 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1095 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1096 AT91_XDMAC_DT_PERID(8))>,
1098 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1099 AT91_XDMAC_DT_PERID(9))>;
1100 dma-names = "tx", "rx";
1101 clocks = <&spi1_clk>;
1102 clock-names = "spi_clk";
1103 atmel,fifo-size = <16>;
1104 #address-cells = <1>;
1106 status = "disabled";
1109 uart3: serial@fc008000 {
1110 compatible = "atmel,at91sam9260-usart";
1111 reg = <0xfc008000 0x100>;
1112 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1114 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1115 AT91_XDMAC_DT_PERID(41))>,
1117 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1118 AT91_XDMAC_DT_PERID(42))>;
1119 dma-names = "tx", "rx";
1120 clocks = <&uart3_clk>;
1121 clock-names = "usart";
1122 status = "disabled";
1125 uart4: serial@fc00c000 {
1126 compatible = "atmel,at91sam9260-usart";
1127 reg = <0xfc00c000 0x100>;
1129 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1130 AT91_XDMAC_DT_PERID(43))>,
1132 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1133 AT91_XDMAC_DT_PERID(44))>;
1134 dma-names = "tx", "rx";
1135 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1136 clocks = <&uart4_clk>;
1137 clock-names = "usart";
1138 status = "disabled";
1141 flx2: flexcom@fc010000 {
1142 compatible = "atmel,sama5d2-flexcom";
1143 reg = <0xfc010000 0x200>;
1144 clocks = <&flx2_clk>;
1145 #address-cells = <1>;
1147 ranges = <0x0 0xfc010000 0x800>;
1148 status = "disabled";
1151 flx3: flexcom@fc014000 {
1152 compatible = "atmel,sama5d2-flexcom";
1153 reg = <0xfc014000 0x200>;
1154 clocks = <&flx3_clk>;
1155 #address-cells = <1>;
1157 ranges = <0x0 0xfc014000 0x800>;
1158 status = "disabled";
1161 flx4: flexcom@fc018000 {
1162 compatible = "atmel,sama5d2-flexcom";
1163 reg = <0xfc018000 0x200>;
1164 clocks = <&flx4_clk>;
1165 #address-cells = <1>;
1167 ranges = <0x0 0xfc018000 0x800>;
1168 status = "disabled";
1172 compatible = "atmel,at91sam9g45-trng";
1173 reg = <0xfc01c000 0x100>;
1174 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1175 clocks = <&trng_clk>;
1178 aic: interrupt-controller@fc020000 {
1179 #interrupt-cells = <3>;
1180 compatible = "atmel,sama5d2-aic";
1181 interrupt-controller;
1182 reg = <0xfc020000 0x200>;
1183 atmel,external-irqs = <49>;
1186 i2c1: i2c@fc028000 {
1187 compatible = "atmel,sama5d2-i2c";
1188 reg = <0xfc028000 0x100>;
1189 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1191 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1192 AT91_XDMAC_DT_PERID(2))>,
1194 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1195 AT91_XDMAC_DT_PERID(3))>;
1196 dma-names = "tx", "rx";
1197 #address-cells = <1>;
1199 clocks = <&twi1_clk>;
1200 status = "disabled";
1204 compatible = "atmel,sama5d2-adc";
1205 reg = <0xfc030000 0x100>;
1206 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1207 clocks = <&adc_clk>;
1208 clock-names = "adc_clk";
1209 atmel,min-sample-rate-hz = <200000>;
1210 atmel,max-sample-rate-hz = <20000000>;
1211 atmel,startup-time-ms = <4>;
1212 status = "disabled";
1215 pioA: pinctrl@fc038000 {
1216 compatible = "atmel,sama5d2-pinctrl";
1217 reg = <0xfc038000 0x600>;
1218 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1219 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1220 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1221 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1222 interrupt-controller;
1223 #interrupt-cells = <2>;
1226 clocks = <&pioA_clk>;
1230 compatible = "atmel,at91sam9g46-tdes";
1231 reg = <0xfc044000 0x100>;
1232 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1234 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1235 AT91_XDMAC_DT_PERID(28))>,
1237 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1238 AT91_XDMAC_DT_PERID(29))>;
1239 dma-names = "tx", "rx";
1240 clocks = <&tdes_clk>;
1241 clock-names = "tdes_clk";
1246 compatible = "atmel,sama5d2-chipid";
1247 reg = <0xfc069000 0x8>;