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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
[deliverable/linux.git] / arch / arm / boot / dts / sama5d3.dtsi
1 /*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11 #include "skeleton.dtsi"
12 #include <dt-bindings/dma/at91.h>
13 #include <dt-bindings/pinctrl/at91.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/at91.h>
17
18 / {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 serial5 = &uart0;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 tcb0 = &tcb0;
36 i2c0 = &i2c0;
37 i2c1 = &i2c1;
38 i2c2 = &i2c2;
39 ssc0 = &ssc0;
40 ssc1 = &ssc1;
41 pwm0 = &pwm0;
42 };
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a5";
49 reg = <0x0>;
50 };
51 };
52
53 pmu {
54 compatible = "arm,cortex-a5-pmu";
55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
56 };
57
58 memory {
59 reg = <0x20000000 0x8000000>;
60 };
61
62 clocks {
63 slow_xtal: slow_xtal {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
68
69 main_xtal: main_xtal {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <0>;
73 };
74
75 adc_op_clk: adc_op_clk{
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <1000000>;
79 };
80 };
81
82 sram: sram@00300000 {
83 compatible = "mmio-sram";
84 reg = <0x00300000 0x20000>;
85 };
86
87 ahb {
88 compatible = "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92
93 apb {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98
99 mmc0: mmc@f0000000 {
100 compatible = "atmel,hsmci";
101 reg = <0xf0000000 0x600>;
102 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
103 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
104 dma-names = "rxtx";
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
107 status = "disabled";
108 #address-cells = <1>;
109 #size-cells = <0>;
110 clocks = <&mci0_clk>;
111 clock-names = "mci_clk";
112 };
113
114 spi0: spi@f0004000 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 compatible = "atmel,at91rm9200-spi";
118 reg = <0xf0004000 0x100>;
119 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
120 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
121 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
122 dma-names = "tx", "rx";
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_spi0>;
125 clocks = <&spi0_clk>;
126 clock-names = "spi_clk";
127 status = "disabled";
128 };
129
130 ssc0: ssc@f0008000 {
131 compatible = "atmel,at91sam9g45-ssc";
132 reg = <0xf0008000 0x4000>;
133 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
134 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
135 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
136 dma-names = "tx", "rx";
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
139 clocks = <&ssc0_clk>;
140 clock-names = "pclk";
141 status = "disabled";
142 };
143
144 tcb0: timer@f0010000 {
145 compatible = "atmel,at91sam9x5-tcb";
146 reg = <0xf0010000 0x100>;
147 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
148 clocks = <&tcb0_clk>, <&clk32k>;
149 clock-names = "t0_clk", "slow_clk";
150 };
151
152 i2c0: i2c@f0014000 {
153 compatible = "atmel,at91sam9x5-i2c";
154 reg = <0xf0014000 0x4000>;
155 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
156 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
157 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
158 dma-names = "tx", "rx";
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_i2c0>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 clocks = <&twi0_clk>;
164 status = "disabled";
165 };
166
167 i2c1: i2c@f0018000 {
168 compatible = "atmel,at91sam9x5-i2c";
169 reg = <0xf0018000 0x4000>;
170 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
171 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
172 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
173 dma-names = "tx", "rx";
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c1>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 clocks = <&twi1_clk>;
179 status = "disabled";
180 };
181
182 usart0: serial@f001c000 {
183 compatible = "atmel,at91sam9260-usart";
184 reg = <0xf001c000 0x100>;
185 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
186 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
187 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
188 dma-names = "tx", "rx";
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_usart0>;
191 clocks = <&usart0_clk>;
192 clock-names = "usart";
193 status = "disabled";
194 };
195
196 usart1: serial@f0020000 {
197 compatible = "atmel,at91sam9260-usart";
198 reg = <0xf0020000 0x100>;
199 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
200 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
201 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
202 dma-names = "tx", "rx";
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_usart1>;
205 clocks = <&usart1_clk>;
206 clock-names = "usart";
207 status = "disabled";
208 };
209
210 uart0: serial@f0024000 {
211 compatible = "atmel,at91sam9260-usart";
212 reg = <0xf0024000 0x100>;
213 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_uart0>;
216 clocks = <&uart0_clk>;
217 clock-names = "usart";
218 status = "disabled";
219 };
220
221 pwm0: pwm@f002c000 {
222 compatible = "atmel,sama5d3-pwm";
223 reg = <0xf002c000 0x300>;
224 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
225 #pwm-cells = <3>;
226 clocks = <&pwm_clk>;
227 status = "disabled";
228 };
229
230 isi: isi@f0034000 {
231 compatible = "atmel,at91sam9g45-isi";
232 reg = <0xf0034000 0x4000>;
233 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_isi_data_0_7>;
236 clocks = <&isi_clk>;
237 clock-names = "isi_clk";
238 status = "disabled";
239 port {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 };
243 };
244
245 sfr: sfr@f0038000 {
246 compatible = "atmel,sama5d3-sfr", "syscon";
247 reg = <0xf0038000 0x60>;
248 };
249
250 mmc1: mmc@f8000000 {
251 compatible = "atmel,hsmci";
252 reg = <0xf8000000 0x600>;
253 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
254 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
255 dma-names = "rxtx";
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
258 status = "disabled";
259 #address-cells = <1>;
260 #size-cells = <0>;
261 clocks = <&mci1_clk>;
262 clock-names = "mci_clk";
263 };
264
265 spi1: spi@f8008000 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "atmel,at91rm9200-spi";
269 reg = <0xf8008000 0x100>;
270 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
271 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
272 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
273 dma-names = "tx", "rx";
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_spi1>;
276 clocks = <&spi1_clk>;
277 clock-names = "spi_clk";
278 status = "disabled";
279 };
280
281 ssc1: ssc@f800c000 {
282 compatible = "atmel,at91sam9g45-ssc";
283 reg = <0xf800c000 0x4000>;
284 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
285 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
286 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
287 dma-names = "tx", "rx";
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
290 clocks = <&ssc1_clk>;
291 clock-names = "pclk";
292 status = "disabled";
293 };
294
295 adc0: adc@f8018000 {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 compatible = "atmel,at91sam9x5-adc";
299 reg = <0xf8018000 0x100>;
300 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
301 pinctrl-names = "default";
302 pinctrl-0 = <
303 &pinctrl_adc0_adtrg
304 &pinctrl_adc0_ad0
305 &pinctrl_adc0_ad1
306 &pinctrl_adc0_ad2
307 &pinctrl_adc0_ad3
308 &pinctrl_adc0_ad4
309 &pinctrl_adc0_ad5
310 &pinctrl_adc0_ad6
311 &pinctrl_adc0_ad7
312 &pinctrl_adc0_ad8
313 &pinctrl_adc0_ad9
314 &pinctrl_adc0_ad10
315 &pinctrl_adc0_ad11
316 >;
317 clocks = <&adc_clk>,
318 <&adc_op_clk>;
319 clock-names = "adc_clk", "adc_op_clk";
320 atmel,adc-channels-used = <0xfff>;
321 atmel,adc-startup-time = <40>;
322 atmel,adc-use-external-triggers;
323 atmel,adc-vref = <3000>;
324 atmel,adc-res = <10 12>;
325 atmel,adc-sample-hold-time = <11>;
326 atmel,adc-res-names = "lowres", "highres";
327 status = "disabled";
328
329 trigger@0 {
330 reg = <0>;
331 trigger-name = "external-rising";
332 trigger-value = <0x1>;
333 trigger-external;
334 };
335 trigger@1 {
336 reg = <1>;
337 trigger-name = "external-falling";
338 trigger-value = <0x2>;
339 trigger-external;
340 };
341 trigger@2 {
342 reg = <2>;
343 trigger-name = "external-any";
344 trigger-value = <0x3>;
345 trigger-external;
346 };
347 trigger@3 {
348 reg = <3>;
349 trigger-name = "continuous";
350 trigger-value = <0x6>;
351 };
352 };
353
354 i2c2: i2c@f801c000 {
355 compatible = "atmel,at91sam9x5-i2c";
356 reg = <0xf801c000 0x4000>;
357 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
358 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
359 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
360 dma-names = "tx", "rx";
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_i2c2>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 clocks = <&twi2_clk>;
366 status = "disabled";
367 };
368
369 usart2: serial@f8020000 {
370 compatible = "atmel,at91sam9260-usart";
371 reg = <0xf8020000 0x100>;
372 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
373 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
374 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
375 dma-names = "tx", "rx";
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_usart2>;
378 clocks = <&usart2_clk>;
379 clock-names = "usart";
380 status = "disabled";
381 };
382
383 usart3: serial@f8024000 {
384 compatible = "atmel,at91sam9260-usart";
385 reg = <0xf8024000 0x100>;
386 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
387 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
388 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
389 dma-names = "tx", "rx";
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_usart3>;
392 clocks = <&usart3_clk>;
393 clock-names = "usart";
394 status = "disabled";
395 };
396
397 sha@f8034000 {
398 compatible = "atmel,at91sam9g46-sha";
399 reg = <0xf8034000 0x100>;
400 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
401 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
402 dma-names = "tx";
403 clocks = <&sha_clk>;
404 clock-names = "sha_clk";
405 };
406
407 aes@f8038000 {
408 compatible = "atmel,at91sam9g46-aes";
409 reg = <0xf8038000 0x100>;
410 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
411 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
412 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
413 dma-names = "tx", "rx";
414 clocks = <&aes_clk>;
415 clock-names = "aes_clk";
416 };
417
418 tdes@f803c000 {
419 compatible = "atmel,at91sam9g46-tdes";
420 reg = <0xf803c000 0x100>;
421 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
422 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
423 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
424 dma-names = "tx", "rx";
425 clocks = <&tdes_clk>;
426 clock-names = "tdes_clk";
427 };
428
429 trng@f8040000 {
430 compatible = "atmel,at91sam9g45-trng";
431 reg = <0xf8040000 0x100>;
432 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
433 clocks = <&trng_clk>;
434 };
435
436 dma0: dma-controller@ffffe600 {
437 compatible = "atmel,at91sam9g45-dma";
438 reg = <0xffffe600 0x200>;
439 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
440 #dma-cells = <2>;
441 clocks = <&dma0_clk>;
442 clock-names = "dma_clk";
443 };
444
445 dma1: dma-controller@ffffe800 {
446 compatible = "atmel,at91sam9g45-dma";
447 reg = <0xffffe800 0x200>;
448 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
449 #dma-cells = <2>;
450 clocks = <&dma1_clk>;
451 clock-names = "dma_clk";
452 };
453
454 ramc0: ramc@ffffea00 {
455 compatible = "atmel,sama5d3-ddramc";
456 reg = <0xffffea00 0x200>;
457 clocks = <&ddrck>, <&mpddr_clk>;
458 clock-names = "ddrck", "mpddr";
459 };
460
461 dbgu: serial@ffffee00 {
462 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
463 reg = <0xffffee00 0x200>;
464 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
465 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
466 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
467 dma-names = "tx", "rx";
468 pinctrl-names = "default";
469 pinctrl-0 = <&pinctrl_dbgu>;
470 clocks = <&dbgu_clk>;
471 clock-names = "usart";
472 status = "disabled";
473 };
474
475 aic: interrupt-controller@fffff000 {
476 #interrupt-cells = <3>;
477 compatible = "atmel,sama5d3-aic";
478 interrupt-controller;
479 reg = <0xfffff000 0x200>;
480 atmel,external-irqs = <47>;
481 };
482
483 pinctrl@fffff200 {
484 #address-cells = <1>;
485 #size-cells = <1>;
486 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
487 ranges = <0xfffff200 0xfffff200 0xa00>;
488 atmel,mux-mask = <
489 /* A B C */
490 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
491 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
492 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
493 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
494 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
495 >;
496
497 /* shared pinctrl settings */
498 adc0 {
499 pinctrl_adc0_adtrg: adc0_adtrg {
500 atmel,pins =
501 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
502 };
503 pinctrl_adc0_ad0: adc0_ad0 {
504 atmel,pins =
505 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
506 };
507 pinctrl_adc0_ad1: adc0_ad1 {
508 atmel,pins =
509 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
510 };
511 pinctrl_adc0_ad2: adc0_ad2 {
512 atmel,pins =
513 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
514 };
515 pinctrl_adc0_ad3: adc0_ad3 {
516 atmel,pins =
517 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
518 };
519 pinctrl_adc0_ad4: adc0_ad4 {
520 atmel,pins =
521 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
522 };
523 pinctrl_adc0_ad5: adc0_ad5 {
524 atmel,pins =
525 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
526 };
527 pinctrl_adc0_ad6: adc0_ad6 {
528 atmel,pins =
529 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
530 };
531 pinctrl_adc0_ad7: adc0_ad7 {
532 atmel,pins =
533 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
534 };
535 pinctrl_adc0_ad8: adc0_ad8 {
536 atmel,pins =
537 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
538 };
539 pinctrl_adc0_ad9: adc0_ad9 {
540 atmel,pins =
541 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
542 };
543 pinctrl_adc0_ad10: adc0_ad10 {
544 atmel,pins =
545 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
546 };
547 pinctrl_adc0_ad11: adc0_ad11 {
548 atmel,pins =
549 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
550 };
551 };
552
553 dbgu {
554 pinctrl_dbgu: dbgu-0 {
555 atmel,pins =
556 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
557 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
558 };
559 };
560
561 i2c0 {
562 pinctrl_i2c0: i2c0-0 {
563 atmel,pins =
564 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
565 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
566 };
567 };
568
569 i2c1 {
570 pinctrl_i2c1: i2c1-0 {
571 atmel,pins =
572 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
573 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
574 };
575 };
576
577 i2c2 {
578 pinctrl_i2c2: i2c2-0 {
579 atmel,pins =
580 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
581 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
582 };
583 };
584
585 isi {
586 pinctrl_isi_data_0_7: isi-0-data-0-7 {
587 atmel,pins =
588 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
589 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
590 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
591 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
592 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
593 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
594 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
595 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
596 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
597 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
598 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
599 };
600
601 pinctrl_isi_data_8_9: isi-0-data-8-9 {
602 atmel,pins =
603 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
604 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
605 };
606
607 pinctrl_isi_data_10_11: isi-0-data-10-11 {
608 atmel,pins =
609 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
610 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
611 };
612 };
613
614 mmc0 {
615 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
616 atmel,pins =
617 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
618 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
619 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
620 };
621 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
622 atmel,pins =
623 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
624 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
625 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
626 };
627 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
628 atmel,pins =
629 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
630 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
631 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
632 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
633 };
634 };
635
636 mmc1 {
637 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
638 atmel,pins =
639 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
640 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
641 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
642 };
643 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
644 atmel,pins =
645 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
646 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
647 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
648 };
649 };
650
651 nand0 {
652 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
653 atmel,pins =
654 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
655 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
656 };
657 };
658
659 pwm0 {
660 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
661 atmel,pins =
662 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
663 };
664 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
665 atmel,pins =
666 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
667 };
668 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
669 atmel,pins =
670 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
671 };
672 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
673 atmel,pins =
674 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
675 };
676
677 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
678 atmel,pins =
679 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
680 };
681 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
682 atmel,pins =
683 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
684 };
685 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
686 atmel,pins =
687 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
688 };
689 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
690 atmel,pins =
691 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
692 };
693 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
694 atmel,pins =
695 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
696 };
697 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
698 atmel,pins =
699 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
700 };
701
702 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
703 atmel,pins =
704 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
705 };
706 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
707 atmel,pins =
708 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
709 };
710 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
711 atmel,pins =
712 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
713 };
714 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
715 atmel,pins =
716 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
717 };
718
719 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
720 atmel,pins =
721 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
722 };
723 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
724 atmel,pins =
725 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
726 };
727 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
728 atmel,pins =
729 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
730 };
731 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
732 atmel,pins =
733 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
734 };
735 };
736
737 spi0 {
738 pinctrl_spi0: spi0-0 {
739 atmel,pins =
740 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
741 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
742 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
743 };
744 };
745
746 spi1 {
747 pinctrl_spi1: spi1-0 {
748 atmel,pins =
749 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
750 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
751 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
752 };
753 };
754
755 ssc0 {
756 pinctrl_ssc0_tx: ssc0_tx {
757 atmel,pins =
758 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
759 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
760 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
761 };
762
763 pinctrl_ssc0_rx: ssc0_rx {
764 atmel,pins =
765 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
766 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
767 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
768 };
769 };
770
771 ssc1 {
772 pinctrl_ssc1_tx: ssc1_tx {
773 atmel,pins =
774 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
775 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
776 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
777 };
778
779 pinctrl_ssc1_rx: ssc1_rx {
780 atmel,pins =
781 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
782 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
783 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
784 };
785 };
786
787 uart0 {
788 pinctrl_uart0: uart0-0 {
789 atmel,pins =
790 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* conflicts with PWMFI2, ISI_D8 */
791 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with ISI_PCK */
792 };
793 };
794
795 uart1 {
796 pinctrl_uart1: uart1-0 {
797 atmel,pins =
798 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* conflicts with TWD0, ISI_VSYNC */
799 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* conflicts with TWCK0, ISI_HSYNC */
800 };
801 };
802
803 usart0 {
804 pinctrl_usart0: usart0-0 {
805 atmel,pins =
806 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
807 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
808 };
809
810 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
811 atmel,pins =
812 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
813 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
814 };
815 };
816
817 usart1 {
818 pinctrl_usart1: usart1-0 {
819 atmel,pins =
820 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
821 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
822 };
823
824 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
825 atmel,pins =
826 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
827 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
828 };
829 };
830
831 usart2 {
832 pinctrl_usart2: usart2-0 {
833 atmel,pins =
834 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
835 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
836 };
837
838 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
839 atmel,pins =
840 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
841 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
842 };
843 };
844
845 usart3 {
846 pinctrl_usart3: usart3-0 {
847 atmel,pins =
848 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
849 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
850 };
851
852 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
853 atmel,pins =
854 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
855 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
856 };
857 };
858
859
860 pioA: gpio@fffff200 {
861 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
862 reg = <0xfffff200 0x100>;
863 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
864 #gpio-cells = <2>;
865 gpio-controller;
866 interrupt-controller;
867 #interrupt-cells = <2>;
868 clocks = <&pioA_clk>;
869 };
870
871 pioB: gpio@fffff400 {
872 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
873 reg = <0xfffff400 0x100>;
874 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
875 #gpio-cells = <2>;
876 gpio-controller;
877 interrupt-controller;
878 #interrupt-cells = <2>;
879 clocks = <&pioB_clk>;
880 };
881
882 pioC: gpio@fffff600 {
883 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
884 reg = <0xfffff600 0x100>;
885 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
886 #gpio-cells = <2>;
887 gpio-controller;
888 interrupt-controller;
889 #interrupt-cells = <2>;
890 clocks = <&pioC_clk>;
891 };
892
893 pioD: gpio@fffff800 {
894 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
895 reg = <0xfffff800 0x100>;
896 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
897 #gpio-cells = <2>;
898 gpio-controller;
899 interrupt-controller;
900 #interrupt-cells = <2>;
901 clocks = <&pioD_clk>;
902 };
903
904 pioE: gpio@fffffa00 {
905 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
906 reg = <0xfffffa00 0x100>;
907 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
908 #gpio-cells = <2>;
909 gpio-controller;
910 interrupt-controller;
911 #interrupt-cells = <2>;
912 clocks = <&pioE_clk>;
913 };
914 };
915
916 pmc: pmc@fffffc00 {
917 compatible = "atmel,sama5d3-pmc", "syscon";
918 reg = <0xfffffc00 0x120>;
919 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
920 interrupt-controller;
921 #address-cells = <1>;
922 #size-cells = <0>;
923 #interrupt-cells = <1>;
924
925 main_rc_osc: main_rc_osc {
926 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
927 #clock-cells = <0>;
928 interrupt-parent = <&pmc>;
929 interrupts = <AT91_PMC_MOSCRCS>;
930 clock-frequency = <12000000>;
931 clock-accuracy = <50000000>;
932 };
933
934 main_osc: main_osc {
935 compatible = "atmel,at91rm9200-clk-main-osc";
936 #clock-cells = <0>;
937 interrupt-parent = <&pmc>;
938 interrupts = <AT91_PMC_MOSCS>;
939 clocks = <&main_xtal>;
940 };
941
942 main: mainck {
943 compatible = "atmel,at91sam9x5-clk-main";
944 #clock-cells = <0>;
945 interrupt-parent = <&pmc>;
946 interrupts = <AT91_PMC_MOSCSELS>;
947 clocks = <&main_rc_osc &main_osc>;
948 };
949
950 plla: pllack {
951 compatible = "atmel,sama5d3-clk-pll";
952 #clock-cells = <0>;
953 interrupt-parent = <&pmc>;
954 interrupts = <AT91_PMC_LOCKA>;
955 clocks = <&main>;
956 reg = <0>;
957 atmel,clk-input-range = <8000000 50000000>;
958 #atmel,pll-clk-output-range-cells = <4>;
959 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
960 };
961
962 plladiv: plladivck {
963 compatible = "atmel,at91sam9x5-clk-plldiv";
964 #clock-cells = <0>;
965 clocks = <&plla>;
966 };
967
968 utmi: utmick {
969 compatible = "atmel,at91sam9x5-clk-utmi";
970 #clock-cells = <0>;
971 interrupt-parent = <&pmc>;
972 interrupts = <AT91_PMC_LOCKU>;
973 clocks = <&main>;
974 };
975
976 mck: masterck {
977 compatible = "atmel,at91sam9x5-clk-master";
978 #clock-cells = <0>;
979 interrupt-parent = <&pmc>;
980 interrupts = <AT91_PMC_MCKRDY>;
981 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
982 atmel,clk-output-range = <0 166000000>;
983 atmel,clk-divisors = <1 2 4 3>;
984 };
985
986 usb: usbck {
987 compatible = "atmel,at91sam9x5-clk-usb";
988 #clock-cells = <0>;
989 clocks = <&plladiv>, <&utmi>;
990 };
991
992 prog: progck {
993 compatible = "atmel,at91sam9x5-clk-programmable";
994 #address-cells = <1>;
995 #size-cells = <0>;
996 interrupt-parent = <&pmc>;
997 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
998
999 prog0: prog0 {
1000 #clock-cells = <0>;
1001 reg = <0>;
1002 interrupts = <AT91_PMC_PCKRDY(0)>;
1003 };
1004
1005 prog1: prog1 {
1006 #clock-cells = <0>;
1007 reg = <1>;
1008 interrupts = <AT91_PMC_PCKRDY(1)>;
1009 };
1010
1011 prog2: prog2 {
1012 #clock-cells = <0>;
1013 reg = <2>;
1014 interrupts = <AT91_PMC_PCKRDY(2)>;
1015 };
1016 };
1017
1018 smd: smdclk {
1019 compatible = "atmel,at91sam9x5-clk-smd";
1020 #clock-cells = <0>;
1021 clocks = <&plladiv>, <&utmi>;
1022 };
1023
1024 systemck {
1025 compatible = "atmel,at91rm9200-clk-system";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1028
1029 ddrck: ddrck {
1030 #clock-cells = <0>;
1031 reg = <2>;
1032 clocks = <&mck>;
1033 };
1034
1035 smdck: smdck {
1036 #clock-cells = <0>;
1037 reg = <4>;
1038 clocks = <&smd>;
1039 };
1040
1041 uhpck: uhpck {
1042 #clock-cells = <0>;
1043 reg = <6>;
1044 clocks = <&usb>;
1045 };
1046
1047 udpck: udpck {
1048 #clock-cells = <0>;
1049 reg = <7>;
1050 clocks = <&usb>;
1051 };
1052
1053 pck0: pck0 {
1054 #clock-cells = <0>;
1055 reg = <8>;
1056 clocks = <&prog0>;
1057 };
1058
1059 pck1: pck1 {
1060 #clock-cells = <0>;
1061 reg = <9>;
1062 clocks = <&prog1>;
1063 };
1064
1065 pck2: pck2 {
1066 #clock-cells = <0>;
1067 reg = <10>;
1068 clocks = <&prog2>;
1069 };
1070 };
1071
1072 periphck {
1073 compatible = "atmel,at91sam9x5-clk-peripheral";
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1076 clocks = <&mck>;
1077
1078 dbgu_clk: dbgu_clk {
1079 #clock-cells = <0>;
1080 reg = <2>;
1081 };
1082
1083 hsmc_clk: hsmc_clk {
1084 #clock-cells = <0>;
1085 reg = <5>;
1086 };
1087
1088 pioA_clk: pioA_clk {
1089 #clock-cells = <0>;
1090 reg = <6>;
1091 };
1092
1093 pioB_clk: pioB_clk {
1094 #clock-cells = <0>;
1095 reg = <7>;
1096 };
1097
1098 pioC_clk: pioC_clk {
1099 #clock-cells = <0>;
1100 reg = <8>;
1101 };
1102
1103 pioD_clk: pioD_clk {
1104 #clock-cells = <0>;
1105 reg = <9>;
1106 };
1107
1108 pioE_clk: pioE_clk {
1109 #clock-cells = <0>;
1110 reg = <10>;
1111 };
1112
1113 usart0_clk: usart0_clk {
1114 #clock-cells = <0>;
1115 reg = <12>;
1116 atmel,clk-output-range = <0 66000000>;
1117 };
1118
1119 usart1_clk: usart1_clk {
1120 #clock-cells = <0>;
1121 reg = <13>;
1122 atmel,clk-output-range = <0 66000000>;
1123 };
1124
1125 usart2_clk: usart2_clk {
1126 #clock-cells = <0>;
1127 reg = <14>;
1128 atmel,clk-output-range = <0 66000000>;
1129 };
1130
1131 usart3_clk: usart3_clk {
1132 #clock-cells = <0>;
1133 reg = <15>;
1134 atmel,clk-output-range = <0 66000000>;
1135 };
1136
1137 uart0_clk: uart0_clk {
1138 #clock-cells = <0>;
1139 reg = <16>;
1140 atmel,clk-output-range = <0 66000000>;
1141 };
1142
1143 twi0_clk: twi0_clk {
1144 reg = <18>;
1145 #clock-cells = <0>;
1146 atmel,clk-output-range = <0 16625000>;
1147 };
1148
1149 twi1_clk: twi1_clk {
1150 #clock-cells = <0>;
1151 reg = <19>;
1152 atmel,clk-output-range = <0 16625000>;
1153 };
1154
1155 twi2_clk: twi2_clk {
1156 #clock-cells = <0>;
1157 reg = <20>;
1158 atmel,clk-output-range = <0 16625000>;
1159 };
1160
1161 mci0_clk: mci0_clk {
1162 #clock-cells = <0>;
1163 reg = <21>;
1164 };
1165
1166 mci1_clk: mci1_clk {
1167 #clock-cells = <0>;
1168 reg = <22>;
1169 };
1170
1171 spi0_clk: spi0_clk {
1172 #clock-cells = <0>;
1173 reg = <24>;
1174 atmel,clk-output-range = <0 133000000>;
1175 };
1176
1177 spi1_clk: spi1_clk {
1178 #clock-cells = <0>;
1179 reg = <25>;
1180 atmel,clk-output-range = <0 133000000>;
1181 };
1182
1183 tcb0_clk: tcb0_clk {
1184 #clock-cells = <0>;
1185 reg = <26>;
1186 atmel,clk-output-range = <0 133000000>;
1187 };
1188
1189 pwm_clk: pwm_clk {
1190 #clock-cells = <0>;
1191 reg = <28>;
1192 };
1193
1194 adc_clk: adc_clk {
1195 #clock-cells = <0>;
1196 reg = <29>;
1197 atmel,clk-output-range = <0 66000000>;
1198 };
1199
1200 dma0_clk: dma0_clk {
1201 #clock-cells = <0>;
1202 reg = <30>;
1203 };
1204
1205 dma1_clk: dma1_clk {
1206 #clock-cells = <0>;
1207 reg = <31>;
1208 };
1209
1210 uhphs_clk: uhphs_clk {
1211 #clock-cells = <0>;
1212 reg = <32>;
1213 };
1214
1215 udphs_clk: udphs_clk {
1216 #clock-cells = <0>;
1217 reg = <33>;
1218 };
1219
1220 isi_clk: isi_clk {
1221 #clock-cells = <0>;
1222 reg = <37>;
1223 };
1224
1225 ssc0_clk: ssc0_clk {
1226 #clock-cells = <0>;
1227 reg = <38>;
1228 atmel,clk-output-range = <0 66000000>;
1229 };
1230
1231 ssc1_clk: ssc1_clk {
1232 #clock-cells = <0>;
1233 reg = <39>;
1234 atmel,clk-output-range = <0 66000000>;
1235 };
1236
1237 sha_clk: sha_clk {
1238 #clock-cells = <0>;
1239 reg = <42>;
1240 };
1241
1242 aes_clk: aes_clk {
1243 #clock-cells = <0>;
1244 reg = <43>;
1245 };
1246
1247 tdes_clk: tdes_clk {
1248 #clock-cells = <0>;
1249 reg = <44>;
1250 };
1251
1252 trng_clk: trng_clk {
1253 #clock-cells = <0>;
1254 reg = <45>;
1255 };
1256
1257 fuse_clk: fuse_clk {
1258 #clock-cells = <0>;
1259 reg = <48>;
1260 };
1261
1262 mpddr_clk: mpddr_clk {
1263 #clock-cells = <0>;
1264 reg = <49>;
1265 };
1266 };
1267 };
1268
1269 rstc@fffffe00 {
1270 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
1271 reg = <0xfffffe00 0x10>;
1272 clocks = <&clk32k>;
1273 };
1274
1275 shutdown-controller@fffffe10 {
1276 compatible = "atmel,at91sam9x5-shdwc";
1277 reg = <0xfffffe10 0x10>;
1278 clocks = <&clk32k>;
1279 };
1280
1281 pit: timer@fffffe30 {
1282 compatible = "atmel,at91sam9260-pit";
1283 reg = <0xfffffe30 0xf>;
1284 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1285 clocks = <&mck>;
1286 };
1287
1288 watchdog@fffffe40 {
1289 compatible = "atmel,at91sam9260-wdt";
1290 reg = <0xfffffe40 0x10>;
1291 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1292 clocks = <&clk32k>;
1293 atmel,watchdog-type = "hardware";
1294 atmel,reset-type = "all";
1295 atmel,dbg-halt;
1296 status = "disabled";
1297 };
1298
1299 sckc@fffffe50 {
1300 compatible = "atmel,at91sam9x5-sckc";
1301 reg = <0xfffffe50 0x4>;
1302
1303 slow_rc_osc: slow_rc_osc {
1304 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1305 #clock-cells = <0>;
1306 clock-frequency = <32768>;
1307 clock-accuracy = <50000000>;
1308 atmel,startup-time-usec = <75>;
1309 };
1310
1311 slow_osc: slow_osc {
1312 compatible = "atmel,at91sam9x5-clk-slow-osc";
1313 #clock-cells = <0>;
1314 clocks = <&slow_xtal>;
1315 atmel,startup-time-usec = <1200000>;
1316 };
1317
1318 clk32k: slowck {
1319 compatible = "atmel,at91sam9x5-clk-slow";
1320 #clock-cells = <0>;
1321 clocks = <&slow_rc_osc &slow_osc>;
1322 };
1323 };
1324
1325 rtc@fffffeb0 {
1326 compatible = "atmel,at91rm9200-rtc";
1327 reg = <0xfffffeb0 0x30>;
1328 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1329 clocks = <&clk32k>;
1330 };
1331 };
1332
1333 usb0: gadget@00500000 {
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1336 compatible = "atmel,sama5d3-udc";
1337 reg = <0x00500000 0x100000
1338 0xf8030000 0x4000>;
1339 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
1340 clocks = <&udphs_clk>, <&utmi>;
1341 clock-names = "pclk", "hclk";
1342 status = "disabled";
1343
1344 ep0 {
1345 reg = <0>;
1346 atmel,fifo-size = <64>;
1347 atmel,nb-banks = <1>;
1348 };
1349
1350 ep1 {
1351 reg = <1>;
1352 atmel,fifo-size = <1024>;
1353 atmel,nb-banks = <3>;
1354 atmel,can-dma;
1355 atmel,can-isoc;
1356 };
1357
1358 ep2 {
1359 reg = <2>;
1360 atmel,fifo-size = <1024>;
1361 atmel,nb-banks = <3>;
1362 atmel,can-dma;
1363 atmel,can-isoc;
1364 };
1365
1366 ep3 {
1367 reg = <3>;
1368 atmel,fifo-size = <1024>;
1369 atmel,nb-banks = <2>;
1370 atmel,can-dma;
1371 };
1372
1373 ep4 {
1374 reg = <4>;
1375 atmel,fifo-size = <1024>;
1376 atmel,nb-banks = <2>;
1377 atmel,can-dma;
1378 };
1379
1380 ep5 {
1381 reg = <5>;
1382 atmel,fifo-size = <1024>;
1383 atmel,nb-banks = <2>;
1384 atmel,can-dma;
1385 };
1386
1387 ep6 {
1388 reg = <6>;
1389 atmel,fifo-size = <1024>;
1390 atmel,nb-banks = <2>;
1391 atmel,can-dma;
1392 };
1393
1394 ep7 {
1395 reg = <7>;
1396 atmel,fifo-size = <1024>;
1397 atmel,nb-banks = <2>;
1398 atmel,can-dma;
1399 };
1400
1401 ep8 {
1402 reg = <8>;
1403 atmel,fifo-size = <1024>;
1404 atmel,nb-banks = <2>;
1405 };
1406
1407 ep9 {
1408 reg = <9>;
1409 atmel,fifo-size = <1024>;
1410 atmel,nb-banks = <2>;
1411 };
1412
1413 ep10 {
1414 reg = <10>;
1415 atmel,fifo-size = <1024>;
1416 atmel,nb-banks = <2>;
1417 };
1418
1419 ep11 {
1420 reg = <11>;
1421 atmel,fifo-size = <1024>;
1422 atmel,nb-banks = <2>;
1423 };
1424
1425 ep12 {
1426 reg = <12>;
1427 atmel,fifo-size = <1024>;
1428 atmel,nb-banks = <2>;
1429 };
1430
1431 ep13 {
1432 reg = <13>;
1433 atmel,fifo-size = <1024>;
1434 atmel,nb-banks = <2>;
1435 };
1436
1437 ep14 {
1438 reg = <14>;
1439 atmel,fifo-size = <1024>;
1440 atmel,nb-banks = <2>;
1441 };
1442
1443 ep15 {
1444 reg = <15>;
1445 atmel,fifo-size = <1024>;
1446 atmel,nb-banks = <2>;
1447 };
1448 };
1449
1450 usb1: ohci@00600000 {
1451 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1452 reg = <0x00600000 0x100000>;
1453 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1454 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1455 clock-names = "ohci_clk", "hclk", "uhpck";
1456 status = "disabled";
1457 };
1458
1459 usb2: ehci@00700000 {
1460 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1461 reg = <0x00700000 0x100000>;
1462 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1463 clocks = <&utmi>, <&uhphs_clk>;
1464 clock-names = "usb_clk", "ehci_clk";
1465 status = "disabled";
1466 };
1467
1468 nand0: nand@60000000 {
1469 compatible = "atmel,at91rm9200-nand";
1470 #address-cells = <1>;
1471 #size-cells = <1>;
1472 ranges;
1473 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1474 0xffffc070 0x00000490 /* SMC PMECC regs */
1475 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1476 0x00110000 0x00018000 /* ROM code */
1477 >;
1478 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1479 atmel,nand-addr-offset = <21>;
1480 atmel,nand-cmd-offset = <22>;
1481 atmel,nand-has-dma;
1482 pinctrl-names = "default";
1483 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1484 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1485 status = "disabled";
1486
1487 nfc@70000000 {
1488 compatible = "atmel,sama5d3-nfc";
1489 #address-cells = <1>;
1490 #size-cells = <1>;
1491 reg = <
1492 0x70000000 0x08000000 /* NFC Command Registers */
1493 0xffffc000 0x00000070 /* NFC HSMC regs */
1494 0x00200000 0x00100000 /* NFC SRAM banks */
1495 >;
1496 clocks = <&hsmc_clk>;
1497 };
1498 };
1499 };
1500 };
Linux kernel - Deliverables
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