2 * Device Tree Source for the SH73A0 SoC
4 * Copyright (C) 2012 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 /include/ "skeleton.dtsi"
13 #include <dt-bindings/clock/sh73a0-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,sh73a0";
19 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a9";
29 clock-frequency = <1196000000>;
30 power-domains = <&pd_a2sl>;
31 next-level-cache = <&L2>;
35 compatible = "arm,cortex-a9";
37 clock-frequency = <1196000000>;
38 power-domains = <&pd_a2sl>;
39 next-level-cache = <&L2>;
44 compatible = "arm,cortex-a9-twd-timer";
45 reg = <0xf0000600 0x20>;
46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
50 gic: interrupt-controller@f0001000 {
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
54 reg = <0xf0001000 0x1000>,
58 L2: cache-controller {
59 compatible = "arm,pl310-cache";
60 reg = <0xf0100000 0x1000>;
61 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
62 power-domains = <&pd_a3sm>;
63 arm,data-latency = <3 3 3>;
64 arm,tag-latency = <2 2 2>;
70 sbsc2: memory-controller@fb400000 {
71 compatible = "renesas,sbsc-sh73a0";
72 reg = <0xfb400000 0x400>;
73 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
75 interrupt-names = "sec", "temp";
76 power-domains = <&pd_a4bc1>;
79 sbsc1: memory-controller@fe400000 {
80 compatible = "renesas,sbsc-sh73a0";
81 reg = <0xfe400000 0x400>;
82 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-names = "sec", "temp";
85 power-domains = <&pd_a4bc0>;
89 compatible = "arm,cortex-a9-pmu";
90 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
94 cmt1: timer@e6138000 {
95 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
96 reg = <0xe6138000 0x200>;
97 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
100 power-domains = <&pd_c5>;
102 renesas,channels-mask = <0x3f>;
107 irqpin0: interrupt-controller@e6900000 {
108 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 reg = <0xe6900000 4>,
116 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
117 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
118 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
121 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
122 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
123 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
125 power-domains = <&pd_a4s>;
129 irqpin1: interrupt-controller@e6900004 {
130 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
131 #interrupt-cells = <2>;
132 interrupt-controller;
133 reg = <0xe6900004 4>,
138 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
139 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
143 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
144 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
145 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
147 power-domains = <&pd_a4s>;
151 irqpin2: interrupt-controller@e6900008 {
152 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
153 #interrupt-cells = <2>;
154 interrupt-controller;
155 reg = <0xe6900008 4>,
160 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
161 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
162 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
163 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
164 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
165 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
166 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
167 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
169 power-domains = <&pd_a4s>;
173 irqpin3: interrupt-controller@e690000c {
174 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
175 #interrupt-cells = <2>;
176 interrupt-controller;
177 reg = <0xe690000c 4>,
182 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
183 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
184 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
185 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
186 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
187 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
188 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
189 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
191 power-domains = <&pd_a4s>;
196 #address-cells = <1>;
198 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
199 reg = <0xe6820000 0x425>;
200 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
201 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
202 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
203 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
205 power-domains = <&pd_a3sp>;
210 #address-cells = <1>;
212 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
213 reg = <0xe6822000 0x425>;
214 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
215 GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
216 GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
217 GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
219 power-domains = <&pd_a3sp>;
224 #address-cells = <1>;
226 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
227 reg = <0xe6824000 0x425>;
228 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
229 GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
230 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
231 GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
233 power-domains = <&pd_a3sp>;
238 #address-cells = <1>;
240 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
241 reg = <0xe6826000 0x425>;
242 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
243 GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
247 power-domains = <&pd_a3sp>;
252 #address-cells = <1>;
254 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
255 reg = <0xe6828000 0x425>;
256 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
257 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
258 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
259 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
261 power-domains = <&pd_c5>;
265 mmcif: mmc@e6bd0000 {
266 compatible = "renesas,sh-mmcif";
267 reg = <0xe6bd0000 0x100>;
268 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
269 GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
271 power-domains = <&pd_a3sp>;
276 msiof0: spi@e6e20000 {
277 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
278 reg = <0xe6e20000 0x0064>;
279 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
281 power-domains = <&pd_a3sp>;
282 #address-cells = <1>;
287 msiof1: spi@e6e10000 {
288 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
289 reg = <0xe6e10000 0x0064>;
290 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
292 power-domains = <&pd_a3sp>;
293 #address-cells = <1>;
298 msiof2: spi@e6e00000 {
299 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
300 reg = <0xe6e00000 0x0064>;
301 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
303 power-domains = <&pd_a3sp>;
304 #address-cells = <1>;
309 msiof3: spi@e6c90000 {
310 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
311 reg = <0xe6c90000 0x0064>;
312 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
314 power-domains = <&pd_a3sp>;
315 #address-cells = <1>;
321 compatible = "renesas,sdhi-sh73a0";
322 reg = <0xee100000 0x100>;
323 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
327 power-domains = <&pd_a3sp>;
332 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
334 compatible = "renesas,sdhi-sh73a0";
335 reg = <0xee120000 0x100>;
336 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
339 power-domains = <&pd_a3sp>;
340 toshiba,mmc-wrprotect-disable;
346 compatible = "renesas,sdhi-sh73a0";
347 reg = <0xee140000 0x100>;
348 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
351 power-domains = <&pd_a3sp>;
352 toshiba,mmc-wrprotect-disable;
357 scifa0: serial@e6c40000 {
358 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
359 reg = <0xe6c40000 0x100>;
360 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
363 power-domains = <&pd_a3sp>;
367 scifa1: serial@e6c50000 {
368 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
369 reg = <0xe6c50000 0x100>;
370 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
373 power-domains = <&pd_a3sp>;
377 scifa2: serial@e6c60000 {
378 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
379 reg = <0xe6c60000 0x100>;
380 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
383 power-domains = <&pd_a3sp>;
387 scifa3: serial@e6c70000 {
388 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
389 reg = <0xe6c70000 0x100>;
390 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
393 power-domains = <&pd_a3sp>;
397 scifa4: serial@e6c80000 {
398 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
399 reg = <0xe6c80000 0x100>;
400 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
403 power-domains = <&pd_a3sp>;
407 scifa5: serial@e6cb0000 {
408 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
409 reg = <0xe6cb0000 0x100>;
410 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
413 power-domains = <&pd_a3sp>;
417 scifa6: serial@e6cc0000 {
418 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
419 reg = <0xe6cc0000 0x100>;
420 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
423 power-domains = <&pd_a3sp>;
427 scifa7: serial@e6cd0000 {
428 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
429 reg = <0xe6cd0000 0x100>;
430 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
433 power-domains = <&pd_a3sp>;
437 scifb: serial@e6c30000 {
438 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
439 reg = <0xe6c30000 0x100>;
440 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
443 power-domains = <&pd_a3sp>;
448 compatible = "renesas,pfc-sh73a0";
449 reg = <0xe6050000 0x8000>,
454 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
456 interrupts-extended =
457 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
458 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
459 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
460 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
461 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
462 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
463 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
464 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
465 power-domains = <&pd_c5>;
468 sysc: system-controller@e6180000 {
469 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
470 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
474 #address-cells = <1>;
476 #power-domain-cells = <0>;
480 #power-domain-cells = <0>;
485 #power-domain-cells = <0>;
490 #power-domain-cells = <0>;
495 #power-domain-cells = <0>;
500 #power-domain-cells = <0>;
505 #power-domain-cells = <0>;
510 #address-cells = <1>;
512 #power-domain-cells = <0>;
516 #power-domain-cells = <0>;
521 #power-domain-cells = <0>;
527 #address-cells = <1>;
529 #power-domain-cells = <0>;
533 #address-cells = <1>;
535 #power-domain-cells = <0>;
539 #address-cells = <1>;
541 #power-domain-cells = <0>;
548 #address-cells = <1>;
550 #power-domain-cells = <0>;
554 #power-domain-cells = <0>;
559 #power-domain-cells = <0>;
564 #address-cells = <1>;
566 #power-domain-cells = <0>;
570 #power-domain-cells = <0>;
578 sh_fsi2: sound@ec230000 {
579 #sound-dai-cells = <1>;
580 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
581 reg = <0xec230000 0x400>;
582 interrupts = <GIC_SPI 146 0x4>;
583 power-domains = <&pd_a4mp>;
588 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
590 #address-cells = <1>;
592 ranges = <0 0 0x20000000>;
593 reg = <0xfec10000 0x400>;
594 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
596 power-domains = <&pd_a4s>;
600 #address-cells = <1>;
604 /* External root clocks */
606 compatible = "fixed-clock";
608 clock-frequency = <32768>;
611 compatible = "fixed-clock";
613 clock-frequency = <26000000>;
616 compatible = "fixed-clock";
620 compatible = "fixed-clock";
624 compatible = "fixed-clock";
626 clock-frequency = <0>;
629 compatible = "fixed-clock";
631 clock-frequency = <0>;
634 /* Special CPG clocks */
635 cpg_clocks: cpg_clocks@e6150000 {
636 compatible = "renesas,sh73a0-cpg-clocks";
637 reg = <0xe6150000 0x10000>;
638 clocks = <&extal1_clk>, <&extal2_clk>;
640 clock-output-names = "main", "pll0", "pll1", "pll2",
641 "pll3", "dsi0phy", "dsi1phy",
642 "zg", "m3", "b", "m1", "m2",
646 /* Variable factor clocks (DIV6) */
647 vclk1_clk: vclk1@e6150008 {
648 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
649 reg = <0xe6150008 4>;
650 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
651 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
652 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
656 vclk2_clk: vclk2@e615000c {
657 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
658 reg = <0xe615000c 4>;
659 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
660 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
661 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
665 vclk3_clk: vclk3@e615001c {
666 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
667 reg = <0xe615001c 4>;
668 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
669 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
670 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
674 zb_clk: zb_clk@e6150010 {
675 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
676 reg = <0xe6150010 4>;
677 clocks = <&pll1_div2_clk>, <0>,
678 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
680 clock-output-names = "zb";
682 flctl_clk: flctlck@e6150014 {
683 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
684 reg = <0xe6150014 4>;
685 clocks = <&pll1_div2_clk>, <0>,
686 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
689 sdhi0_clk: sdhi0ck@e6150074 {
690 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
691 reg = <0xe6150074 4>;
692 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
693 <&pll1_div13_clk>, <0>;
696 sdhi1_clk: sdhi1ck@e6150078 {
697 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
698 reg = <0xe6150078 4>;
699 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
700 <&pll1_div13_clk>, <0>;
703 sdhi2_clk: sdhi2ck@e615007c {
704 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
705 reg = <0xe615007c 4>;
706 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
707 <&pll1_div13_clk>, <0>;
710 fsia_clk: fsia@e6150018 {
711 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
712 reg = <0xe6150018 4>;
713 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
714 <&fsiack_clk>, <&fsiack_clk>;
717 fsib_clk: fsib@e6150090 {
718 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
719 reg = <0xe6150090 4>;
720 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
721 <&fsibck_clk>, <&fsibck_clk>;
724 sub_clk: sub@e6150080 {
725 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
726 reg = <0xe6150080 4>;
727 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
728 <&extal2_clk>, <&extal2_clk>;
731 spua_clk: spua@e6150084 {
732 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
733 reg = <0xe6150084 4>;
734 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
735 <&extal2_clk>, <&extal2_clk>;
738 spuv_clk: spuv@e6150094 {
739 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
740 reg = <0xe6150094 4>;
741 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
742 <&extal2_clk>, <&extal2_clk>;
745 msu_clk: msu@e6150088 {
746 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
747 reg = <0xe6150088 4>;
748 clocks = <&pll1_div2_clk>, <0>,
749 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
752 hsi_clk: hsi@e615008c {
753 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
754 reg = <0xe615008c 4>;
755 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
756 <&pll1_div7_clk>, <0>;
759 mfg1_clk: mfg1@e6150098 {
760 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
761 reg = <0xe6150098 4>;
762 clocks = <&pll1_div2_clk>, <0>,
763 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
766 mfg2_clk: mfg2@e615009c {
767 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
768 reg = <0xe615009c 4>;
769 clocks = <&pll1_div2_clk>, <0>,
770 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
773 dsit_clk: dsit@e6150060 {
774 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
775 reg = <0xe6150060 4>;
776 clocks = <&pll1_div2_clk>, <0>,
777 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
780 dsi0p_clk: dsi0pck@e6150064 {
781 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
782 reg = <0xe6150064 4>;
783 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
784 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
785 <&extcki_clk>, <0>, <0>, <0>;
789 /* Fixed factor clocks */
790 main_div2_clk: main_div2 {
791 compatible = "fixed-factor-clock";
792 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
797 pll1_div2_clk: pll1_div2 {
798 compatible = "fixed-factor-clock";
799 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
804 pll1_div7_clk: pll1_div7 {
805 compatible = "fixed-factor-clock";
806 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
811 pll1_div13_clk: pll1_div13 {
812 compatible = "fixed-factor-clock";
813 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
819 compatible = "fixed-factor-clock";
820 clocks = <&cpg_clocks SH73A0_CLK_Z>;
827 mstp0_clks: mstp0_clks@e6150130 {
828 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
829 reg = <0xe6150130 4>, <0xe6150030 4>;
830 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
833 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
838 mstp1_clks: mstp1_clks@e6150134 {
839 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
840 reg = <0xe6150134 4>, <0xe6150038 4>;
841 clocks = <&cpg_clocks SH73A0_CLK_B>,
842 <&cpg_clocks SH73A0_CLK_B>,
843 <&cpg_clocks SH73A0_CLK_B>,
844 <&cpg_clocks SH73A0_CLK_B>,
845 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
846 <&cpg_clocks SH73A0_CLK_HP>,
847 <&cpg_clocks SH73A0_CLK_ZG>,
848 <&cpg_clocks SH73A0_CLK_B>;
851 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
852 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
853 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
854 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
858 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
859 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
861 mstp2_clks: mstp2_clks@e6150138 {
862 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
863 reg = <0xe6150138 4>, <0xe6150040 4>;
864 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
865 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
866 <&sub_clk>, <&sub_clk>, <&sub_clk>,
867 <&sub_clk>, <&sub_clk>, <&sub_clk>,
868 <&sub_clk>, <&sub_clk>, <&sub_clk>;
871 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
872 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
873 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
874 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
875 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
876 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
880 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
881 "msiof1", "scifa5", "scifb", "msiof2",
882 "scifa0", "scifa1", "scifa2", "scifa3",
885 mstp3_clks: mstp3_clks@e615013c {
886 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
887 reg = <0xe615013c 4>, <0xe6150048 4>;
888 clocks = <&sub_clk>, <&extalr_clk>,
889 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
890 <&cpg_clocks SH73A0_CLK_HP>,
891 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
892 <&sdhi0_clk>, <&sdhi1_clk>,
893 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
894 <&main_div2_clk>, <&main_div2_clk>,
895 <&main_div2_clk>, <&main_div2_clk>,
899 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
900 SH73A0_CLK_FSI SH73A0_CLK_IRDA
901 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
902 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
903 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
904 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
905 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
909 "scifa6", "cmt1", "fsi", "irda", "iic1",
910 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
911 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
913 mstp4_clks: mstp4_clks@e6150140 {
914 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
915 reg = <0xe6150140 4>, <0xe615004c 4>;
916 clocks = <&cpg_clocks SH73A0_CLK_HP>,
917 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
920 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
924 "iic3", "iic4", "keysc";
926 mstp5_clks: mstp5_clks@e6150144 {
927 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
928 reg = <0xe6150144 4>, <0xe615003c 4>;
929 clocks = <&cpg_clocks SH73A0_CLK_HP>;