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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux...
[deliverable/linux.git] / arch / arm / boot / dts / socfpga.dtsi
1 /*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include "skeleton.dtsi"
19 #include <dt-bindings/reset/altr,rst-mgr.h>
20
21 / {
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 aliases {
26 ethernet0 = &gmac0;
27 ethernet1 = &gmac1;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 timer0 = &timer0;
31 timer1 = &timer1;
32 timer2 = &timer2;
33 timer3 = &timer3;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0>;
44 next-level-cache = <&L2>;
45 };
46 cpu@1 {
47 compatible = "arm,cortex-a9";
48 device_type = "cpu";
49 reg = <1>;
50 next-level-cache = <&L2>;
51 };
52 };
53
54 intc: intc@fffed000 {
55 compatible = "arm,cortex-a9-gic";
56 #interrupt-cells = <3>;
57 interrupt-controller;
58 reg = <0xfffed000 0x1000>,
59 <0xfffec100 0x100>;
60 };
61
62 soc {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "simple-bus";
66 device_type = "soc";
67 interrupt-parent = <&intc>;
68 ranges;
69
70 amba {
71 compatible = "arm,amba-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges;
75
76 pdma: pdma@ffe01000 {
77 compatible = "arm,pl330", "arm,primecell";
78 reg = <0xffe01000 0x1000>;
79 interrupts = <0 104 4>,
80 <0 105 4>,
81 <0 106 4>,
82 <0 107 4>,
83 <0 108 4>,
84 <0 109 4>,
85 <0 110 4>,
86 <0 111 4>;
87 #dma-cells = <1>;
88 #dma-channels = <8>;
89 #dma-requests = <32>;
90 clocks = <&l4_main_clk>;
91 clock-names = "apb_pclk";
92 };
93 };
94
95 can0: can@ffc00000 {
96 compatible = "bosch,d_can";
97 reg = <0xffc00000 0x1000>;
98 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
99 clocks = <&can0_clk>;
100 status = "disabled";
101 };
102
103 can1: can@ffc01000 {
104 compatible = "bosch,d_can";
105 reg = <0xffc01000 0x1000>;
106 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
107 clocks = <&can1_clk>;
108 status = "disabled";
109 };
110
111 clkmgr@ffd04000 {
112 compatible = "altr,clk-mgr";
113 reg = <0xffd04000 0x1000>;
114
115 clocks {
116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 osc1: osc1 {
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
122 };
123
124 osc2: osc2 {
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 };
128
129 f2s_periph_ref_clk: f2s_periph_ref_clk {
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
132 };
133
134 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
135 #clock-cells = <0>;
136 compatible = "fixed-clock";
137 };
138
139 main_pll: main_pll {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 #clock-cells = <0>;
143 compatible = "altr,socfpga-pll-clock";
144 clocks = <&osc1>;
145 reg = <0x40>;
146
147 mpuclk: mpuclk {
148 #clock-cells = <0>;
149 compatible = "altr,socfpga-perip-clk";
150 clocks = <&main_pll>;
151 div-reg = <0xe0 0 9>;
152 reg = <0x48>;
153 };
154
155 mainclk: mainclk {
156 #clock-cells = <0>;
157 compatible = "altr,socfpga-perip-clk";
158 clocks = <&main_pll>;
159 div-reg = <0xe4 0 9>;
160 reg = <0x4C>;
161 };
162
163 dbg_base_clk: dbg_base_clk {
164 #clock-cells = <0>;
165 compatible = "altr,socfpga-perip-clk";
166 clocks = <&main_pll>;
167 div-reg = <0xe8 0 9>;
168 reg = <0x50>;
169 };
170
171 main_qspi_clk: main_qspi_clk {
172 #clock-cells = <0>;
173 compatible = "altr,socfpga-perip-clk";
174 clocks = <&main_pll>;
175 reg = <0x54>;
176 };
177
178 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-perip-clk";
181 clocks = <&main_pll>;
182 reg = <0x58>;
183 };
184
185 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-perip-clk";
188 clocks = <&main_pll>;
189 reg = <0x5C>;
190 };
191 };
192
193 periph_pll: periph_pll {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 #clock-cells = <0>;
197 compatible = "altr,socfpga-pll-clock";
198 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
199 reg = <0x80>;
200
201 emac0_clk: emac0_clk {
202 #clock-cells = <0>;
203 compatible = "altr,socfpga-perip-clk";
204 clocks = <&periph_pll>;
205 reg = <0x88>;
206 };
207
208 emac1_clk: emac1_clk {
209 #clock-cells = <0>;
210 compatible = "altr,socfpga-perip-clk";
211 clocks = <&periph_pll>;
212 reg = <0x8C>;
213 };
214
215 per_qspi_clk: per_qsi_clk {
216 #clock-cells = <0>;
217 compatible = "altr,socfpga-perip-clk";
218 clocks = <&periph_pll>;
219 reg = <0x90>;
220 };
221
222 per_nand_mmc_clk: per_nand_mmc_clk {
223 #clock-cells = <0>;
224 compatible = "altr,socfpga-perip-clk";
225 clocks = <&periph_pll>;
226 reg = <0x94>;
227 };
228
229 per_base_clk: per_base_clk {
230 #clock-cells = <0>;
231 compatible = "altr,socfpga-perip-clk";
232 clocks = <&periph_pll>;
233 reg = <0x98>;
234 };
235
236 h2f_usr1_clk: h2f_usr1_clk {
237 #clock-cells = <0>;
238 compatible = "altr,socfpga-perip-clk";
239 clocks = <&periph_pll>;
240 reg = <0x9C>;
241 };
242 };
243
244 sdram_pll: sdram_pll {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 #clock-cells = <0>;
248 compatible = "altr,socfpga-pll-clock";
249 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
250 reg = <0xC0>;
251
252 ddr_dqs_clk: ddr_dqs_clk {
253 #clock-cells = <0>;
254 compatible = "altr,socfpga-perip-clk";
255 clocks = <&sdram_pll>;
256 reg = <0xC8>;
257 };
258
259 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
260 #clock-cells = <0>;
261 compatible = "altr,socfpga-perip-clk";
262 clocks = <&sdram_pll>;
263 reg = <0xCC>;
264 };
265
266 ddr_dq_clk: ddr_dq_clk {
267 #clock-cells = <0>;
268 compatible = "altr,socfpga-perip-clk";
269 clocks = <&sdram_pll>;
270 reg = <0xD0>;
271 };
272
273 h2f_usr2_clk: h2f_usr2_clk {
274 #clock-cells = <0>;
275 compatible = "altr,socfpga-perip-clk";
276 clocks = <&sdram_pll>;
277 reg = <0xD4>;
278 };
279 };
280
281 mpu_periph_clk: mpu_periph_clk {
282 #clock-cells = <0>;
283 compatible = "altr,socfpga-perip-clk";
284 clocks = <&mpuclk>;
285 fixed-divider = <4>;
286 };
287
288 mpu_l2_ram_clk: mpu_l2_ram_clk {
289 #clock-cells = <0>;
290 compatible = "altr,socfpga-perip-clk";
291 clocks = <&mpuclk>;
292 fixed-divider = <2>;
293 };
294
295 l4_main_clk: l4_main_clk {
296 #clock-cells = <0>;
297 compatible = "altr,socfpga-gate-clk";
298 clocks = <&mainclk>;
299 clk-gate = <0x60 0>;
300 };
301
302 l3_main_clk: l3_main_clk {
303 #clock-cells = <0>;
304 compatible = "altr,socfpga-perip-clk";
305 clocks = <&mainclk>;
306 fixed-divider = <1>;
307 };
308
309 l3_mp_clk: l3_mp_clk {
310 #clock-cells = <0>;
311 compatible = "altr,socfpga-gate-clk";
312 clocks = <&mainclk>;
313 div-reg = <0x64 0 2>;
314 clk-gate = <0x60 1>;
315 };
316
317 l3_sp_clk: l3_sp_clk {
318 #clock-cells = <0>;
319 compatible = "altr,socfpga-gate-clk";
320 clocks = <&mainclk>;
321 div-reg = <0x64 2 2>;
322 };
323
324 l4_mp_clk: l4_mp_clk {
325 #clock-cells = <0>;
326 compatible = "altr,socfpga-gate-clk";
327 clocks = <&mainclk>, <&per_base_clk>;
328 div-reg = <0x64 4 3>;
329 clk-gate = <0x60 2>;
330 };
331
332 l4_sp_clk: l4_sp_clk {
333 #clock-cells = <0>;
334 compatible = "altr,socfpga-gate-clk";
335 clocks = <&mainclk>, <&per_base_clk>;
336 div-reg = <0x64 7 3>;
337 clk-gate = <0x60 3>;
338 };
339
340 dbg_at_clk: dbg_at_clk {
341 #clock-cells = <0>;
342 compatible = "altr,socfpga-gate-clk";
343 clocks = <&dbg_base_clk>;
344 div-reg = <0x68 0 2>;
345 clk-gate = <0x60 4>;
346 };
347
348 dbg_clk: dbg_clk {
349 #clock-cells = <0>;
350 compatible = "altr,socfpga-gate-clk";
351 clocks = <&dbg_base_clk>;
352 div-reg = <0x68 2 2>;
353 clk-gate = <0x60 5>;
354 };
355
356 dbg_trace_clk: dbg_trace_clk {
357 #clock-cells = <0>;
358 compatible = "altr,socfpga-gate-clk";
359 clocks = <&dbg_base_clk>;
360 div-reg = <0x6C 0 3>;
361 clk-gate = <0x60 6>;
362 };
363
364 dbg_timer_clk: dbg_timer_clk {
365 #clock-cells = <0>;
366 compatible = "altr,socfpga-gate-clk";
367 clocks = <&dbg_base_clk>;
368 clk-gate = <0x60 7>;
369 };
370
371 cfg_clk: cfg_clk {
372 #clock-cells = <0>;
373 compatible = "altr,socfpga-gate-clk";
374 clocks = <&cfg_h2f_usr0_clk>;
375 clk-gate = <0x60 8>;
376 };
377
378 h2f_user0_clk: h2f_user0_clk {
379 #clock-cells = <0>;
380 compatible = "altr,socfpga-gate-clk";
381 clocks = <&cfg_h2f_usr0_clk>;
382 clk-gate = <0x60 9>;
383 };
384
385 emac_0_clk: emac_0_clk {
386 #clock-cells = <0>;
387 compatible = "altr,socfpga-gate-clk";
388 clocks = <&emac0_clk>;
389 clk-gate = <0xa0 0>;
390 };
391
392 emac_1_clk: emac_1_clk {
393 #clock-cells = <0>;
394 compatible = "altr,socfpga-gate-clk";
395 clocks = <&emac1_clk>;
396 clk-gate = <0xa0 1>;
397 };
398
399 usb_mp_clk: usb_mp_clk {
400 #clock-cells = <0>;
401 compatible = "altr,socfpga-gate-clk";
402 clocks = <&per_base_clk>;
403 clk-gate = <0xa0 2>;
404 div-reg = <0xa4 0 3>;
405 };
406
407 spi_m_clk: spi_m_clk {
408 #clock-cells = <0>;
409 compatible = "altr,socfpga-gate-clk";
410 clocks = <&per_base_clk>;
411 clk-gate = <0xa0 3>;
412 div-reg = <0xa4 3 3>;
413 };
414
415 can0_clk: can0_clk {
416 #clock-cells = <0>;
417 compatible = "altr,socfpga-gate-clk";
418 clocks = <&per_base_clk>;
419 clk-gate = <0xa0 4>;
420 div-reg = <0xa4 6 3>;
421 };
422
423 can1_clk: can1_clk {
424 #clock-cells = <0>;
425 compatible = "altr,socfpga-gate-clk";
426 clocks = <&per_base_clk>;
427 clk-gate = <0xa0 5>;
428 div-reg = <0xa4 9 3>;
429 };
430
431 gpio_db_clk: gpio_db_clk {
432 #clock-cells = <0>;
433 compatible = "altr,socfpga-gate-clk";
434 clocks = <&per_base_clk>;
435 clk-gate = <0xa0 6>;
436 div-reg = <0xa8 0 24>;
437 };
438
439 h2f_user1_clk: h2f_user1_clk {
440 #clock-cells = <0>;
441 compatible = "altr,socfpga-gate-clk";
442 clocks = <&h2f_usr1_clk>;
443 clk-gate = <0xa0 7>;
444 };
445
446 sdmmc_clk: sdmmc_clk {
447 #clock-cells = <0>;
448 compatible = "altr,socfpga-gate-clk";
449 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
450 clk-gate = <0xa0 8>;
451 clk-phase = <0 135>;
452 };
453
454 nand_x_clk: nand_x_clk {
455 #clock-cells = <0>;
456 compatible = "altr,socfpga-gate-clk";
457 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
458 clk-gate = <0xa0 9>;
459 };
460
461 nand_clk: nand_clk {
462 #clock-cells = <0>;
463 compatible = "altr,socfpga-gate-clk";
464 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
465 clk-gate = <0xa0 10>;
466 fixed-divider = <4>;
467 };
468
469 qspi_clk: qspi_clk {
470 #clock-cells = <0>;
471 compatible = "altr,socfpga-gate-clk";
472 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
473 clk-gate = <0xa0 11>;
474 };
475 };
476 };
477
478 gmac0: ethernet@ff700000 {
479 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
480 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
481 reg = <0xff700000 0x2000>;
482 interrupts = <0 115 4>;
483 interrupt-names = "macirq";
484 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
485 clocks = <&emac0_clk>;
486 clock-names = "stmmaceth";
487 resets = <&rst EMAC0_RESET>;
488 reset-names = "stmmaceth";
489 status = "disabled";
490 };
491
492 gmac1: ethernet@ff702000 {
493 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
494 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
495 reg = <0xff702000 0x2000>;
496 interrupts = <0 120 4>;
497 interrupt-names = "macirq";
498 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
499 clocks = <&emac1_clk>;
500 clock-names = "stmmaceth";
501 resets = <&rst EMAC1_RESET>;
502 reset-names = "stmmaceth";
503 status = "disabled";
504 };
505
506 i2c0: i2c@ffc04000 {
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "snps,designware-i2c";
510 reg = <0xffc04000 0x1000>;
511 clocks = <&l4_sp_clk>;
512 interrupts = <0 158 0x4>;
513 status = "disabled";
514 };
515
516 i2c1: i2c@ffc05000 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 compatible = "snps,designware-i2c";
520 reg = <0xffc05000 0x1000>;
521 clocks = <&l4_sp_clk>;
522 interrupts = <0 159 0x4>;
523 status = "disabled";
524 };
525
526 i2c2: i2c@ffc06000 {
527 #address-cells = <1>;
528 #size-cells = <0>;
529 compatible = "snps,designware-i2c";
530 reg = <0xffc06000 0x1000>;
531 clocks = <&l4_sp_clk>;
532 interrupts = <0 160 0x4>;
533 status = "disabled";
534 };
535
536 i2c3: i2c@ffc07000 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 compatible = "snps,designware-i2c";
540 reg = <0xffc07000 0x1000>;
541 clocks = <&l4_sp_clk>;
542 interrupts = <0 161 0x4>;
543 status = "disabled";
544 };
545
546 gpio@ff708000 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 compatible = "snps,dw-apb-gpio";
550 reg = <0xff708000 0x1000>;
551 clocks = <&per_base_clk>;
552 status = "disabled";
553
554 gpio0: gpio-controller@0 {
555 compatible = "snps,dw-apb-gpio-port";
556 gpio-controller;
557 #gpio-cells = <2>;
558 snps,nr-gpios = <29>;
559 reg = <0>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
562 interrupts = <0 164 4>;
563 };
564 };
565
566 gpio@ff709000 {
567 #address-cells = <1>;
568 #size-cells = <0>;
569 compatible = "snps,dw-apb-gpio";
570 reg = <0xff709000 0x1000>;
571 clocks = <&per_base_clk>;
572 status = "disabled";
573
574 gpio1: gpio-controller@0 {
575 compatible = "snps,dw-apb-gpio-port";
576 gpio-controller;
577 #gpio-cells = <2>;
578 snps,nr-gpios = <29>;
579 reg = <0>;
580 interrupt-controller;
581 #interrupt-cells = <2>;
582 interrupts = <0 165 4>;
583 };
584 };
585
586 gpio@ff70a000 {
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "snps,dw-apb-gpio";
590 reg = <0xff70a000 0x1000>;
591 clocks = <&per_base_clk>;
592 status = "disabled";
593
594 gpio2: gpio-controller@0 {
595 compatible = "snps,dw-apb-gpio-port";
596 gpio-controller;
597 #gpio-cells = <2>;
598 snps,nr-gpios = <27>;
599 reg = <0>;
600 interrupt-controller;
601 #interrupt-cells = <2>;
602 interrupts = <0 166 4>;
603 };
604 };
605
606 L2: l2-cache@fffef000 {
607 compatible = "arm,pl310-cache";
608 reg = <0xfffef000 0x1000>;
609 interrupts = <0 38 0x04>;
610 cache-unified;
611 cache-level = <2>;
612 arm,tag-latency = <1 1 1>;
613 arm,data-latency = <2 1 1>;
614 };
615
616 mmc: dwmmc0@ff704000 {
617 compatible = "altr,socfpga-dw-mshc";
618 reg = <0xff704000 0x1000>;
619 interrupts = <0 139 4>;
620 fifo-depth = <0x400>;
621 #address-cells = <1>;
622 #size-cells = <0>;
623 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
624 clock-names = "biu", "ciu";
625 };
626
627 /* Local timer */
628 timer@fffec600 {
629 compatible = "arm,cortex-a9-twd-timer";
630 reg = <0xfffec600 0x100>;
631 interrupts = <1 13 0xf04>;
632 clocks = <&mpu_periph_clk>;
633 };
634
635 timer0: timer0@ffc08000 {
636 compatible = "snps,dw-apb-timer";
637 interrupts = <0 167 4>;
638 reg = <0xffc08000 0x1000>;
639 clocks = <&l4_sp_clk>;
640 clock-names = "timer";
641 };
642
643 timer1: timer1@ffc09000 {
644 compatible = "snps,dw-apb-timer";
645 interrupts = <0 168 4>;
646 reg = <0xffc09000 0x1000>;
647 clocks = <&l4_sp_clk>;
648 clock-names = "timer";
649 };
650
651 timer2: timer2@ffd00000 {
652 compatible = "snps,dw-apb-timer";
653 interrupts = <0 169 4>;
654 reg = <0xffd00000 0x1000>;
655 clocks = <&osc1>;
656 clock-names = "timer";
657 };
658
659 timer3: timer3@ffd01000 {
660 compatible = "snps,dw-apb-timer";
661 interrupts = <0 170 4>;
662 reg = <0xffd01000 0x1000>;
663 clocks = <&osc1>;
664 clock-names = "timer";
665 };
666
667 uart0: serial0@ffc02000 {
668 compatible = "snps,dw-apb-uart";
669 reg = <0xffc02000 0x1000>;
670 interrupts = <0 162 4>;
671 reg-shift = <2>;
672 reg-io-width = <4>;
673 clocks = <&l4_sp_clk>;
674 };
675
676 uart1: serial1@ffc03000 {
677 compatible = "snps,dw-apb-uart";
678 reg = <0xffc03000 0x1000>;
679 interrupts = <0 163 4>;
680 reg-shift = <2>;
681 reg-io-width = <4>;
682 clocks = <&l4_sp_clk>;
683 };
684
685 rst: rstmgr@ffd05000 {
686 compatible = "altr,rst-mgr";
687 reg = <0xffd05000 0x1000>;
688 };
689
690 usbphy0: usbphy@0 {
691 #phy-cells = <0>;
692 compatible = "usb-nop-xceiv";
693 status = "okay";
694 };
695
696 usb0: usb@ffb00000 {
697 compatible = "snps,dwc2";
698 reg = <0xffb00000 0xffff>;
699 interrupts = <0 125 4>;
700 clocks = <&usb_mp_clk>;
701 clock-names = "otg";
702 phys = <&usbphy0>;
703 phy-names = "usb2-phy";
704 status = "disabled";
705 };
706
707 usb1: usb@ffb40000 {
708 compatible = "snps,dwc2";
709 reg = <0xffb40000 0xffff>;
710 interrupts = <0 128 4>;
711 clocks = <&usb_mp_clk>;
712 clock-names = "otg";
713 phys = <&usbphy0>;
714 phy-names = "usb2-phy";
715 status = "disabled";
716 };
717
718 watchdog0: watchdog@ffd02000 {
719 compatible = "snps,dw-wdt";
720 reg = <0xffd02000 0x1000>;
721 interrupts = <0 171 4>;
722 clocks = <&osc1>;
723 status = "disabled";
724 };
725
726 watchdog1: watchdog@ffd03000 {
727 compatible = "snps,dw-wdt";
728 reg = <0xffd03000 0x1000>;
729 interrupts = <0 172 4>;
730 clocks = <&osc1>;
731 status = "disabled";
732 };
733
734 sysmgr: sysmgr@ffd08000 {
735 compatible = "altr,sys-mgr", "syscon";
736 reg = <0xffd08000 0x4000>;
737 };
738 };
739 };
Linux kernel - Deliverables
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