2 * Copyright (C) 2012 Altera <www.altera.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 /include/ "skeleton.dtsi"
40 compatible = "arm,cortex-a9";
43 next-level-cache = <&L2>;
46 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
57 reg = <0xfffed000 0x1000>,
64 compatible = "simple-bus";
66 interrupt-parent = <&intc>;
70 compatible = "arm,amba-bus";
76 compatible = "arm,pl330", "arm,primecell";
77 reg = <0xffe01000 0x1000>;
78 interrupts = <0 104 4>,
89 clocks = <&l4_main_clk>;
90 clock-names = "apb_pclk";
95 compatible = "altr,clk-mgr";
96 reg = <0xffd04000 0x1000>;
104 compatible = "fixed-clock";
109 compatible = "fixed-clock";
112 f2s_periph_ref_clk: f2s_periph_ref_clk {
114 compatible = "fixed-clock";
117 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
119 compatible = "fixed-clock";
123 #address-cells = <1>;
126 compatible = "altr,socfpga-pll-clock";
132 compatible = "altr,socfpga-perip-clk";
133 clocks = <&main_pll>;
140 compatible = "altr,socfpga-perip-clk";
141 clocks = <&main_pll>;
146 dbg_base_clk: dbg_base_clk {
148 compatible = "altr,socfpga-perip-clk";
149 clocks = <&main_pll>;
154 main_qspi_clk: main_qspi_clk {
156 compatible = "altr,socfpga-perip-clk";
157 clocks = <&main_pll>;
161 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
163 compatible = "altr,socfpga-perip-clk";
164 clocks = <&main_pll>;
168 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
170 compatible = "altr,socfpga-perip-clk";
171 clocks = <&main_pll>;
176 periph_pll: periph_pll {
177 #address-cells = <1>;
180 compatible = "altr,socfpga-pll-clock";
181 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
184 emac0_clk: emac0_clk {
186 compatible = "altr,socfpga-perip-clk";
187 clocks = <&periph_pll>;
191 emac1_clk: emac1_clk {
193 compatible = "altr,socfpga-perip-clk";
194 clocks = <&periph_pll>;
198 per_qspi_clk: per_qsi_clk {
200 compatible = "altr,socfpga-perip-clk";
201 clocks = <&periph_pll>;
205 per_nand_mmc_clk: per_nand_mmc_clk {
207 compatible = "altr,socfpga-perip-clk";
208 clocks = <&periph_pll>;
212 per_base_clk: per_base_clk {
214 compatible = "altr,socfpga-perip-clk";
215 clocks = <&periph_pll>;
219 h2f_usr1_clk: h2f_usr1_clk {
221 compatible = "altr,socfpga-perip-clk";
222 clocks = <&periph_pll>;
227 sdram_pll: sdram_pll {
228 #address-cells = <1>;
231 compatible = "altr,socfpga-pll-clock";
232 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
235 ddr_dqs_clk: ddr_dqs_clk {
237 compatible = "altr,socfpga-perip-clk";
238 clocks = <&sdram_pll>;
242 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
244 compatible = "altr,socfpga-perip-clk";
245 clocks = <&sdram_pll>;
249 ddr_dq_clk: ddr_dq_clk {
251 compatible = "altr,socfpga-perip-clk";
252 clocks = <&sdram_pll>;
256 h2f_usr2_clk: h2f_usr2_clk {
258 compatible = "altr,socfpga-perip-clk";
259 clocks = <&sdram_pll>;
264 mpu_periph_clk: mpu_periph_clk {
266 compatible = "altr,socfpga-perip-clk";
271 mpu_l2_ram_clk: mpu_l2_ram_clk {
273 compatible = "altr,socfpga-perip-clk";
278 l4_main_clk: l4_main_clk {
280 compatible = "altr,socfpga-gate-clk";
285 l3_main_clk: l3_main_clk {
287 compatible = "altr,socfpga-perip-clk";
292 l3_mp_clk: l3_mp_clk {
294 compatible = "altr,socfpga-gate-clk";
296 div-reg = <0x64 0 2>;
300 l3_sp_clk: l3_sp_clk {
302 compatible = "altr,socfpga-gate-clk";
304 div-reg = <0x64 2 2>;
307 l4_mp_clk: l4_mp_clk {
309 compatible = "altr,socfpga-gate-clk";
310 clocks = <&mainclk>, <&per_base_clk>;
311 div-reg = <0x64 4 3>;
315 l4_sp_clk: l4_sp_clk {
317 compatible = "altr,socfpga-gate-clk";
318 clocks = <&mainclk>, <&per_base_clk>;
319 div-reg = <0x64 7 3>;
323 dbg_at_clk: dbg_at_clk {
325 compatible = "altr,socfpga-gate-clk";
326 clocks = <&dbg_base_clk>;
327 div-reg = <0x68 0 2>;
333 compatible = "altr,socfpga-gate-clk";
334 clocks = <&dbg_base_clk>;
335 div-reg = <0x68 2 2>;
339 dbg_trace_clk: dbg_trace_clk {
341 compatible = "altr,socfpga-gate-clk";
342 clocks = <&dbg_base_clk>;
343 div-reg = <0x6C 0 3>;
347 dbg_timer_clk: dbg_timer_clk {
349 compatible = "altr,socfpga-gate-clk";
350 clocks = <&dbg_base_clk>;
356 compatible = "altr,socfpga-gate-clk";
357 clocks = <&cfg_h2f_usr0_clk>;
361 h2f_user0_clk: h2f_user0_clk {
363 compatible = "altr,socfpga-gate-clk";
364 clocks = <&cfg_h2f_usr0_clk>;
368 emac_0_clk: emac_0_clk {
370 compatible = "altr,socfpga-gate-clk";
371 clocks = <&emac0_clk>;
375 emac_1_clk: emac_1_clk {
377 compatible = "altr,socfpga-gate-clk";
378 clocks = <&emac1_clk>;
382 usb_mp_clk: usb_mp_clk {
384 compatible = "altr,socfpga-gate-clk";
385 clocks = <&per_base_clk>;
387 div-reg = <0xa4 0 3>;
390 spi_m_clk: spi_m_clk {
392 compatible = "altr,socfpga-gate-clk";
393 clocks = <&per_base_clk>;
395 div-reg = <0xa4 3 3>;
400 compatible = "altr,socfpga-gate-clk";
401 clocks = <&per_base_clk>;
403 div-reg = <0xa4 6 3>;
408 compatible = "altr,socfpga-gate-clk";
409 clocks = <&per_base_clk>;
411 div-reg = <0xa4 9 3>;
414 gpio_db_clk: gpio_db_clk {
416 compatible = "altr,socfpga-gate-clk";
417 clocks = <&per_base_clk>;
419 div-reg = <0xa8 0 24>;
422 h2f_user1_clk: h2f_user1_clk {
424 compatible = "altr,socfpga-gate-clk";
425 clocks = <&h2f_usr1_clk>;
429 sdmmc_clk: sdmmc_clk {
431 compatible = "altr,socfpga-gate-clk";
432 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
437 nand_x_clk: nand_x_clk {
439 compatible = "altr,socfpga-gate-clk";
440 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
446 compatible = "altr,socfpga-gate-clk";
447 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
448 clk-gate = <0xa0 10>;
454 compatible = "altr,socfpga-gate-clk";
455 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
456 clk-gate = <0xa0 11>;
461 gmac0: ethernet@ff700000 {
462 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
463 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
464 reg = <0xff700000 0x2000>;
465 interrupts = <0 115 4>;
466 interrupt-names = "macirq";
467 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
468 clocks = <&emac0_clk>;
469 clock-names = "stmmaceth";
473 gmac1: ethernet@ff702000 {
474 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
475 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
476 reg = <0xff702000 0x2000>;
477 interrupts = <0 120 4>;
478 interrupt-names = "macirq";
479 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
480 clocks = <&emac1_clk>;
481 clock-names = "stmmaceth";
485 L2: l2-cache@fffef000 {
486 compatible = "arm,pl310-cache";
487 reg = <0xfffef000 0x1000>;
488 interrupts = <0 38 0x04>;
491 arm,tag-latency = <1 1 1>;
492 arm,data-latency = <2 1 1>;
495 mmc: dwmmc0@ff704000 {
496 compatible = "altr,socfpga-dw-mshc";
497 reg = <0xff704000 0x1000>;
498 interrupts = <0 139 4>;
499 fifo-depth = <0x400>;
500 #address-cells = <1>;
502 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
503 clock-names = "biu", "ciu";
508 compatible = "arm,cortex-a9-twd-timer";
509 reg = <0xfffec600 0x100>;
510 interrupts = <1 13 0xf04>;
511 clocks = <&mpu_periph_clk>;
514 timer0: timer0@ffc08000 {
515 compatible = "snps,dw-apb-timer";
516 interrupts = <0 167 4>;
517 reg = <0xffc08000 0x1000>;
520 timer1: timer1@ffc09000 {
521 compatible = "snps,dw-apb-timer";
522 interrupts = <0 168 4>;
523 reg = <0xffc09000 0x1000>;
526 timer2: timer2@ffd00000 {
527 compatible = "snps,dw-apb-timer";
528 interrupts = <0 169 4>;
529 reg = <0xffd00000 0x1000>;
532 timer3: timer3@ffd01000 {
533 compatible = "snps,dw-apb-timer";
534 interrupts = <0 170 4>;
535 reg = <0xffd01000 0x1000>;
538 uart0: serial0@ffc02000 {
539 compatible = "snps,dw-apb-uart";
540 reg = <0xffc02000 0x1000>;
541 interrupts = <0 162 4>;
546 uart1: serial1@ffc03000 {
547 compatible = "snps,dw-apb-uart";
548 reg = <0xffc03000 0x1000>;
549 interrupts = <0 163 4>;
555 compatible = "altr,rst-mgr";
556 reg = <0xffd05000 0x1000>;
559 sysmgr: sysmgr@ffd08000 {
560 compatible = "altr,sys-mgr", "syscon";
561 reg = <0xffd08000 0x4000>;