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[deliverable/linux.git] / arch / arm / boot / dts / socfpga.dtsi
1 /*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 /include/ "skeleton.dtsi"
19
20 / {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
26 ethernet1 = &gmac1;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 timer0 = &timer0;
30 timer1 = &timer1;
31 timer2 = &timer2;
32 timer3 = &timer3;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 compatible = "arm,cortex-a9";
41 device_type = "cpu";
42 reg = <0>;
43 next-level-cache = <&L2>;
44 };
45 cpu@1 {
46 compatible = "arm,cortex-a9";
47 device_type = "cpu";
48 reg = <1>;
49 next-level-cache = <&L2>;
50 };
51 };
52
53 intc: intc@fffed000 {
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
56 interrupt-controller;
57 reg = <0xfffed000 0x1000>,
58 <0xfffec100 0x100>;
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 device_type = "soc";
66 interrupt-parent = <&intc>;
67 ranges;
68
69 amba {
70 compatible = "arm,amba-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges;
74
75 pdma: pdma@ffe01000 {
76 compatible = "arm,pl330", "arm,primecell";
77 reg = <0xffe01000 0x1000>;
78 interrupts = <0 104 4>,
79 <0 105 4>,
80 <0 106 4>,
81 <0 107 4>,
82 <0 108 4>,
83 <0 109 4>,
84 <0 110 4>,
85 <0 111 4>;
86 #dma-cells = <1>;
87 #dma-channels = <8>;
88 #dma-requests = <32>;
89 clocks = <&l4_main_clk>;
90 clock-names = "apb_pclk";
91 };
92 };
93
94 clkmgr@ffd04000 {
95 compatible = "altr,clk-mgr";
96 reg = <0xffd04000 0x1000>;
97
98 clocks {
99 #address-cells = <1>;
100 #size-cells = <0>;
101
102 osc1: osc1 {
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
105 };
106
107 osc2: osc2 {
108 #clock-cells = <0>;
109 compatible = "fixed-clock";
110 };
111
112 f2s_periph_ref_clk: f2s_periph_ref_clk {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 };
116
117 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
118 #clock-cells = <0>;
119 compatible = "fixed-clock";
120 };
121
122 main_pll: main_pll {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 #clock-cells = <0>;
126 compatible = "altr,socfpga-pll-clock";
127 clocks = <&osc1>;
128 reg = <0x40>;
129
130 mpuclk: mpuclk {
131 #clock-cells = <0>;
132 compatible = "altr,socfpga-perip-clk";
133 clocks = <&main_pll>;
134 fixed-divider = <2>;
135 reg = <0x48>;
136 };
137
138 mainclk: mainclk {
139 #clock-cells = <0>;
140 compatible = "altr,socfpga-perip-clk";
141 clocks = <&main_pll>;
142 fixed-divider = <4>;
143 reg = <0x4C>;
144 };
145
146 dbg_base_clk: dbg_base_clk {
147 #clock-cells = <0>;
148 compatible = "altr,socfpga-perip-clk";
149 clocks = <&main_pll>;
150 fixed-divider = <4>;
151 reg = <0x50>;
152 };
153
154 main_qspi_clk: main_qspi_clk {
155 #clock-cells = <0>;
156 compatible = "altr,socfpga-perip-clk";
157 clocks = <&main_pll>;
158 reg = <0x54>;
159 };
160
161 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
162 #clock-cells = <0>;
163 compatible = "altr,socfpga-perip-clk";
164 clocks = <&main_pll>;
165 reg = <0x58>;
166 };
167
168 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
169 #clock-cells = <0>;
170 compatible = "altr,socfpga-perip-clk";
171 clocks = <&main_pll>;
172 reg = <0x5C>;
173 };
174 };
175
176 periph_pll: periph_pll {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-pll-clock";
181 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
182 reg = <0x80>;
183
184 emac0_clk: emac0_clk {
185 #clock-cells = <0>;
186 compatible = "altr,socfpga-perip-clk";
187 clocks = <&periph_pll>;
188 reg = <0x88>;
189 };
190
191 emac1_clk: emac1_clk {
192 #clock-cells = <0>;
193 compatible = "altr,socfpga-perip-clk";
194 clocks = <&periph_pll>;
195 reg = <0x8C>;
196 };
197
198 per_qspi_clk: per_qsi_clk {
199 #clock-cells = <0>;
200 compatible = "altr,socfpga-perip-clk";
201 clocks = <&periph_pll>;
202 reg = <0x90>;
203 };
204
205 per_nand_mmc_clk: per_nand_mmc_clk {
206 #clock-cells = <0>;
207 compatible = "altr,socfpga-perip-clk";
208 clocks = <&periph_pll>;
209 reg = <0x94>;
210 };
211
212 per_base_clk: per_base_clk {
213 #clock-cells = <0>;
214 compatible = "altr,socfpga-perip-clk";
215 clocks = <&periph_pll>;
216 reg = <0x98>;
217 };
218
219 h2f_usr1_clk: h2f_usr1_clk {
220 #clock-cells = <0>;
221 compatible = "altr,socfpga-perip-clk";
222 clocks = <&periph_pll>;
223 reg = <0x9C>;
224 };
225 };
226
227 sdram_pll: sdram_pll {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 #clock-cells = <0>;
231 compatible = "altr,socfpga-pll-clock";
232 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
233 reg = <0xC0>;
234
235 ddr_dqs_clk: ddr_dqs_clk {
236 #clock-cells = <0>;
237 compatible = "altr,socfpga-perip-clk";
238 clocks = <&sdram_pll>;
239 reg = <0xC8>;
240 };
241
242 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
243 #clock-cells = <0>;
244 compatible = "altr,socfpga-perip-clk";
245 clocks = <&sdram_pll>;
246 reg = <0xCC>;
247 };
248
249 ddr_dq_clk: ddr_dq_clk {
250 #clock-cells = <0>;
251 compatible = "altr,socfpga-perip-clk";
252 clocks = <&sdram_pll>;
253 reg = <0xD0>;
254 };
255
256 h2f_usr2_clk: h2f_usr2_clk {
257 #clock-cells = <0>;
258 compatible = "altr,socfpga-perip-clk";
259 clocks = <&sdram_pll>;
260 reg = <0xD4>;
261 };
262 };
263
264 mpu_periph_clk: mpu_periph_clk {
265 #clock-cells = <0>;
266 compatible = "altr,socfpga-perip-clk";
267 clocks = <&mpuclk>;
268 fixed-divider = <4>;
269 };
270
271 mpu_l2_ram_clk: mpu_l2_ram_clk {
272 #clock-cells = <0>;
273 compatible = "altr,socfpga-perip-clk";
274 clocks = <&mpuclk>;
275 fixed-divider = <2>;
276 };
277
278 l4_main_clk: l4_main_clk {
279 #clock-cells = <0>;
280 compatible = "altr,socfpga-gate-clk";
281 clocks = <&mainclk>;
282 clk-gate = <0x60 0>;
283 };
284
285 l3_main_clk: l3_main_clk {
286 #clock-cells = <0>;
287 compatible = "altr,socfpga-perip-clk";
288 clocks = <&mainclk>;
289 fixed-divider = <1>;
290 };
291
292 l3_mp_clk: l3_mp_clk {
293 #clock-cells = <0>;
294 compatible = "altr,socfpga-gate-clk";
295 clocks = <&mainclk>;
296 div-reg = <0x64 0 2>;
297 clk-gate = <0x60 1>;
298 };
299
300 l3_sp_clk: l3_sp_clk {
301 #clock-cells = <0>;
302 compatible = "altr,socfpga-gate-clk";
303 clocks = <&mainclk>;
304 div-reg = <0x64 2 2>;
305 };
306
307 l4_mp_clk: l4_mp_clk {
308 #clock-cells = <0>;
309 compatible = "altr,socfpga-gate-clk";
310 clocks = <&mainclk>, <&per_base_clk>;
311 div-reg = <0x64 4 3>;
312 clk-gate = <0x60 2>;
313 };
314
315 l4_sp_clk: l4_sp_clk {
316 #clock-cells = <0>;
317 compatible = "altr,socfpga-gate-clk";
318 clocks = <&mainclk>, <&per_base_clk>;
319 div-reg = <0x64 7 3>;
320 clk-gate = <0x60 3>;
321 };
322
323 dbg_at_clk: dbg_at_clk {
324 #clock-cells = <0>;
325 compatible = "altr,socfpga-gate-clk";
326 clocks = <&dbg_base_clk>;
327 div-reg = <0x68 0 2>;
328 clk-gate = <0x60 4>;
329 };
330
331 dbg_clk: dbg_clk {
332 #clock-cells = <0>;
333 compatible = "altr,socfpga-gate-clk";
334 clocks = <&dbg_base_clk>;
335 div-reg = <0x68 2 2>;
336 clk-gate = <0x60 5>;
337 };
338
339 dbg_trace_clk: dbg_trace_clk {
340 #clock-cells = <0>;
341 compatible = "altr,socfpga-gate-clk";
342 clocks = <&dbg_base_clk>;
343 div-reg = <0x6C 0 3>;
344 clk-gate = <0x60 6>;
345 };
346
347 dbg_timer_clk: dbg_timer_clk {
348 #clock-cells = <0>;
349 compatible = "altr,socfpga-gate-clk";
350 clocks = <&dbg_base_clk>;
351 clk-gate = <0x60 7>;
352 };
353
354 cfg_clk: cfg_clk {
355 #clock-cells = <0>;
356 compatible = "altr,socfpga-gate-clk";
357 clocks = <&cfg_h2f_usr0_clk>;
358 clk-gate = <0x60 8>;
359 };
360
361 h2f_user0_clk: h2f_user0_clk {
362 #clock-cells = <0>;
363 compatible = "altr,socfpga-gate-clk";
364 clocks = <&cfg_h2f_usr0_clk>;
365 clk-gate = <0x60 9>;
366 };
367
368 emac_0_clk: emac_0_clk {
369 #clock-cells = <0>;
370 compatible = "altr,socfpga-gate-clk";
371 clocks = <&emac0_clk>;
372 clk-gate = <0xa0 0>;
373 };
374
375 emac_1_clk: emac_1_clk {
376 #clock-cells = <0>;
377 compatible = "altr,socfpga-gate-clk";
378 clocks = <&emac1_clk>;
379 clk-gate = <0xa0 1>;
380 };
381
382 usb_mp_clk: usb_mp_clk {
383 #clock-cells = <0>;
384 compatible = "altr,socfpga-gate-clk";
385 clocks = <&per_base_clk>;
386 clk-gate = <0xa0 2>;
387 div-reg = <0xa4 0 3>;
388 };
389
390 spi_m_clk: spi_m_clk {
391 #clock-cells = <0>;
392 compatible = "altr,socfpga-gate-clk";
393 clocks = <&per_base_clk>;
394 clk-gate = <0xa0 3>;
395 div-reg = <0xa4 3 3>;
396 };
397
398 can0_clk: can0_clk {
399 #clock-cells = <0>;
400 compatible = "altr,socfpga-gate-clk";
401 clocks = <&per_base_clk>;
402 clk-gate = <0xa0 4>;
403 div-reg = <0xa4 6 3>;
404 };
405
406 can1_clk: can1_clk {
407 #clock-cells = <0>;
408 compatible = "altr,socfpga-gate-clk";
409 clocks = <&per_base_clk>;
410 clk-gate = <0xa0 5>;
411 div-reg = <0xa4 9 3>;
412 };
413
414 gpio_db_clk: gpio_db_clk {
415 #clock-cells = <0>;
416 compatible = "altr,socfpga-gate-clk";
417 clocks = <&per_base_clk>;
418 clk-gate = <0xa0 6>;
419 div-reg = <0xa8 0 24>;
420 };
421
422 h2f_user1_clk: h2f_user1_clk {
423 #clock-cells = <0>;
424 compatible = "altr,socfpga-gate-clk";
425 clocks = <&h2f_usr1_clk>;
426 clk-gate = <0xa0 7>;
427 };
428
429 sdmmc_clk: sdmmc_clk {
430 #clock-cells = <0>;
431 compatible = "altr,socfpga-gate-clk";
432 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
433 clk-gate = <0xa0 8>;
434 clk-phase = <0 135>;
435 };
436
437 nand_x_clk: nand_x_clk {
438 #clock-cells = <0>;
439 compatible = "altr,socfpga-gate-clk";
440 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
441 clk-gate = <0xa0 9>;
442 };
443
444 nand_clk: nand_clk {
445 #clock-cells = <0>;
446 compatible = "altr,socfpga-gate-clk";
447 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
448 clk-gate = <0xa0 10>;
449 fixed-divider = <4>;
450 };
451
452 qspi_clk: qspi_clk {
453 #clock-cells = <0>;
454 compatible = "altr,socfpga-gate-clk";
455 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
456 clk-gate = <0xa0 11>;
457 };
458 };
459 };
460
461 gmac0: ethernet@ff700000 {
462 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
463 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
464 reg = <0xff700000 0x2000>;
465 interrupts = <0 115 4>;
466 interrupt-names = "macirq";
467 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
468 clocks = <&emac0_clk>;
469 clock-names = "stmmaceth";
470 status = "disabled";
471 };
472
473 gmac1: ethernet@ff702000 {
474 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
475 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
476 reg = <0xff702000 0x2000>;
477 interrupts = <0 120 4>;
478 interrupt-names = "macirq";
479 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
480 clocks = <&emac1_clk>;
481 clock-names = "stmmaceth";
482 status = "disabled";
483 };
484
485 i2c0: i2c@ffc04000 {
486 #address-cells = <1>;
487 #size-cells = <0>;
488 compatible = "snps,designware-i2c";
489 reg = <0xffc04000 0x1000>;
490 clocks = <&l4_sp_clk>;
491 interrupts = <0 158 0x4>;
492 status = "disabled";
493 };
494
495 i2c1: i2c@ffc05000 {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 compatible = "snps,designware-i2c";
499 reg = <0xffc05000 0x1000>;
500 clocks = <&l4_sp_clk>;
501 interrupts = <0 159 0x4>;
502 status = "disabled";
503 };
504
505 i2c2: i2c@ffc06000 {
506 #address-cells = <1>;
507 #size-cells = <0>;
508 compatible = "snps,designware-i2c";
509 reg = <0xffc06000 0x1000>;
510 clocks = <&l4_sp_clk>;
511 interrupts = <0 160 0x4>;
512 status = "disabled";
513 };
514
515 i2c3: i2c@ffc07000 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "snps,designware-i2c";
519 reg = <0xffc07000 0x1000>;
520 clocks = <&l4_sp_clk>;
521 interrupts = <0 161 0x4>;
522 status = "disabled";
523 };
524
525 L2: l2-cache@fffef000 {
526 compatible = "arm,pl310-cache";
527 reg = <0xfffef000 0x1000>;
528 interrupts = <0 38 0x04>;
529 cache-unified;
530 cache-level = <2>;
531 arm,tag-latency = <1 1 1>;
532 arm,data-latency = <2 1 1>;
533 };
534
535 mmc: dwmmc0@ff704000 {
536 compatible = "altr,socfpga-dw-mshc";
537 reg = <0xff704000 0x1000>;
538 interrupts = <0 139 4>;
539 fifo-depth = <0x400>;
540 #address-cells = <1>;
541 #size-cells = <0>;
542 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
543 clock-names = "biu", "ciu";
544 };
545
546 /* Local timer */
547 timer@fffec600 {
548 compatible = "arm,cortex-a9-twd-timer";
549 reg = <0xfffec600 0x100>;
550 interrupts = <1 13 0xf04>;
551 clocks = <&mpu_periph_clk>;
552 };
553
554 timer0: timer0@ffc08000 {
555 compatible = "snps,dw-apb-timer";
556 interrupts = <0 167 4>;
557 reg = <0xffc08000 0x1000>;
558 };
559
560 timer1: timer1@ffc09000 {
561 compatible = "snps,dw-apb-timer";
562 interrupts = <0 168 4>;
563 reg = <0xffc09000 0x1000>;
564 };
565
566 timer2: timer2@ffd00000 {
567 compatible = "snps,dw-apb-timer";
568 interrupts = <0 169 4>;
569 reg = <0xffd00000 0x1000>;
570 };
571
572 timer3: timer3@ffd01000 {
573 compatible = "snps,dw-apb-timer";
574 interrupts = <0 170 4>;
575 reg = <0xffd01000 0x1000>;
576 };
577
578 uart0: serial0@ffc02000 {
579 compatible = "snps,dw-apb-uart";
580 reg = <0xffc02000 0x1000>;
581 interrupts = <0 162 4>;
582 reg-shift = <2>;
583 reg-io-width = <4>;
584 };
585
586 uart1: serial1@ffc03000 {
587 compatible = "snps,dw-apb-uart";
588 reg = <0xffc03000 0x1000>;
589 interrupts = <0 163 4>;
590 reg-shift = <2>;
591 reg-io-width = <4>;
592 };
593
594 rstmgr@ffd05000 {
595 compatible = "altr,rst-mgr";
596 reg = <0xffd05000 0x1000>;
597 };
598
599 sysmgr: sysmgr@ffd08000 {
600 compatible = "altr,sys-mgr", "syscon";
601 reg = <0xffd08000 0x4000>;
602 };
603 };
604 };
Linux kernel - Deliverables
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