arch/arm/boot/dts/stih407-family.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics Limited.
   3  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih407-pinctrl.dtsi"
  10 #include <dt-bindings/mfd/st-lpc.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/reset-controller/stih407-resets.h>
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a9";
  23                         reg = <0>;
  24                 };
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <1>;
  29                 };
  30         };
  31
  32         intc: interrupt-controller@08761000 {
  33                 compatible = "arm,cortex-a9-gic";
  34                 #interrupt-cells = <3>;
  35                 interrupt-controller;
  36                 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
  37         };
  38
  39         scu@08760000 {
  40                 compatible = "arm,cortex-a9-scu";
  41                 reg = <0x08760000 0x1000>;
  42         };
  43
  44         timer@08760200 {
  45                 interrupt-parent = <&intc>;
  46                 compatible = "arm,cortex-a9-global-timer";
  47                 reg = <0x08760200 0x100>;
  48                 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  49                 clocks = <&arm_periph_clk>;
  50         };
  51
  52         l2: cache-controller {
  53                 compatible = "arm,pl310-cache";
  54                 reg = <0x08762000 0x1000>;
  55                 arm,data-latency = <3 3 3>;
  56                 arm,tag-latency = <2 2 2>;
  57                 cache-unified;
  58                 cache-level = <2>;
  59         };
  60
  61         soc {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 interrupt-parent = <&intc>;
  65                 ranges;
  66                 compatible = "simple-bus";
  67
  68                 powerdown: powerdown-controller {
  69                         compatible = "st,stih407-powerdown";
  70                         #reset-cells = <1>;
  71                 };
  72
  73                 softreset: softreset-controller {
  74                         compatible = "st,stih407-softreset";
  75                         #reset-cells = <1>;
  76                 };
  77
  78                 picophyreset: picophyreset-controller {
  79                         compatible = "st,stih407-picophyreset";
  80                         #reset-cells = <1>;
  81                 };
  82
  83                 syscfg_sbc: sbc-syscfg@9620000 {
  84                         compatible = "st,stih407-sbc-syscfg", "syscon";
  85                         reg = <0x9620000 0x1000>;
  86                 };
  87
  88                 syscfg_front: front-syscfg@9280000 {
  89                         compatible = "st,stih407-front-syscfg", "syscon";
  90                         reg = <0x9280000 0x1000>;
  91                 };
  92
  93                 syscfg_rear: rear-syscfg@9290000 {
  94                         compatible = "st,stih407-rear-syscfg", "syscon";
  95                         reg = <0x9290000 0x1000>;
  96                 };
  97
  98                 syscfg_flash: flash-syscfg@92a0000 {
  99                         compatible = "st,stih407-flash-syscfg", "syscon";
 100                         reg = <0x92a0000 0x1000>;
 101                 };
 102
 103                 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
 104                         compatible = "st,stih407-sbc-reg-syscfg", "syscon";
 105                         reg = <0x9600000 0x1000>;
 106                 };
 107
 108                 syscfg_core: core-syscfg@92b0000 {
 109                         compatible = "st,stih407-core-syscfg", "syscon";
 110                         reg = <0x92b0000 0x1000>;
 111                 };
 112
 113                 syscfg_lpm: lpm-syscfg@94b5100 {
 114                         compatible = "st,stih407-lpm-syscfg", "syscon";
 115                         reg = <0x94b5100 0x1000>;
 116                 };
 117
 118                 serial@9830000 {
 119                         compatible = "st,asc";
 120                         reg = <0x9830000 0x2c>;
 121                         interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
 122                         pinctrl-names = "default";
 123                         pinctrl-0 = <&pinctrl_serial0>;
 124                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 125
 126                         status = "disabled";
 127                 };
 128
 129                 serial@9831000 {
 130                         compatible = "st,asc";
 131                         reg = <0x9831000 0x2c>;
 132                         interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
 133                         pinctrl-names = "default";
 134                         pinctrl-0 = <&pinctrl_serial1>;
 135                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 136
 137                         status = "disabled";
 138                 };
 139
 140                 serial@9832000 {
 141                         compatible = "st,asc";
 142                         reg = <0x9832000 0x2c>;
 143                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
 144                         pinctrl-names = "default";
 145                         pinctrl-0 = <&pinctrl_serial2>;
 146                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 147
 148                         status = "disabled";
 149                 };
 150
 151                 /* SBC_ASC0 - UART10 */
 152                 sbc_serial0: serial@9530000 {
 153                         compatible = "st,asc";
 154                         reg = <0x9530000 0x2c>;
 155                         interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
 156                         pinctrl-names = "default";
 157                         pinctrl-0 = <&pinctrl_sbc_serial0>;
 158                         clocks = <&clk_sysin>;
 159
 160                         status = "disabled";
 161                 };
 162
 163                 serial@9531000 {
 164                         compatible = "st,asc";
 165                         reg = <0x9531000 0x2c>;
 166                         interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
 167                         pinctrl-names = "default";
 168                         pinctrl-0 = <&pinctrl_sbc_serial1>;
 169                         clocks = <&clk_sysin>;
 170
 171                         status = "disabled";
 172                 };
 173
 174                 i2c@9840000 {
 175                         compatible = "st,comms-ssc4-i2c";
 176                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 177                         reg = <0x9840000 0x110>;
 178                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 179                         clock-names = "ssc";
 180                         clock-frequency = <400000>;
 181                         pinctrl-names = "default";
 182                         pinctrl-0 = <&pinctrl_i2c0_default>;
 183
 184                         status = "disabled";
 185                 };
 186
 187                 i2c@9841000 {
 188                         compatible = "st,comms-ssc4-i2c";
 189                         reg = <0x9841000 0x110>;
 190                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 192                         clock-names = "ssc";
 193                         clock-frequency = <400000>;
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&pinctrl_i2c1_default>;
 196
 197                         status = "disabled";
 198                 };
 199
 200                 i2c@9842000 {
 201                         compatible = "st,comms-ssc4-i2c";
 202                         reg = <0x9842000 0x110>;
 203                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 204                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 205                         clock-names = "ssc";
 206                         clock-frequency = <400000>;
 207                         pinctrl-names = "default";
 208                         pinctrl-0 = <&pinctrl_i2c2_default>;
 209
 210                         status = "disabled";
 211                 };
 212
 213                 i2c@9843000 {
 214                         compatible = "st,comms-ssc4-i2c";
 215                         reg = <0x9843000 0x110>;
 216                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 218                         clock-names = "ssc";
 219                         clock-frequency = <400000>;
 220                         pinctrl-names = "default";
 221                         pinctrl-0 = <&pinctrl_i2c3_default>;
 222
 223                         status = "disabled";
 224                 };
 225
 226                 i2c@9844000 {
 227                         compatible = "st,comms-ssc4-i2c";
 228                         reg = <0x9844000 0x110>;
 229                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 230                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 231                         clock-names = "ssc";
 232                         clock-frequency = <400000>;
 233                         pinctrl-names = "default";
 234                         pinctrl-0 = <&pinctrl_i2c4_default>;
 235
 236                         status = "disabled";
 237                 };
 238
 239                 i2c@9845000 {
 240                         compatible = "st,comms-ssc4-i2c";
 241                         reg = <0x9845000 0x110>;
 242                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 243                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 244                         clock-names = "ssc";
 245                         clock-frequency = <400000>;
 246                         pinctrl-names = "default";
 247                         pinctrl-0 = <&pinctrl_i2c5_default>;
 248
 249                         status = "disabled";
 250                 };
 251
 252
 253                 /* SSCs on SBC */
 254                 i2c@9540000 {
 255                         compatible = "st,comms-ssc4-i2c";
 256                         reg = <0x9540000 0x110>;
 257                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 258                         clocks = <&clk_sysin>;
 259                         clock-names = "ssc";
 260                         clock-frequency = <400000>;
 261                         pinctrl-names = "default";
 262                         pinctrl-0 = <&pinctrl_i2c10_default>;
 263
 264                         status = "disabled";
 265                 };
 266
 267                 i2c@9541000 {
 268                         compatible = "st,comms-ssc4-i2c";
 269                         reg = <0x9541000 0x110>;
 270                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 271                         clocks = <&clk_sysin>;
 272                         clock-names = "ssc";
 273                         clock-frequency = <400000>;
 274                         pinctrl-names = "default";
 275                         pinctrl-0 = <&pinctrl_i2c11_default>;
 276
 277                         status = "disabled";
 278                 };
 279
 280                 usb2_picophy0: phy1 {
 281                         compatible = "st,stih407-usb2-phy";
 282                         #phy-cells = <0>;
 283                         st,syscfg = <&syscfg_core 0x100 0xf4>;
 284                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
 285                                  <&picophyreset STIH407_PICOPHY2_RESET>;
 286                         reset-names = "global", "port";
 287                 };
 288
 289                 miphy28lp_phy: miphy28lp@9b22000 {
 290                         compatible = "st,miphy28lp-phy";
 291                         st,syscfg = <&syscfg_core>;
 292                         #address-cells  = <1>;
 293                         #size-cells     = <1>;
 294                         ranges;
 295
 296                         phy_port0: port@9b22000 {
 297                                 reg = <0x9b22000 0xff>,
 298                                       <0x9b09000 0xff>,
 299                                       <0x9b04000 0xff>;
 300                                 reg-names = "sata-up",
 301                                             "pcie-up",
 302                                             "pipew";
 303
 304                                 st,syscfg = <0x114 0x818 0xe0 0xec>;
 305                                 #phy-cells = <1>;
 306
 307                                 reset-names = "miphy-sw-rst";
 308                                 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
 309                         };
 310
 311                         phy_port1: port@9b2a000 {
 312                                 reg = <0x9b2a000 0xff>,
 313                                       <0x9b19000 0xff>,
 314                                       <0x9b14000 0xff>;
 315                                 reg-names = "sata-up",
 316                                             "pcie-up",
 317                                             "pipew";
 318
 319                                 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
 320
 321                                 #phy-cells = <1>;
 322
 323                                 reset-names = "miphy-sw-rst";
 324                                 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
 325                         };
 326
 327                         phy_port2: port@8f95000 {
 328                                 reg = <0x8f95000 0xff>,
 329                                       <0x8f90000 0xff>;
 330                                 reg-names = "pipew",
 331                                             "usb3-up";
 332
 333                                 st,syscfg = <0x11c 0x820>;
 334
 335                                 #phy-cells = <1>;
 336
 337                                 reset-names = "miphy-sw-rst";
 338                                 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 339                         };
 340                 };
 341
 342                 spi@9840000 {
 343                         compatible = "st,comms-ssc4-spi";
 344                         reg = <0x9840000 0x110>;
 345                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 347                         clock-names = "ssc";
 348                         pinctrl-0 = <&pinctrl_spi0_default>;
 349                         pinctrl-names = "default";
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352
 353                         status = "disabled";
 354                 };
 355
 356                 spi@9841000 {
 357                         compatible = "st,comms-ssc4-spi";
 358                         reg = <0x9841000 0x110>;
 359                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 360                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 361                         clock-names = "ssc";
 362
 363                         status = "disabled";
 364                 };
 365
 366                 spi@9842000 {
 367                         compatible = "st,comms-ssc4-spi";
 368                         reg = <0x9842000 0x110>;
 369                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 371                         clock-names = "ssc";
 372
 373                         status = "disabled";
 374                 };
 375
 376                 spi@9843000 {
 377                         compatible = "st,comms-ssc4-spi";
 378                         reg = <0x9843000 0x110>;
 379                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 380                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 381                         clock-names = "ssc";
 382
 383                         status = "disabled";
 384                 };
 385
 386                 spi@9844000 {
 387                         compatible = "st,comms-ssc4-spi";
 388                         reg = <0x9844000 0x110>;
 389                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 390                         clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
 391                         clock-names = "ssc";
 392
 393                         status = "disabled";
 394                 };
 395
 396                 /* SBC SSC */
 397                 spi@9540000 {
 398                         compatible = "st,comms-ssc4-spi";
 399                         reg = <0x9540000 0x110>;
 400                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 401                         clocks = <&clk_sysin>;
 402                         clock-names = "ssc";
 403
 404                         status = "disabled";
 405                 };
 406
 407                 spi@9541000 {
 408                         compatible = "st,comms-ssc4-spi";
 409                         reg = <0x9541000 0x110>;
 410                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 411                         clocks = <&clk_sysin>;
 412                         clock-names = "ssc";
 413
 414                         status = "disabled";
 415                 };
 416
 417                 spi@9542000 {
 418                         compatible = "st,comms-ssc4-spi";
 419                         reg = <0x9542000 0x110>;
 420                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&clk_sysin>;
 422                         clock-names = "ssc";
 423
 424                         status = "disabled";
 425                 };
 426
 427                 mmc0: sdhci@09060000 {
 428                         compatible = "st,sdhci-stih407", "st,sdhci";
 429                         status = "disabled";
 430                         reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
 431                         reg-names = "mmc", "top-mmc-delay";
 432                         interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
 433                         interrupt-names = "mmcirq";
 434                         pinctrl-names = "default";
 435                         pinctrl-0 = <&pinctrl_mmc0>;
 436                         clock-names = "mmc";
 437                         clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
 438                         bus-width = <8>;
 439                         non-removable;
 440                 };
 441
 442                 mmc1: sdhci@09080000 {
 443                         compatible = "st,sdhci-stih407", "st,sdhci";
 444                         status = "disabled";
 445                         reg = <0x09080000 0x7ff>;
 446                         reg-names = "mmc";
 447                         interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
 448                         interrupt-names = "mmcirq";
 449                         pinctrl-names = "default";
 450                         pinctrl-0 = <&pinctrl_sd1>;
 451                         clock-names = "mmc";
 452                         clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
 453                         resets = <&softreset STIH407_MMC1_SOFTRESET>;
 454                         bus-width = <4>;
 455                 };
 456
 457                 /* Watchdog and Real-Time Clock */
 458                 lpc@8787000 {
 459                         compatible = "st,stih407-lpc";
 460                         reg = <0x8787000 0x1000>;
 461                         interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
 462                         clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
 463                         timeout-sec = <120>;
 464                         st,syscfg = <&syscfg_core>;
 465                         st,lpc-mode = <ST_LPC_MODE_WDT>;
 466                 };
 467
 468                 lpc@8788000 {
 469                         compatible = "st,stih407-lpc";
 470                         reg = <0x8788000 0x1000>;
 471                         interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
 472                         clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
 473                         st,lpc-mode = <ST_LPC_MODE_RTC>;
 474                 };
 475
 476                 sata0: sata@9b20000 {
 477                         compatible = "st,ahci";
 478                         reg = <0x9b20000 0x1000>;
 479
 480                         interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 481                         interrupt-names = "hostc";
 482
 483                         phys = <&phy_port0 PHY_TYPE_SATA>;
 484                         phy-names = "ahci_phy";
 485
 486                         resets = <&powerdown STIH407_SATA0_POWERDOWN>,
 487                                  <&softreset STIH407_SATA0_SOFTRESET>,
 488                                  <&softreset STIH407_SATA0_PWR_SOFTRESET>;
 489                         reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
 490
 491                         clock-names = "ahci_clk";
 492                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 493
 494                         status = "disabled";
 495                 };
 496
 497                 sata1: sata@9b28000 {
 498                         compatible = "st,ahci";
 499                         reg = <0x9b28000 0x1000>;
 500
 501                         interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
 502                         interrupt-names = "hostc";
 503
 504                         phys = <&phy_port1 PHY_TYPE_SATA>;
 505                         phy-names = "ahci_phy";
 506
 507                         resets = <&powerdown STIH407_SATA1_POWERDOWN>,
 508                                  <&softreset STIH407_SATA1_SOFTRESET>,
 509                                  <&softreset STIH407_SATA1_PWR_SOFTRESET>;
 510                         reset-names = "pwr-dwn",
 511                                       "sw-rst",
 512                                       "pwr-rst";
 513
 514                         clock-names = "ahci_clk";
 515                         clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
 516
 517                         status = "disabled";
 518                 };
 519         };
 520 };