2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include "skeleton.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&intc>;
65 compatible = "allwinner,simple-framebuffer",
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
68 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
69 <&ahb_gates 44>, <&dram_gates 26>;
74 compatible = "allwinner,simple-framebuffer",
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
78 <&ahb_gates 44>, <&ahb_gates 46>,
79 <&dram_gates 25>, <&dram_gates 26>;
84 compatible = "allwinner,simple-framebuffer",
86 allwinner,pipeline = "de_fe0-de_be0-lcd0";
87 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
88 <&ahb_gates 46>, <&dram_gates 25>,
94 compatible = "allwinner,simple-framebuffer",
96 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
97 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
98 <&ahb_gates 44>, <&ahb_gates 46>,
99 <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;
105 #address-cells = <1>;
109 compatible = "arm,cortex-a8";
112 clock-latency = <244144>; /* 8 32k periods */
120 #cooling-cells = <2>;
121 cooling-min-level = <0>;
122 cooling-max-level = <3>;
129 polling-delay-passive = <250>;
130 polling-delay = <1000>;
131 thermal-sensors = <&rtp>;
135 trip = <&cpu_alert0>;
136 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
141 cpu_alert0: cpu_alert0 {
143 temperature = <850000>;
150 temperature = <100000>;
159 reg = <0x40000000 0x80000000>;
163 #address-cells = <1>;
168 * This is a dummy clock, to be used as placeholder on
169 * other mux clocks when a specific parent clock is not
170 * yet implemented. It should be dropped when the driver
175 compatible = "fixed-clock";
176 clock-frequency = <0>;
179 osc24M: clk@01c20050 {
181 compatible = "allwinner,sun4i-a10-osc-clk";
182 reg = <0x01c20050 0x4>;
183 clock-frequency = <24000000>;
184 clock-output-names = "osc24M";
188 compatible = "fixed-factor-clock";
193 clock-output-names = "osc3M";
198 compatible = "fixed-clock";
199 clock-frequency = <32768>;
200 clock-output-names = "osc32k";
205 compatible = "allwinner,sun4i-a10-pll1-clk";
206 reg = <0x01c20000 0x4>;
208 clock-output-names = "pll1";
213 compatible = "allwinner,sun4i-a10-pll2-clk";
214 reg = <0x01c20008 0x8>;
216 clock-output-names = "pll2-1x", "pll2-2x",
217 "pll2-4x", "pll2-8x";
222 compatible = "allwinner,sun4i-a10-pll3-clk";
223 reg = <0x01c20010 0x4>;
225 clock-output-names = "pll3";
229 compatible = "fixed-factor-clock";
234 clock-output-names = "pll3-2x";
239 compatible = "allwinner,sun4i-a10-pll1-clk";
240 reg = <0x01c20018 0x4>;
242 clock-output-names = "pll4";
247 compatible = "allwinner,sun4i-a10-pll5-clk";
248 reg = <0x01c20020 0x4>;
250 clock-output-names = "pll5_ddr", "pll5_other";
255 compatible = "allwinner,sun4i-a10-pll6-clk";
256 reg = <0x01c20028 0x4>;
258 clock-output-names = "pll6_sata", "pll6_other", "pll6";
263 compatible = "allwinner,sun4i-a10-pll3-clk";
264 reg = <0x01c20030 0x4>;
266 clock-output-names = "pll7";
270 compatible = "fixed-factor-clock";
275 clock-output-names = "pll7-2x";
281 compatible = "allwinner,sun4i-a10-cpu-clk";
282 reg = <0x01c20054 0x4>;
283 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
284 clock-output-names = "cpu";
289 compatible = "allwinner,sun4i-a10-axi-clk";
290 reg = <0x01c20054 0x4>;
292 clock-output-names = "axi";
295 axi_gates: clk@01c2005c {
297 compatible = "allwinner,sun4i-a10-axi-gates-clk";
298 reg = <0x01c2005c 0x4>;
301 clock-output-names = "axi_dram";
306 compatible = "allwinner,sun4i-a10-ahb-clk";
307 reg = <0x01c20054 0x4>;
309 clock-output-names = "ahb";
312 ahb_gates: clk@01c20060 {
314 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
315 reg = <0x01c20060 0x8>;
317 clock-indices = <0>, <1>,
332 clock-output-names = "ahb_usb0", "ahb_ehci0",
333 "ahb_ohci0", "ahb_ehci1",
334 "ahb_ohci1", "ahb_ss", "ahb_dma",
335 "ahb_bist", "ahb_mmc0", "ahb_mmc1",
336 "ahb_mmc2", "ahb_mmc3", "ahb_ms",
337 "ahb_nand", "ahb_sdram", "ahb_ace",
338 "ahb_emac", "ahb_ts", "ahb_spi0",
339 "ahb_spi1", "ahb_spi2", "ahb_spi3",
340 "ahb_pata", "ahb_sata", "ahb_gps",
341 "ahb_ve", "ahb_tvd", "ahb_tve0",
342 "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
343 "ahb_csi0", "ahb_csi1", "ahb_hdmi",
344 "ahb_de_be0", "ahb_de_be1",
345 "ahb_de_fe0", "ahb_de_fe1",
346 "ahb_mp", "ahb_mali400";
349 apb0: apb0@01c20054 {
351 compatible = "allwinner,sun4i-a10-apb0-clk";
352 reg = <0x01c20054 0x4>;
354 clock-output-names = "apb0";
357 apb0_gates: clk@01c20068 {
359 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
360 reg = <0x01c20068 0x4>;
362 clock-indices = <0>, <1>,
366 clock-output-names = "apb0_codec", "apb0_spdif",
367 "apb0_ac97", "apb0_iis",
368 "apb0_pio", "apb0_ir0",
369 "apb0_ir1", "apb0_keypad";
374 compatible = "allwinner,sun4i-a10-apb1-clk";
375 reg = <0x01c20058 0x4>;
376 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
377 clock-output-names = "apb1";
380 apb1_gates: clk@01c2006c {
382 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
383 reg = <0x01c2006c 0x4>;
385 clock-indices = <0>, <1>,
393 clock-output-names = "apb1_i2c0", "apb1_i2c1",
394 "apb1_i2c2", "apb1_can",
395 "apb1_scr", "apb1_ps20",
396 "apb1_ps21", "apb1_uart0",
397 "apb1_uart1", "apb1_uart2",
398 "apb1_uart3", "apb1_uart4",
399 "apb1_uart5", "apb1_uart6",
403 nand_clk: clk@01c20080 {
405 compatible = "allwinner,sun4i-a10-mod0-clk";
406 reg = <0x01c20080 0x4>;
407 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
408 clock-output-names = "nand";
411 ms_clk: clk@01c20084 {
413 compatible = "allwinner,sun4i-a10-mod0-clk";
414 reg = <0x01c20084 0x4>;
415 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
416 clock-output-names = "ms";
419 mmc0_clk: clk@01c20088 {
421 compatible = "allwinner,sun4i-a10-mmc-clk";
422 reg = <0x01c20088 0x4>;
423 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
424 clock-output-names = "mmc0",
429 mmc1_clk: clk@01c2008c {
431 compatible = "allwinner,sun4i-a10-mmc-clk";
432 reg = <0x01c2008c 0x4>;
433 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
434 clock-output-names = "mmc1",
439 mmc2_clk: clk@01c20090 {
441 compatible = "allwinner,sun4i-a10-mmc-clk";
442 reg = <0x01c20090 0x4>;
443 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
444 clock-output-names = "mmc2",
449 mmc3_clk: clk@01c20094 {
451 compatible = "allwinner,sun4i-a10-mmc-clk";
452 reg = <0x01c20094 0x4>;
453 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
454 clock-output-names = "mmc3",
459 ts_clk: clk@01c20098 {
461 compatible = "allwinner,sun4i-a10-mod0-clk";
462 reg = <0x01c20098 0x4>;
463 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
464 clock-output-names = "ts";
467 ss_clk: clk@01c2009c {
469 compatible = "allwinner,sun4i-a10-mod0-clk";
470 reg = <0x01c2009c 0x4>;
471 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
472 clock-output-names = "ss";
475 spi0_clk: clk@01c200a0 {
477 compatible = "allwinner,sun4i-a10-mod0-clk";
478 reg = <0x01c200a0 0x4>;
479 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
480 clock-output-names = "spi0";
483 spi1_clk: clk@01c200a4 {
485 compatible = "allwinner,sun4i-a10-mod0-clk";
486 reg = <0x01c200a4 0x4>;
487 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
488 clock-output-names = "spi1";
491 spi2_clk: clk@01c200a8 {
493 compatible = "allwinner,sun4i-a10-mod0-clk";
494 reg = <0x01c200a8 0x4>;
495 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
496 clock-output-names = "spi2";
499 pata_clk: clk@01c200ac {
501 compatible = "allwinner,sun4i-a10-mod0-clk";
502 reg = <0x01c200ac 0x4>;
503 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
504 clock-output-names = "pata";
507 ir0_clk: clk@01c200b0 {
509 compatible = "allwinner,sun4i-a10-mod0-clk";
510 reg = <0x01c200b0 0x4>;
511 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
512 clock-output-names = "ir0";
515 ir1_clk: clk@01c200b4 {
517 compatible = "allwinner,sun4i-a10-mod0-clk";
518 reg = <0x01c200b4 0x4>;
519 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
520 clock-output-names = "ir1";
523 spdif_clk: clk@01c200c0 {
525 compatible = "allwinner,sun4i-a10-mod1-clk";
526 reg = <0x01c200c0 0x4>;
527 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
528 <&pll2 SUN4I_A10_PLL2_4X>,
529 <&pll2 SUN4I_A10_PLL2_2X>,
530 <&pll2 SUN4I_A10_PLL2_1X>;
531 clock-output-names = "spdif";
534 usb_clk: clk@01c200cc {
537 compatible = "allwinner,sun4i-a10-usb-clk";
538 reg = <0x01c200cc 0x4>;
540 clock-output-names = "usb_ohci0", "usb_ohci1",
544 spi3_clk: clk@01c200d4 {
546 compatible = "allwinner,sun4i-a10-mod0-clk";
547 reg = <0x01c200d4 0x4>;
548 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
549 clock-output-names = "spi3";
552 dram_gates: clk@01c20100 {
554 compatible = "allwinner,sun4i-a10-dram-gates-clk";
555 reg = <0x01c20100 0x4>;
566 clock-output-names = "dram_ve",
567 "dram_csi0", "dram_csi1",
570 "dram_tve0", "dram_tve1",
572 "dram_de_fe1", "dram_de_fe0",
573 "dram_de_be0", "dram_de_be1",
574 "dram_de_mp", "dram_ace";
577 ve_clk: clk@01c2013c {
580 compatible = "allwinner,sun4i-a10-ve-clk";
581 reg = <0x01c2013c 0x4>;
583 clock-output-names = "ve";
586 codec_clk: clk@01c20140 {
588 compatible = "allwinner,sun4i-a10-codec-clk";
589 reg = <0x01c20140 0x4>;
590 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
591 clock-output-names = "codec";
596 compatible = "simple-bus";
597 #address-cells = <1>;
601 sram-controller@01c00000 {
602 compatible = "allwinner,sun4i-a10-sram-controller";
603 reg = <0x01c00000 0x30>;
604 #address-cells = <1>;
608 sram_a: sram@00000000 {
609 compatible = "mmio-sram";
610 reg = <0x00000000 0xc000>;
611 #address-cells = <1>;
613 ranges = <0 0x00000000 0xc000>;
615 emac_sram: sram-section@8000 {
616 compatible = "allwinner,sun4i-a10-sram-a3-a4";
617 reg = <0x8000 0x4000>;
622 sram_d: sram@00010000 {
623 compatible = "mmio-sram";
624 reg = <0x00010000 0x1000>;
625 #address-cells = <1>;
627 ranges = <0 0x00010000 0x1000>;
629 otg_sram: sram-section@0000 {
630 compatible = "allwinner,sun4i-a10-sram-d";
631 reg = <0x0000 0x1000>;
637 dma: dma-controller@01c02000 {
638 compatible = "allwinner,sun4i-a10-dma";
639 reg = <0x01c02000 0x1000>;
641 clocks = <&ahb_gates 6>;
646 compatible = "allwinner,sun4i-a10-spi";
647 reg = <0x01c05000 0x1000>;
649 clocks = <&ahb_gates 20>, <&spi0_clk>;
650 clock-names = "ahb", "mod";
651 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
652 <&dma SUN4I_DMA_DEDICATED 26>;
653 dma-names = "rx", "tx";
655 #address-cells = <1>;
660 compatible = "allwinner,sun4i-a10-spi";
661 reg = <0x01c06000 0x1000>;
663 clocks = <&ahb_gates 21>, <&spi1_clk>;
664 clock-names = "ahb", "mod";
665 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
666 <&dma SUN4I_DMA_DEDICATED 8>;
667 dma-names = "rx", "tx";
669 #address-cells = <1>;
673 emac: ethernet@01c0b000 {
674 compatible = "allwinner,sun4i-a10-emac";
675 reg = <0x01c0b000 0x1000>;
677 clocks = <&ahb_gates 17>;
678 allwinner,sram = <&emac_sram 1>;
682 mdio: mdio@01c0b080 {
683 compatible = "allwinner,sun4i-a10-mdio";
684 reg = <0x01c0b080 0x14>;
686 #address-cells = <1>;
691 compatible = "allwinner,sun4i-a10-mmc";
692 reg = <0x01c0f000 0x1000>;
693 clocks = <&ahb_gates 8>,
703 #address-cells = <1>;
708 compatible = "allwinner,sun4i-a10-mmc";
709 reg = <0x01c10000 0x1000>;
710 clocks = <&ahb_gates 9>,
720 #address-cells = <1>;
725 compatible = "allwinner,sun4i-a10-mmc";
726 reg = <0x01c11000 0x1000>;
727 clocks = <&ahb_gates 10>,
737 #address-cells = <1>;
742 compatible = "allwinner,sun4i-a10-mmc";
743 reg = <0x01c12000 0x1000>;
744 clocks = <&ahb_gates 11>,
754 #address-cells = <1>;
758 usb_otg: usb@01c13000 {
759 compatible = "allwinner,sun4i-a10-musb";
760 reg = <0x01c13000 0x0400>;
761 clocks = <&ahb_gates 0>;
763 interrupt-names = "mc";
766 extcon = <&usbphy 0>;
767 allwinner,sram = <&otg_sram 1>;
771 usbphy: phy@01c13400 {
773 compatible = "allwinner,sun4i-a10-usb-phy";
774 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
775 reg-names = "phy_ctrl", "pmu1", "pmu2";
776 clocks = <&usb_clk 8>;
777 clock-names = "usb_phy";
778 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
779 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
783 ehci0: usb@01c14000 {
784 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
785 reg = <0x01c14000 0x100>;
787 clocks = <&ahb_gates 1>;
793 ohci0: usb@01c14400 {
794 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
795 reg = <0x01c14400 0x100>;
797 clocks = <&usb_clk 6>, <&ahb_gates 2>;
803 crypto: crypto-engine@01c15000 {
804 compatible = "allwinner,sun4i-a10-crypto";
805 reg = <0x01c15000 0x1000>;
807 clocks = <&ahb_gates 5>, <&ss_clk>;
808 clock-names = "ahb", "mod";
812 compatible = "allwinner,sun4i-a10-spi";
813 reg = <0x01c17000 0x1000>;
815 clocks = <&ahb_gates 22>, <&spi2_clk>;
816 clock-names = "ahb", "mod";
817 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
818 <&dma SUN4I_DMA_DEDICATED 28>;
819 dma-names = "rx", "tx";
821 #address-cells = <1>;
825 ahci: sata@01c18000 {
826 compatible = "allwinner,sun4i-a10-ahci";
827 reg = <0x01c18000 0x1000>;
829 clocks = <&pll6 0>, <&ahb_gates 25>;
833 ehci1: usb@01c1c000 {
834 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
835 reg = <0x01c1c000 0x100>;
837 clocks = <&ahb_gates 3>;
843 ohci1: usb@01c1c400 {
844 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
845 reg = <0x01c1c400 0x100>;
847 clocks = <&usb_clk 7>, <&ahb_gates 4>;
854 compatible = "allwinner,sun4i-a10-spi";
855 reg = <0x01c1f000 0x1000>;
857 clocks = <&ahb_gates 23>, <&spi3_clk>;
858 clock-names = "ahb", "mod";
859 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
860 <&dma SUN4I_DMA_DEDICATED 30>;
861 dma-names = "rx", "tx";
863 #address-cells = <1>;
867 intc: interrupt-controller@01c20400 {
868 compatible = "allwinner,sun4i-a10-ic";
869 reg = <0x01c20400 0x400>;
870 interrupt-controller;
871 #interrupt-cells = <1>;
874 pio: pinctrl@01c20800 {
875 compatible = "allwinner,sun4i-a10-pinctrl";
876 reg = <0x01c20800 0x400>;
878 clocks = <&apb0_gates 5>;
880 interrupt-controller;
881 #interrupt-cells = <3>;
884 pwm0_pins_a: pwm0@0 {
885 allwinner,pins = "PB2";
886 allwinner,function = "pwm";
887 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
888 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
891 pwm1_pins_a: pwm1@0 {
892 allwinner,pins = "PI3";
893 allwinner,function = "pwm";
894 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
895 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
898 uart0_pins_a: uart0@0 {
899 allwinner,pins = "PB22", "PB23";
900 allwinner,function = "uart0";
901 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
902 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
905 uart0_pins_b: uart0@1 {
906 allwinner,pins = "PF2", "PF4";
907 allwinner,function = "uart0";
908 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
909 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
912 uart1_pins_a: uart1@0 {
913 allwinner,pins = "PA10", "PA11";
914 allwinner,function = "uart1";
915 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
916 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
919 i2c0_pins_a: i2c0@0 {
920 allwinner,pins = "PB0", "PB1";
921 allwinner,function = "i2c0";
922 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
923 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
926 i2c1_pins_a: i2c1@0 {
927 allwinner,pins = "PB18", "PB19";
928 allwinner,function = "i2c1";
929 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
930 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
933 i2c2_pins_a: i2c2@0 {
934 allwinner,pins = "PB20", "PB21";
935 allwinner,function = "i2c2";
936 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
937 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
940 emac_pins_a: emac0@0 {
941 allwinner,pins = "PA0", "PA1", "PA2",
942 "PA3", "PA4", "PA5", "PA6",
943 "PA7", "PA8", "PA9", "PA10",
944 "PA11", "PA12", "PA13", "PA14",
946 allwinner,function = "emac";
947 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
948 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
951 mmc0_pins_a: mmc0@0 {
952 allwinner,pins = "PF0", "PF1", "PF2",
954 allwinner,function = "mmc0";
955 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
956 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
959 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
960 allwinner,pins = "PH1";
961 allwinner,function = "gpio_in";
962 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
963 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
966 ir0_rx_pins_a: ir0@0 {
967 allwinner,pins = "PB4";
968 allwinner,function = "ir0";
969 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
970 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
973 ir0_tx_pins_a: ir0@1 {
974 allwinner,pins = "PB3";
975 allwinner,function = "ir0";
976 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
977 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
980 ir1_rx_pins_a: ir1@0 {
981 allwinner,pins = "PB23";
982 allwinner,function = "ir1";
983 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
984 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
987 ir1_tx_pins_a: ir1@1 {
988 allwinner,pins = "PB22";
989 allwinner,function = "ir1";
990 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
991 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
994 spi0_pins_a: spi0@0 {
995 allwinner,pins = "PI11", "PI12", "PI13";
996 allwinner,function = "spi0";
997 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
998 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1001 spi0_cs0_pins_a: spi0_cs0@0 {
1002 allwinner,pins = "PI10";
1003 allwinner,function = "spi0";
1004 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1005 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1008 spi1_pins_a: spi1@0 {
1009 allwinner,pins = "PI17", "PI18", "PI19";
1010 allwinner,function = "spi1";
1011 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1012 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1015 spi1_cs0_pins_a: spi1_cs0@0 {
1016 allwinner,pins = "PI16";
1017 allwinner,function = "spi1";
1018 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1019 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1022 spi2_pins_a: spi2@0 {
1023 allwinner,pins = "PC20", "PC21", "PC22";
1024 allwinner,function = "spi2";
1025 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1026 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1029 spi2_pins_b: spi2@1 {
1030 allwinner,pins = "PB15", "PB16", "PB17";
1031 allwinner,function = "spi2";
1032 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1033 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1036 spi2_cs0_pins_a: spi2_cs0@0 {
1037 allwinner,pins = "PC19";
1038 allwinner,function = "spi2";
1039 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1040 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1043 spi2_cs0_pins_b: spi2_cs0@1 {
1044 allwinner,pins = "PB14";
1045 allwinner,function = "spi2";
1046 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1047 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1050 ps20_pins_a: ps20@0 {
1051 allwinner,pins = "PI20", "PI21";
1052 allwinner,function = "ps2";
1053 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1054 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1057 ps21_pins_a: ps21@0 {
1058 allwinner,pins = "PH12", "PH13";
1059 allwinner,function = "ps2";
1060 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1061 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1064 spdif_tx_pins_a: spdif@0 {
1065 allwinner,pins = "PB13";
1066 allwinner,function = "spdif";
1067 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1068 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1073 compatible = "allwinner,sun4i-a10-timer";
1074 reg = <0x01c20c00 0x90>;
1079 wdt: watchdog@01c20c90 {
1080 compatible = "allwinner,sun4i-a10-wdt";
1081 reg = <0x01c20c90 0x10>;
1085 compatible = "allwinner,sun4i-a10-rtc";
1086 reg = <0x01c20d00 0x20>;
1091 compatible = "allwinner,sun4i-a10-pwm";
1092 reg = <0x01c20e00 0xc>;
1095 status = "disabled";
1098 spdif: spdif@01c21000 {
1099 #sound-dai-cells = <0>;
1100 compatible = "allwinner,sun4i-a10-spdif";
1101 reg = <0x01c21000 0x400>;
1103 clocks = <&apb0_gates 1>, <&spdif_clk>;
1104 clock-names = "apb", "spdif";
1105 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1106 <&dma SUN4I_DMA_NORMAL 2>;
1107 dma-names = "rx", "tx";
1108 status = "disabled";
1112 compatible = "allwinner,sun4i-a10-ir";
1113 clocks = <&apb0_gates 6>, <&ir0_clk>;
1114 clock-names = "apb", "ir";
1116 reg = <0x01c21800 0x40>;
1117 status = "disabled";
1121 compatible = "allwinner,sun4i-a10-ir";
1122 clocks = <&apb0_gates 7>, <&ir1_clk>;
1123 clock-names = "apb", "ir";
1125 reg = <0x01c21c00 0x40>;
1126 status = "disabled";
1129 lradc: lradc@01c22800 {
1130 compatible = "allwinner,sun4i-a10-lradc-keys";
1131 reg = <0x01c22800 0x100>;
1133 status = "disabled";
1136 codec: codec@01c22c00 {
1137 #sound-dai-cells = <0>;
1138 compatible = "allwinner,sun4i-a10-codec";
1139 reg = <0x01c22c00 0x40>;
1141 clocks = <&apb0_gates 0>, <&codec_clk>;
1142 clock-names = "apb", "codec";
1143 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1144 <&dma SUN4I_DMA_NORMAL 19>;
1145 dma-names = "rx", "tx";
1146 status = "disabled";
1149 sid: eeprom@01c23800 {
1150 compatible = "allwinner,sun4i-a10-sid";
1151 reg = <0x01c23800 0x10>;
1155 compatible = "allwinner,sun4i-a10-ts";
1156 reg = <0x01c25000 0x100>;
1158 #thermal-sensor-cells = <0>;
1161 uart0: serial@01c28000 {
1162 compatible = "snps,dw-apb-uart";
1163 reg = <0x01c28000 0x400>;
1167 clocks = <&apb1_gates 16>;
1168 status = "disabled";
1171 uart1: serial@01c28400 {
1172 compatible = "snps,dw-apb-uart";
1173 reg = <0x01c28400 0x400>;
1177 clocks = <&apb1_gates 17>;
1178 status = "disabled";
1181 uart2: serial@01c28800 {
1182 compatible = "snps,dw-apb-uart";
1183 reg = <0x01c28800 0x400>;
1187 clocks = <&apb1_gates 18>;
1188 status = "disabled";
1191 uart3: serial@01c28c00 {
1192 compatible = "snps,dw-apb-uart";
1193 reg = <0x01c28c00 0x400>;
1197 clocks = <&apb1_gates 19>;
1198 status = "disabled";
1201 uart4: serial@01c29000 {
1202 compatible = "snps,dw-apb-uart";
1203 reg = <0x01c29000 0x400>;
1207 clocks = <&apb1_gates 20>;
1208 status = "disabled";
1211 uart5: serial@01c29400 {
1212 compatible = "snps,dw-apb-uart";
1213 reg = <0x01c29400 0x400>;
1217 clocks = <&apb1_gates 21>;
1218 status = "disabled";
1221 uart6: serial@01c29800 {
1222 compatible = "snps,dw-apb-uart";
1223 reg = <0x01c29800 0x400>;
1227 clocks = <&apb1_gates 22>;
1228 status = "disabled";
1231 uart7: serial@01c29c00 {
1232 compatible = "snps,dw-apb-uart";
1233 reg = <0x01c29c00 0x400>;
1237 clocks = <&apb1_gates 23>;
1238 status = "disabled";
1241 i2c0: i2c@01c2ac00 {
1242 compatible = "allwinner,sun4i-a10-i2c";
1243 reg = <0x01c2ac00 0x400>;
1245 clocks = <&apb1_gates 0>;
1246 status = "disabled";
1247 #address-cells = <1>;
1251 i2c1: i2c@01c2b000 {
1252 compatible = "allwinner,sun4i-a10-i2c";
1253 reg = <0x01c2b000 0x400>;
1255 clocks = <&apb1_gates 1>;
1256 status = "disabled";
1257 #address-cells = <1>;
1261 i2c2: i2c@01c2b400 {
1262 compatible = "allwinner,sun4i-a10-i2c";
1263 reg = <0x01c2b400 0x400>;
1265 clocks = <&apb1_gates 2>;
1266 status = "disabled";
1267 #address-cells = <1>;
1271 ps20: ps2@01c2a000 {
1272 compatible = "allwinner,sun4i-a10-ps2";
1273 reg = <0x01c2a000 0x400>;
1275 clocks = <&apb1_gates 6>;
1276 status = "disabled";
1279 ps21: ps2@01c2a400 {
1280 compatible = "allwinner,sun4i-a10-ps2";
1281 reg = <0x01c2a400 0x400>;
1283 clocks = <&apb1_gates 7>;
1284 status = "disabled";