2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
16 #include <dt-bindings/dma/sun4i-a10.h>
17 #include <dt-bindings/pinctrl/sun4i-a10.h>
20 interrupt-parent = <&intc>;
32 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
33 allwinner,pipeline = "de_be0-lcd0-hdmi";
34 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
40 compatible = "allwinner,simple-framebuffer",
42 allwinner,pipeline = "de_be0-lcd0";
43 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
50 compatible = "arm,cortex-a8";
55 reg = <0x40000000 0x20000000>;
64 * This is a dummy clock, to be used as placeholder on
65 * other mux clocks when a specific parent clock is not
66 * yet implemented. It should be dropped when the driver
71 compatible = "fixed-clock";
72 clock-frequency = <0>;
75 osc24M: clk@01c20050 {
77 compatible = "allwinner,sun4i-a10-osc-clk";
78 reg = <0x01c20050 0x4>;
79 clock-frequency = <24000000>;
80 clock-output-names = "osc24M";
85 compatible = "fixed-clock";
86 clock-frequency = <32768>;
87 clock-output-names = "osc32k";
92 compatible = "allwinner,sun4i-a10-pll1-clk";
93 reg = <0x01c20000 0x4>;
95 clock-output-names = "pll1";
100 compatible = "allwinner,sun4i-a10-pll1-clk";
101 reg = <0x01c20018 0x4>;
103 clock-output-names = "pll4";
108 compatible = "allwinner,sun4i-a10-pll5-clk";
109 reg = <0x01c20020 0x4>;
111 clock-output-names = "pll5_ddr", "pll5_other";
116 compatible = "allwinner,sun4i-a10-pll6-clk";
117 reg = <0x01c20028 0x4>;
119 clock-output-names = "pll6_sata", "pll6_other", "pll6";
125 compatible = "allwinner,sun4i-a10-cpu-clk";
126 reg = <0x01c20054 0x4>;
127 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
128 clock-output-names = "cpu";
133 compatible = "allwinner,sun4i-a10-axi-clk";
134 reg = <0x01c20054 0x4>;
136 clock-output-names = "axi";
139 axi_gates: clk@01c2005c {
141 compatible = "allwinner,sun4i-a10-axi-gates-clk";
142 reg = <0x01c2005c 0x4>;
144 clock-output-names = "axi_dram";
149 compatible = "allwinner,sun4i-a10-ahb-clk";
150 reg = <0x01c20054 0x4>;
152 clock-output-names = "ahb";
155 ahb_gates: clk@01c20060 {
157 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
158 reg = <0x01c20060 0x8>;
160 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
161 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
162 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
163 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
164 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
165 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
166 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
169 apb0: apb0@01c20054 {
171 compatible = "allwinner,sun4i-a10-apb0-clk";
172 reg = <0x01c20054 0x4>;
174 clock-output-names = "apb0";
177 apb0_gates: clk@01c20068 {
179 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
180 reg = <0x01c20068 0x4>;
182 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
183 "apb0_ir", "apb0_keypad";
188 compatible = "allwinner,sun4i-a10-apb1-clk";
189 reg = <0x01c20058 0x4>;
190 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
191 clock-output-names = "apb1";
194 apb1_gates: clk@01c2006c {
196 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
197 reg = <0x01c2006c 0x4>;
199 clock-output-names = "apb1_i2c0", "apb1_i2c1",
200 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
201 "apb1_uart2", "apb1_uart3";
204 nand_clk: clk@01c20080 {
206 compatible = "allwinner,sun4i-a10-mod0-clk";
207 reg = <0x01c20080 0x4>;
208 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
209 clock-output-names = "nand";
212 ms_clk: clk@01c20084 {
214 compatible = "allwinner,sun4i-a10-mod0-clk";
215 reg = <0x01c20084 0x4>;
216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
217 clock-output-names = "ms";
220 mmc0_clk: clk@01c20088 {
222 compatible = "allwinner,sun4i-a10-mmc-clk";
223 reg = <0x01c20088 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "mmc0",
230 mmc1_clk: clk@01c2008c {
232 compatible = "allwinner,sun4i-a10-mmc-clk";
233 reg = <0x01c2008c 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc1",
240 mmc2_clk: clk@01c20090 {
242 compatible = "allwinner,sun4i-a10-mmc-clk";
243 reg = <0x01c20090 0x4>;
244 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
245 clock-output-names = "mmc2",
250 ts_clk: clk@01c20098 {
252 compatible = "allwinner,sun4i-a10-mod0-clk";
253 reg = <0x01c20098 0x4>;
254 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
255 clock-output-names = "ts";
258 ss_clk: clk@01c2009c {
260 compatible = "allwinner,sun4i-a10-mod0-clk";
261 reg = <0x01c2009c 0x4>;
262 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
263 clock-output-names = "ss";
266 spi0_clk: clk@01c200a0 {
268 compatible = "allwinner,sun4i-a10-mod0-clk";
269 reg = <0x01c200a0 0x4>;
270 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
271 clock-output-names = "spi0";
274 spi1_clk: clk@01c200a4 {
276 compatible = "allwinner,sun4i-a10-mod0-clk";
277 reg = <0x01c200a4 0x4>;
278 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
279 clock-output-names = "spi1";
282 spi2_clk: clk@01c200a8 {
284 compatible = "allwinner,sun4i-a10-mod0-clk";
285 reg = <0x01c200a8 0x4>;
286 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
287 clock-output-names = "spi2";
290 ir0_clk: clk@01c200b0 {
292 compatible = "allwinner,sun4i-a10-mod0-clk";
293 reg = <0x01c200b0 0x4>;
294 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
295 clock-output-names = "ir0";
298 usb_clk: clk@01c200cc {
301 compatible = "allwinner,sun5i-a13-usb-clk";
302 reg = <0x01c200cc 0x4>;
304 clock-output-names = "usb_ohci0", "usb_phy";
307 mbus_clk: clk@01c2015c {
309 compatible = "allwinner,sun5i-a13-mbus-clk";
310 reg = <0x01c2015c 0x4>;
311 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
312 clock-output-names = "mbus";
317 compatible = "simple-bus";
318 #address-cells = <1>;
322 dma: dma-controller@01c02000 {
323 compatible = "allwinner,sun4i-a10-dma";
324 reg = <0x01c02000 0x1000>;
326 clocks = <&ahb_gates 6>;
331 compatible = "allwinner,sun4i-a10-spi";
332 reg = <0x01c05000 0x1000>;
334 clocks = <&ahb_gates 20>, <&spi0_clk>;
335 clock-names = "ahb", "mod";
336 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
337 <&dma SUN4I_DMA_DEDICATED 26>;
338 dma-names = "rx", "tx";
340 #address-cells = <1>;
345 compatible = "allwinner,sun4i-a10-spi";
346 reg = <0x01c06000 0x1000>;
348 clocks = <&ahb_gates 21>, <&spi1_clk>;
349 clock-names = "ahb", "mod";
350 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
351 <&dma SUN4I_DMA_DEDICATED 8>;
352 dma-names = "rx", "tx";
354 #address-cells = <1>;
358 emac: ethernet@01c0b000 {
359 compatible = "allwinner,sun4i-a10-emac";
360 reg = <0x01c0b000 0x1000>;
362 clocks = <&ahb_gates 17>;
366 mdio: mdio@01c0b080 {
367 compatible = "allwinner,sun4i-a10-mdio";
368 reg = <0x01c0b080 0x14>;
370 #address-cells = <1>;
375 compatible = "allwinner,sun5i-a13-mmc";
376 reg = <0x01c0f000 0x1000>;
377 clocks = <&ahb_gates 8>,
390 compatible = "allwinner,sun5i-a13-mmc";
391 reg = <0x01c10000 0x1000>;
392 clocks = <&ahb_gates 9>,
405 compatible = "allwinner,sun5i-a13-mmc";
406 reg = <0x01c11000 0x1000>;
407 clocks = <&ahb_gates 10>,
419 usbphy: phy@01c13400 {
421 compatible = "allwinner,sun5i-a13-usb-phy";
422 reg = <0x01c13400 0x10 0x01c14800 0x4>;
423 reg-names = "phy_ctrl", "pmu1";
424 clocks = <&usb_clk 8>;
425 clock-names = "usb_phy";
426 resets = <&usb_clk 0>, <&usb_clk 1>;
427 reset-names = "usb0_reset", "usb1_reset";
431 ehci0: usb@01c14000 {
432 compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
433 reg = <0x01c14000 0x100>;
435 clocks = <&ahb_gates 1>;
441 ohci0: usb@01c14400 {
442 compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
443 reg = <0x01c14400 0x100>;
445 clocks = <&usb_clk 6>, <&ahb_gates 2>;
452 compatible = "allwinner,sun4i-a10-spi";
453 reg = <0x01c17000 0x1000>;
455 clocks = <&ahb_gates 22>, <&spi2_clk>;
456 clock-names = "ahb", "mod";
457 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
458 <&dma SUN4I_DMA_DEDICATED 28>;
459 dma-names = "rx", "tx";
461 #address-cells = <1>;
465 intc: interrupt-controller@01c20400 {
466 compatible = "allwinner,sun4i-a10-ic";
467 reg = <0x01c20400 0x400>;
468 interrupt-controller;
469 #interrupt-cells = <1>;
472 pio: pinctrl@01c20800 {
473 compatible = "allwinner,sun5i-a10s-pinctrl";
474 reg = <0x01c20800 0x400>;
476 clocks = <&apb0_gates 5>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
483 uart0_pins_a: uart0@0 {
484 allwinner,pins = "PB19", "PB20";
485 allwinner,function = "uart0";
486 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
487 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
490 uart2_pins_a: uart2@0 {
491 allwinner,pins = "PC18", "PC19";
492 allwinner,function = "uart2";
493 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
494 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
497 uart3_pins_a: uart3@0 {
498 allwinner,pins = "PG9", "PG10";
499 allwinner,function = "uart3";
500 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
501 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
504 emac_pins_a: emac0@0 {
505 allwinner,pins = "PA0", "PA1", "PA2",
506 "PA3", "PA4", "PA5", "PA6",
507 "PA7", "PA8", "PA9", "PA10",
508 "PA11", "PA12", "PA13", "PA14",
510 allwinner,function = "emac";
511 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
512 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
515 i2c0_pins_a: i2c0@0 {
516 allwinner,pins = "PB0", "PB1";
517 allwinner,function = "i2c0";
518 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
519 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
522 i2c1_pins_a: i2c1@0 {
523 allwinner,pins = "PB15", "PB16";
524 allwinner,function = "i2c1";
525 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
526 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
529 i2c2_pins_a: i2c2@0 {
530 allwinner,pins = "PB17", "PB18";
531 allwinner,function = "i2c2";
532 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
533 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
536 mmc0_pins_a: mmc0@0 {
537 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
538 allwinner,function = "mmc0";
539 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
540 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
543 mmc1_pins_a: mmc1@0 {
544 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
545 allwinner,function = "mmc1";
546 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
547 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
552 compatible = "allwinner,sun4i-a10-timer";
553 reg = <0x01c20c00 0x90>;
558 wdt: watchdog@01c20c90 {
559 compatible = "allwinner,sun4i-a10-wdt";
560 reg = <0x01c20c90 0x10>;
563 lradc: lradc@01c22800 {
564 compatible = "allwinner,sun4i-a10-lradc-keys";
565 reg = <0x01c22800 0x100>;
570 sid: eeprom@01c23800 {
571 compatible = "allwinner,sun4i-a10-sid";
572 reg = <0x01c23800 0x10>;
576 compatible = "allwinner,sun4i-a10-ts";
577 reg = <0x01c25000 0x100>;
579 #thermal-sensor-cells = <0>;
582 uart0: serial@01c28000 {
583 compatible = "snps,dw-apb-uart";
584 reg = <0x01c28000 0x400>;
588 clocks = <&apb1_gates 16>;
592 uart1: serial@01c28400 {
593 compatible = "snps,dw-apb-uart";
594 reg = <0x01c28400 0x400>;
598 clocks = <&apb1_gates 17>;
602 uart2: serial@01c28800 {
603 compatible = "snps,dw-apb-uart";
604 reg = <0x01c28800 0x400>;
608 clocks = <&apb1_gates 18>;
612 uart3: serial@01c28c00 {
613 compatible = "snps,dw-apb-uart";
614 reg = <0x01c28c00 0x400>;
618 clocks = <&apb1_gates 19>;
623 #address-cells = <1>;
625 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
626 reg = <0x01c2ac00 0x400>;
628 clocks = <&apb1_gates 0>;
633 #address-cells = <1>;
635 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
636 reg = <0x01c2b000 0x400>;
638 clocks = <&apb1_gates 1>;
643 #address-cells = <1>;
645 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
646 reg = <0x01c2b400 0x400>;
648 clocks = <&apb1_gates 2>;
653 compatible = "allwinner,sun5i-a13-hstimer";
654 reg = <0x01c60000 0x1000>;
655 interrupts = <82>, <83>;
656 clocks = <&ahb_gates 28>;