arch/arm/boot/dts/sun5i-a13.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "skeleton.dtsi"
  15
  16 #include <dt-bindings/thermal/thermal.h>
  17
  18 #include <dt-bindings/dma/sun4i-a10.h>
  19 #include <dt-bindings/pinctrl/sun4i-a10.h>
  20
  21 / {
  22         interrupt-parent = <&intc>;
  23
  24         chosen {
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27                 ranges;
  28
  29                 framebuffer@0 {
  30                         compatible = "allwinner,simple-framebuffer",
  31                                      "simple-framebuffer";
  32                         allwinner,pipeline = "de_be0-lcd0";
  33                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
  34                         status = "disabled";
  35                 };
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a8";
  45                         reg = <0x0>;
  46                         clocks = <&cpu>;
  47                         clock-latency = <244144>; /* 8 32k periods */
  48                         operating-points = <
  49                                 /* kHz    uV */
  50                                 1008000 1400000
  51                                 912000  1350000
  52                                 864000  1300000
  53                                 624000  1200000
  54                                 576000  1200000
  55                                 432000  1200000
  56                                 >;
  57                         #cooling-cells = <2>;
  58                         cooling-min-level = <0>;
  59                         cooling-max-level = <5>;
  60                 };
  61         };
  62
  63         thermal-zones {
  64                 cpu_thermal {
  65                         /* milliseconds */
  66                         polling-delay-passive = <250>;
  67                         polling-delay = <1000>;
  68                         thermal-sensors = <&rtp>;
  69
  70                         cooling-maps {
  71                                 map0 {
  72                                         trip = <&cpu_alert0>;
  73                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  74                                 };
  75                         };
  76
  77                         trips {
  78                                 cpu_alert0: cpu_alert0 {
  79                                         /* milliCelsius */
  80                                         temperature = <850000>;
  81                                         hysteresis = <2000>;
  82                                         type = "passive";
  83                                 };
  84
  85                                 cpu_crit: cpu_crit {
  86                                         /* milliCelsius */
  87                                         temperature = <100000>;
  88                                         hysteresis = <2000>;
  89                                         type = "critical";
  90                                 };
  91                         };
  92                 };
  93         };
  94
  95         memory {
  96                 reg = <0x40000000 0x20000000>;
  97         };
  98
  99         clocks {
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 /*
 105                  * This is a dummy clock, to be used as placeholder on
 106                  * other mux clocks when a specific parent clock is not
 107                  * yet implemented. It should be dropped when the driver
 108                  * is complete.
 109                  */
 110                 dummy: dummy {
 111                         #clock-cells = <0>;
 112                         compatible = "fixed-clock";
 113                         clock-frequency = <0>;
 114                 };
 115
 116                 osc24M: clk@01c20050 {
 117                         #clock-cells = <0>;
 118                         compatible = "allwinner,sun4i-a10-osc-clk";
 119                         reg = <0x01c20050 0x4>;
 120                         clock-frequency = <24000000>;
 121                         clock-output-names = "osc24M";
 122                 };
 123
 124                 osc32k: clk@0 {
 125                         #clock-cells = <0>;
 126                         compatible = "fixed-clock";
 127                         clock-frequency = <32768>;
 128                         clock-output-names = "osc32k";
 129                 };
 130
 131                 pll1: clk@01c20000 {
 132                         #clock-cells = <0>;
 133                         compatible = "allwinner,sun4i-a10-pll1-clk";
 134                         reg = <0x01c20000 0x4>;
 135                         clocks = <&osc24M>;
 136                         clock-output-names = "pll1";
 137                 };
 138
 139                 pll4: clk@01c20018 {
 140                         #clock-cells = <0>;
 141                         compatible = "allwinner,sun4i-a10-pll1-clk";
 142                         reg = <0x01c20018 0x4>;
 143                         clocks = <&osc24M>;
 144                         clock-output-names = "pll4";
 145                 };
 146
 147                 pll5: clk@01c20020 {
 148                         #clock-cells = <1>;
 149                         compatible = "allwinner,sun4i-a10-pll5-clk";
 150                         reg = <0x01c20020 0x4>;
 151                         clocks = <&osc24M>;
 152                         clock-output-names = "pll5_ddr", "pll5_other";
 153                 };
 154
 155                 pll6: clk@01c20028 {
 156                         #clock-cells = <1>;
 157                         compatible = "allwinner,sun4i-a10-pll6-clk";
 158                         reg = <0x01c20028 0x4>;
 159                         clocks = <&osc24M>;
 160                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 161                 };
 162
 163                 /* dummy is 200M */
 164                 cpu: cpu@01c20054 {
 165                         #clock-cells = <0>;
 166                         compatible = "allwinner,sun4i-a10-cpu-clk";
 167                         reg = <0x01c20054 0x4>;
 168                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 169                         clock-output-names = "cpu";
 170                 };
 171
 172                 axi: axi@01c20054 {
 173                         #clock-cells = <0>;
 174                         compatible = "allwinner,sun4i-a10-axi-clk";
 175                         reg = <0x01c20054 0x4>;
 176                         clocks = <&cpu>;
 177                         clock-output-names = "axi";
 178                 };
 179
 180                 axi_gates: clk@01c2005c {
 181                         #clock-cells = <1>;
 182                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 183                         reg = <0x01c2005c 0x4>;
 184                         clocks = <&axi>;
 185                         clock-output-names = "axi_dram";
 186                 };
 187
 188                 ahb: ahb@01c20054 {
 189                         #clock-cells = <0>;
 190                         compatible = "allwinner,sun4i-a10-ahb-clk";
 191                         reg = <0x01c20054 0x4>;
 192                         clocks = <&axi>;
 193                         clock-output-names = "ahb";
 194                 };
 195
 196                 ahb_gates: clk@01c20060 {
 197                         #clock-cells = <1>;
 198                         compatible = "allwinner,sun5i-a13-ahb-gates-clk";
 199                         reg = <0x01c20060 0x8>;
 200                         clocks = <&ahb>;
 201                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 202                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 203                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 204                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
 205                                 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
 206                                 "ahb_de_fe", "ahb_iep", "ahb_mali400";
 207                 };
 208
 209                 apb0: apb0@01c20054 {
 210                         #clock-cells = <0>;
 211                         compatible = "allwinner,sun4i-a10-apb0-clk";
 212                         reg = <0x01c20054 0x4>;
 213                         clocks = <&ahb>;
 214                         clock-output-names = "apb0";
 215                 };
 216
 217                 apb0_gates: clk@01c20068 {
 218                         #clock-cells = <1>;
 219                         compatible = "allwinner,sun5i-a13-apb0-gates-clk";
 220                         reg = <0x01c20068 0x4>;
 221                         clocks = <&apb0>;
 222                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
 223                 };
 224
 225                 apb1: clk@01c20058 {
 226                         #clock-cells = <0>;
 227                         compatible = "allwinner,sun4i-a10-apb1-clk";
 228                         reg = <0x01c20058 0x4>;
 229                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 230                         clock-output-names = "apb1";
 231                 };
 232
 233                 apb1_gates: clk@01c2006c {
 234                         #clock-cells = <1>;
 235                         compatible = "allwinner,sun5i-a13-apb1-gates-clk";
 236                         reg = <0x01c2006c 0x4>;
 237                         clocks = <&apb1>;
 238                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 239                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
 240                 };
 241
 242                 nand_clk: clk@01c20080 {
 243                         #clock-cells = <0>;
 244                         compatible = "allwinner,sun4i-a10-mod0-clk";
 245                         reg = <0x01c20080 0x4>;
 246                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 247                         clock-output-names = "nand";
 248                 };
 249
 250                 ms_clk: clk@01c20084 {
 251                         #clock-cells = <0>;
 252                         compatible = "allwinner,sun4i-a10-mod0-clk";
 253                         reg = <0x01c20084 0x4>;
 254                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 255                         clock-output-names = "ms";
 256                 };
 257
 258                 mmc0_clk: clk@01c20088 {
 259                         #clock-cells = <1>;
 260                         compatible = "allwinner,sun4i-a10-mmc-clk";
 261                         reg = <0x01c20088 0x4>;
 262                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 263                         clock-output-names = "mmc0",
 264                                              "mmc0_output",
 265                                              "mmc0_sample";
 266                 };
 267
 268                 mmc1_clk: clk@01c2008c {
 269                         #clock-cells = <1>;
 270                         compatible = "allwinner,sun4i-a10-mmc-clk";
 271                         reg = <0x01c2008c 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "mmc1",
 274                                              "mmc1_output",
 275                                              "mmc1_sample";
 276                 };
 277
 278                 mmc2_clk: clk@01c20090 {
 279                         #clock-cells = <1>;
 280                         compatible = "allwinner,sun4i-a10-mmc-clk";
 281                         reg = <0x01c20090 0x4>;
 282                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 283                         clock-output-names = "mmc2",
 284                                              "mmc2_output",
 285                                              "mmc2_sample";
 286                 };
 287
 288                 ts_clk: clk@01c20098 {
 289                         #clock-cells = <0>;
 290                         compatible = "allwinner,sun4i-a10-mod0-clk";
 291                         reg = <0x01c20098 0x4>;
 292                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 293                         clock-output-names = "ts";
 294                 };
 295
 296                 ss_clk: clk@01c2009c {
 297                         #clock-cells = <0>;
 298                         compatible = "allwinner,sun4i-a10-mod0-clk";
 299                         reg = <0x01c2009c 0x4>;
 300                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 301                         clock-output-names = "ss";
 302                 };
 303
 304                 spi0_clk: clk@01c200a0 {
 305                         #clock-cells = <0>;
 306                         compatible = "allwinner,sun4i-a10-mod0-clk";
 307                         reg = <0x01c200a0 0x4>;
 308                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 309                         clock-output-names = "spi0";
 310                 };
 311
 312                 spi1_clk: clk@01c200a4 {
 313                         #clock-cells = <0>;
 314                         compatible = "allwinner,sun4i-a10-mod0-clk";
 315                         reg = <0x01c200a4 0x4>;
 316                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 317                         clock-output-names = "spi1";
 318                 };
 319
 320                 spi2_clk: clk@01c200a8 {
 321                         #clock-cells = <0>;
 322                         compatible = "allwinner,sun4i-a10-mod0-clk";
 323                         reg = <0x01c200a8 0x4>;
 324                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 325                         clock-output-names = "spi2";
 326                 };
 327
 328                 ir0_clk: clk@01c200b0 {
 329                         #clock-cells = <0>;
 330                         compatible = "allwinner,sun4i-a10-mod0-clk";
 331                         reg = <0x01c200b0 0x4>;
 332                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 333                         clock-output-names = "ir0";
 334                 };
 335
 336                 usb_clk: clk@01c200cc {
 337                         #clock-cells = <1>;
 338                         #reset-cells = <1>;
 339                         compatible = "allwinner,sun5i-a13-usb-clk";
 340                         reg = <0x01c200cc 0x4>;
 341                         clocks = <&pll6 1>;
 342                         clock-output-names = "usb_ohci0", "usb_phy";
 343                 };
 344
 345                 mbus_clk: clk@01c2015c {
 346                         #clock-cells = <0>;
 347                         compatible = "allwinner,sun5i-a13-mbus-clk";
 348                         reg = <0x01c2015c 0x4>;
 349                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 350                         clock-output-names = "mbus";
 351                 };
 352         };
 353
 354         soc@01c00000 {
 355                 compatible = "simple-bus";
 356                 #address-cells = <1>;
 357                 #size-cells = <1>;
 358                 ranges;
 359
 360                 dma: dma-controller@01c02000 {
 361                         compatible = "allwinner,sun4i-a10-dma";
 362                         reg = <0x01c02000 0x1000>;
 363                         interrupts = <27>;
 364                         clocks = <&ahb_gates 6>;
 365                         #dma-cells = <2>;
 366                 };
 367
 368                 spi0: spi@01c05000 {
 369                         compatible = "allwinner,sun4i-a10-spi";
 370                         reg = <0x01c05000 0x1000>;
 371                         interrupts = <10>;
 372                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 373                         clock-names = "ahb", "mod";
 374                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 375                                <&dma SUN4I_DMA_DEDICATED 26>;
 376                         dma-names = "rx", "tx";
 377                         status = "disabled";
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                 };
 381
 382                 spi1: spi@01c06000 {
 383                         compatible = "allwinner,sun4i-a10-spi";
 384                         reg = <0x01c06000 0x1000>;
 385                         interrupts = <11>;
 386                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 387                         clock-names = "ahb", "mod";
 388                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 389                                <&dma SUN4I_DMA_DEDICATED 8>;
 390                         dma-names = "rx", "tx";
 391                         status = "disabled";
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                 };
 395
 396                 mmc0: mmc@01c0f000 {
 397                         compatible = "allwinner,sun5i-a13-mmc";
 398                         reg = <0x01c0f000 0x1000>;
 399                         clocks = <&ahb_gates 8>,
 400                                  <&mmc0_clk 0>,
 401                                  <&mmc0_clk 1>,
 402                                  <&mmc0_clk 2>;
 403                         clock-names = "ahb",
 404                                       "mmc",
 405                                       "output",
 406                                       "sample";
 407                         interrupts = <32>;
 408                         status = "disabled";
 409                 };
 410
 411                 mmc2: mmc@01c11000 {
 412                         compatible = "allwinner,sun5i-a13-mmc";
 413                         reg = <0x01c11000 0x1000>;
 414                         clocks = <&ahb_gates 10>,
 415                                  <&mmc2_clk 0>,
 416                                  <&mmc2_clk 1>,
 417                                  <&mmc2_clk 2>;
 418                         clock-names = "ahb",
 419                                       "mmc",
 420                                       "output",
 421                                       "sample";
 422                         interrupts = <34>;
 423                         status = "disabled";
 424                 };
 425
 426                 usbphy: phy@01c13400 {
 427                         #phy-cells = <1>;
 428                         compatible = "allwinner,sun5i-a13-usb-phy";
 429                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 430                         reg-names = "phy_ctrl", "pmu1";
 431                         clocks = <&usb_clk 8>;
 432                         clock-names = "usb_phy";
 433                         resets = <&usb_clk 0>, <&usb_clk 1>;
 434                         reset-names = "usb0_reset", "usb1_reset";
 435                         status = "disabled";
 436                 };
 437
 438                 ehci0: usb@01c14000 {
 439                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 440                         reg = <0x01c14000 0x100>;
 441                         interrupts = <39>;
 442                         clocks = <&ahb_gates 1>;
 443                         phys = <&usbphy 1>;
 444                         phy-names = "usb";
 445                         status = "disabled";
 446                 };
 447
 448                 ohci0: usb@01c14400 {
 449                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 450                         reg = <0x01c14400 0x100>;
 451                         interrupts = <40>;
 452                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 453                         phys = <&usbphy 1>;
 454                         phy-names = "usb";
 455                         status = "disabled";
 456                 };
 457
 458                 spi2: spi@01c17000 {
 459                         compatible = "allwinner,sun4i-a10-spi";
 460                         reg = <0x01c17000 0x1000>;
 461                         interrupts = <12>;
 462                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 463                         clock-names = "ahb", "mod";
 464                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 465                                <&dma SUN4I_DMA_DEDICATED 28>;
 466                         dma-names = "rx", "tx";
 467                         status = "disabled";
 468                         #address-cells = <1>;
 469                         #size-cells = <0>;
 470                 };
 471
 472                 intc: interrupt-controller@01c20400 {
 473                         compatible = "allwinner,sun4i-a10-ic";
 474                         reg = <0x01c20400 0x400>;
 475                         interrupt-controller;
 476                         #interrupt-cells = <1>;
 477                 };
 478
 479                 pio: pinctrl@01c20800 {
 480                         compatible = "allwinner,sun5i-a13-pinctrl";
 481                         reg = <0x01c20800 0x400>;
 482                         interrupts = <28>;
 483                         clocks = <&apb0_gates 5>;
 484                         gpio-controller;
 485                         interrupt-controller;
 486                         #interrupt-cells = <2>;
 487                         #size-cells = <0>;
 488                         #gpio-cells = <3>;
 489
 490                         uart1_pins_a: uart1@0 {
 491                                 allwinner,pins = "PE10", "PE11";
 492                                 allwinner,function = "uart1";
 493                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 494                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 495                         };
 496
 497                         uart1_pins_b: uart1@1 {
 498                                 allwinner,pins = "PG3", "PG4";
 499                                 allwinner,function = "uart1";
 500                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 501                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 502                         };
 503
 504                         i2c0_pins_a: i2c0@0 {
 505                                 allwinner,pins = "PB0", "PB1";
 506                                 allwinner,function = "i2c0";
 507                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 508                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 509                         };
 510
 511                         i2c1_pins_a: i2c1@0 {
 512                                 allwinner,pins = "PB15", "PB16";
 513                                 allwinner,function = "i2c1";
 514                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 515                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 516                         };
 517
 518                         i2c2_pins_a: i2c2@0 {
 519                                 allwinner,pins = "PB17", "PB18";
 520                                 allwinner,function = "i2c2";
 521                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 522                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 523                         };
 524
 525                         mmc0_pins_a: mmc0@0 {
 526                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 527                                 allwinner,function = "mmc0";
 528                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 529                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 530                         };
 531                 };
 532
 533                 timer@01c20c00 {
 534                         compatible = "allwinner,sun4i-a10-timer";
 535                         reg = <0x01c20c00 0x90>;
 536                         interrupts = <22>;
 537                         clocks = <&osc24M>;
 538                 };
 539
 540                 wdt: watchdog@01c20c90 {
 541                         compatible = "allwinner,sun4i-a10-wdt";
 542                         reg = <0x01c20c90 0x10>;
 543                 };
 544
 545                 lradc: lradc@01c22800 {
 546                         compatible = "allwinner,sun4i-a10-lradc-keys";
 547                         reg = <0x01c22800 0x100>;
 548                         interrupts = <31>;
 549                         status = "disabled";
 550                 };
 551
 552                 sid: eeprom@01c23800 {
 553                         compatible = "allwinner,sun4i-a10-sid";
 554                         reg = <0x01c23800 0x10>;
 555                 };
 556
 557                 rtp: rtp@01c25000 {
 558                         compatible = "allwinner,sun4i-a10-ts";
 559                         reg = <0x01c25000 0x100>;
 560                         interrupts = <29>;
 561                         #thermal-sensor-cells = <0>;
 562                 };
 563
 564                 uart1: serial@01c28400 {
 565                         compatible = "snps,dw-apb-uart";
 566                         reg = <0x01c28400 0x400>;
 567                         interrupts = <2>;
 568                         reg-shift = <2>;
 569                         reg-io-width = <4>;
 570                         clocks = <&apb1_gates 17>;
 571                         status = "disabled";
 572                 };
 573
 574                 uart3: serial@01c28c00 {
 575                         compatible = "snps,dw-apb-uart";
 576                         reg = <0x01c28c00 0x400>;
 577                         interrupts = <4>;
 578                         reg-shift = <2>;
 579                         reg-io-width = <4>;
 580                         clocks = <&apb1_gates 19>;
 581                         status = "disabled";
 582                 };
 583
 584                 i2c0: i2c@01c2ac00 {
 585                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 586                         reg = <0x01c2ac00 0x400>;
 587                         interrupts = <7>;
 588                         clocks = <&apb1_gates 0>;
 589                         status = "disabled";
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                 };
 593
 594                 i2c1: i2c@01c2b000 {
 595                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 596                         reg = <0x01c2b000 0x400>;
 597                         interrupts = <8>;
 598                         clocks = <&apb1_gates 1>;
 599                         status = "disabled";
 600                         #address-cells = <1>;
 601                         #size-cells = <0>;
 602                 };
 603
 604                 i2c2: i2c@01c2b400 {
 605                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 606                         reg = <0x01c2b400 0x400>;
 607                         interrupts = <9>;
 608                         clocks = <&apb1_gates 2>;
 609                         status = "disabled";
 610                         #address-cells = <1>;
 611                         #size-cells = <0>;
 612                 };
 613
 614                 timer@01c60000 {
 615                         compatible = "allwinner,sun5i-a13-hstimer";
 616                         reg = <0x01c60000 0x1000>;
 617                         interrupts = <82>, <83>;
 618                         clocks = <&ahb_gates 28>;
 619                 };
 620         };
 621 };