2 * Copyright 2012 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
16 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/dma/sun4i-a10.h>
19 #include <dt-bindings/pinctrl/sun4i-a10.h>
22 interrupt-parent = <&intc>;
30 compatible = "allwinner,simple-framebuffer",
32 allwinner,pipeline = "de_be0-lcd0";
33 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
44 compatible = "arm,cortex-a8";
47 clock-latency = <244144>; /* 8 32k periods */
59 cooling-min-level = <0>;
60 cooling-max-level = <6>;
67 polling-delay-passive = <250>;
68 polling-delay = <1000>;
69 thermal-sensors = <&rtp>;
74 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
79 cpu_alert0: cpu_alert0 {
81 temperature = <850000>;
88 temperature = <100000>;
97 reg = <0x40000000 0x20000000>;
101 #address-cells = <1>;
106 * This is a dummy clock, to be used as placeholder on
107 * other mux clocks when a specific parent clock is not
108 * yet implemented. It should be dropped when the driver
113 compatible = "fixed-clock";
114 clock-frequency = <0>;
117 osc24M: clk@01c20050 {
119 compatible = "allwinner,sun4i-a10-osc-clk";
120 reg = <0x01c20050 0x4>;
121 clock-frequency = <24000000>;
122 clock-output-names = "osc24M";
127 compatible = "fixed-clock";
128 clock-frequency = <32768>;
129 clock-output-names = "osc32k";
134 compatible = "allwinner,sun4i-a10-pll1-clk";
135 reg = <0x01c20000 0x4>;
137 clock-output-names = "pll1";
142 compatible = "allwinner,sun4i-a10-pll1-clk";
143 reg = <0x01c20018 0x4>;
145 clock-output-names = "pll4";
150 compatible = "allwinner,sun4i-a10-pll5-clk";
151 reg = <0x01c20020 0x4>;
153 clock-output-names = "pll5_ddr", "pll5_other";
158 compatible = "allwinner,sun4i-a10-pll6-clk";
159 reg = <0x01c20028 0x4>;
161 clock-output-names = "pll6_sata", "pll6_other", "pll6";
167 compatible = "allwinner,sun4i-a10-cpu-clk";
168 reg = <0x01c20054 0x4>;
169 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
170 clock-output-names = "cpu";
175 compatible = "allwinner,sun4i-a10-axi-clk";
176 reg = <0x01c20054 0x4>;
178 clock-output-names = "axi";
181 axi_gates: clk@01c2005c {
183 compatible = "allwinner,sun4i-a10-axi-gates-clk";
184 reg = <0x01c2005c 0x4>;
186 clock-output-names = "axi_dram";
191 compatible = "allwinner,sun4i-a10-ahb-clk";
192 reg = <0x01c20054 0x4>;
194 clock-output-names = "ahb";
197 ahb_gates: clk@01c20060 {
199 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
200 reg = <0x01c20060 0x8>;
202 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
203 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
204 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
205 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
206 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
207 "ahb_de_fe", "ahb_iep", "ahb_mali400";
210 apb0: apb0@01c20054 {
212 compatible = "allwinner,sun4i-a10-apb0-clk";
213 reg = <0x01c20054 0x4>;
215 clock-output-names = "apb0";
218 apb0_gates: clk@01c20068 {
220 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
221 reg = <0x01c20068 0x4>;
223 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
228 compatible = "allwinner,sun4i-a10-apb1-clk";
229 reg = <0x01c20058 0x4>;
230 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
231 clock-output-names = "apb1";
234 apb1_gates: clk@01c2006c {
236 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
237 reg = <0x01c2006c 0x4>;
239 clock-output-names = "apb1_i2c0", "apb1_i2c1",
240 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
243 nand_clk: clk@01c20080 {
245 compatible = "allwinner,sun4i-a10-mod0-clk";
246 reg = <0x01c20080 0x4>;
247 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
248 clock-output-names = "nand";
251 ms_clk: clk@01c20084 {
253 compatible = "allwinner,sun4i-a10-mod0-clk";
254 reg = <0x01c20084 0x4>;
255 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
256 clock-output-names = "ms";
259 mmc0_clk: clk@01c20088 {
261 compatible = "allwinner,sun4i-a10-mod0-clk";
262 reg = <0x01c20088 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264 clock-output-names = "mmc0";
267 mmc1_clk: clk@01c2008c {
269 compatible = "allwinner,sun4i-a10-mod0-clk";
270 reg = <0x01c2008c 0x4>;
271 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
272 clock-output-names = "mmc1";
275 mmc2_clk: clk@01c20090 {
277 compatible = "allwinner,sun4i-a10-mod0-clk";
278 reg = <0x01c20090 0x4>;
279 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
280 clock-output-names = "mmc2";
283 ts_clk: clk@01c20098 {
285 compatible = "allwinner,sun4i-a10-mod0-clk";
286 reg = <0x01c20098 0x4>;
287 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
288 clock-output-names = "ts";
291 ss_clk: clk@01c2009c {
293 compatible = "allwinner,sun4i-a10-mod0-clk";
294 reg = <0x01c2009c 0x4>;
295 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
296 clock-output-names = "ss";
299 spi0_clk: clk@01c200a0 {
301 compatible = "allwinner,sun4i-a10-mod0-clk";
302 reg = <0x01c200a0 0x4>;
303 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
304 clock-output-names = "spi0";
307 spi1_clk: clk@01c200a4 {
309 compatible = "allwinner,sun4i-a10-mod0-clk";
310 reg = <0x01c200a4 0x4>;
311 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
312 clock-output-names = "spi1";
315 spi2_clk: clk@01c200a8 {
317 compatible = "allwinner,sun4i-a10-mod0-clk";
318 reg = <0x01c200a8 0x4>;
319 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
320 clock-output-names = "spi2";
323 ir0_clk: clk@01c200b0 {
325 compatible = "allwinner,sun4i-a10-mod0-clk";
326 reg = <0x01c200b0 0x4>;
327 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
328 clock-output-names = "ir0";
331 usb_clk: clk@01c200cc {
334 compatible = "allwinner,sun5i-a13-usb-clk";
335 reg = <0x01c200cc 0x4>;
337 clock-output-names = "usb_ohci0", "usb_phy";
340 mbus_clk: clk@01c2015c {
342 compatible = "allwinner,sun5i-a13-mbus-clk";
343 reg = <0x01c2015c 0x4>;
344 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
345 clock-output-names = "mbus";
350 compatible = "simple-bus";
351 #address-cells = <1>;
355 dma: dma-controller@01c02000 {
356 compatible = "allwinner,sun4i-a10-dma";
357 reg = <0x01c02000 0x1000>;
359 clocks = <&ahb_gates 6>;
364 compatible = "allwinner,sun4i-a10-spi";
365 reg = <0x01c05000 0x1000>;
367 clocks = <&ahb_gates 20>, <&spi0_clk>;
368 clock-names = "ahb", "mod";
369 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
370 <&dma SUN4I_DMA_DEDICATED 26>;
371 dma-names = "rx", "tx";
373 #address-cells = <1>;
378 compatible = "allwinner,sun4i-a10-spi";
379 reg = <0x01c06000 0x1000>;
381 clocks = <&ahb_gates 21>, <&spi1_clk>;
382 clock-names = "ahb", "mod";
383 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
384 <&dma SUN4I_DMA_DEDICATED 8>;
385 dma-names = "rx", "tx";
387 #address-cells = <1>;
392 compatible = "allwinner,sun5i-a13-mmc";
393 reg = <0x01c0f000 0x1000>;
394 clocks = <&ahb_gates 8>, <&mmc0_clk>;
395 clock-names = "ahb", "mmc";
401 compatible = "allwinner,sun5i-a13-mmc";
402 reg = <0x01c11000 0x1000>;
403 clocks = <&ahb_gates 10>, <&mmc2_clk>;
404 clock-names = "ahb", "mmc";
409 usbphy: phy@01c13400 {
411 compatible = "allwinner,sun5i-a13-usb-phy";
412 reg = <0x01c13400 0x10 0x01c14800 0x4>;
413 reg-names = "phy_ctrl", "pmu1";
414 clocks = <&usb_clk 8>;
415 clock-names = "usb_phy";
416 resets = <&usb_clk 0>, <&usb_clk 1>;
417 reset-names = "usb0_reset", "usb1_reset";
421 ehci0: usb@01c14000 {
422 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
423 reg = <0x01c14000 0x100>;
425 clocks = <&ahb_gates 1>;
431 ohci0: usb@01c14400 {
432 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
433 reg = <0x01c14400 0x100>;
435 clocks = <&usb_clk 6>, <&ahb_gates 2>;
442 compatible = "allwinner,sun4i-a10-spi";
443 reg = <0x01c17000 0x1000>;
445 clocks = <&ahb_gates 22>, <&spi2_clk>;
446 clock-names = "ahb", "mod";
447 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
448 <&dma SUN4I_DMA_DEDICATED 28>;
449 dma-names = "rx", "tx";
451 #address-cells = <1>;
455 intc: interrupt-controller@01c20400 {
456 compatible = "allwinner,sun4i-a10-ic";
457 reg = <0x01c20400 0x400>;
458 interrupt-controller;
459 #interrupt-cells = <1>;
462 pio: pinctrl@01c20800 {
463 compatible = "allwinner,sun5i-a13-pinctrl";
464 reg = <0x01c20800 0x400>;
466 clocks = <&apb0_gates 5>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
473 uart1_pins_a: uart1@0 {
474 allwinner,pins = "PE10", "PE11";
475 allwinner,function = "uart1";
476 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
477 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
480 uart1_pins_b: uart1@1 {
481 allwinner,pins = "PG3", "PG4";
482 allwinner,function = "uart1";
483 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
484 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
487 i2c0_pins_a: i2c0@0 {
488 allwinner,pins = "PB0", "PB1";
489 allwinner,function = "i2c0";
490 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
491 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
494 i2c1_pins_a: i2c1@0 {
495 allwinner,pins = "PB15", "PB16";
496 allwinner,function = "i2c1";
497 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
498 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
501 i2c2_pins_a: i2c2@0 {
502 allwinner,pins = "PB17", "PB18";
503 allwinner,function = "i2c2";
504 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
505 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
508 mmc0_pins_a: mmc0@0 {
509 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
510 allwinner,function = "mmc0";
511 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
512 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
517 compatible = "allwinner,sun4i-a10-timer";
518 reg = <0x01c20c00 0x90>;
523 wdt: watchdog@01c20c90 {
524 compatible = "allwinner,sun4i-a10-wdt";
525 reg = <0x01c20c90 0x10>;
528 lradc: lradc@01c22800 {
529 compatible = "allwinner,sun4i-a10-lradc-keys";
530 reg = <0x01c22800 0x100>;
535 sid: eeprom@01c23800 {
536 compatible = "allwinner,sun4i-a10-sid";
537 reg = <0x01c23800 0x10>;
541 compatible = "allwinner,sun4i-a10-ts";
542 reg = <0x01c25000 0x100>;
544 #thermal-sensor-cells = <0>;
547 uart1: serial@01c28400 {
548 compatible = "snps,dw-apb-uart";
549 reg = <0x01c28400 0x400>;
553 clocks = <&apb1_gates 17>;
557 uart3: serial@01c28c00 {
558 compatible = "snps,dw-apb-uart";
559 reg = <0x01c28c00 0x400>;
563 clocks = <&apb1_gates 19>;
568 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
569 reg = <0x01c2ac00 0x400>;
571 clocks = <&apb1_gates 0>;
573 #address-cells = <1>;
578 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
579 reg = <0x01c2b000 0x400>;
581 clocks = <&apb1_gates 1>;
583 #address-cells = <1>;
588 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
589 reg = <0x01c2b400 0x400>;
591 clocks = <&apb1_gates 2>;
593 #address-cells = <1>;
598 compatible = "allwinner,sun5i-a13-hstimer";
599 reg = <0x01c60000 0x1000>;
600 interrupts = <82>, <83>;
601 clocks = <&ahb_gates 28>;