arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 serial3 = &uart3;
  24                 serial4 = &uart4;
  25                 serial5 = &uart5;
  26         };
  27
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         compatible = "arm,cortex-a7";
  35                         device_type = "cpu";
  36                         reg = <0>;
  37                 };
  38
  39                 cpu@1 {
  40                         compatible = "arm,cortex-a7";
  41                         device_type = "cpu";
  42                         reg = <1>;
  43                 };
  44
  45                 cpu@2 {
  46                         compatible = "arm,cortex-a7";
  47                         device_type = "cpu";
  48                         reg = <2>;
  49                 };
  50
  51                 cpu@3 {
  52                         compatible = "arm,cortex-a7";
  53                         device_type = "cpu";
  54                         reg = <3>;
  55                 };
  56         };
  57
  58         memory {
  59                 reg = <0x40000000 0x80000000>;
  60         };
  61
  62         pmu {
  63                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
  64                 interrupts = <0 120 4>,
  65                              <0 121 4>,
  66                              <0 122 4>,
  67                              <0 123 4>;
  68         };
  69
  70         clocks {
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 ranges;
  74
  75                 osc24M: osc24M {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <24000000>;
  79                 };
  80
  81                 osc32k: clk@0 {
  82                         #clock-cells = <0>;
  83                         compatible = "fixed-clock";
  84                         clock-frequency = <32768>;
  85                         clock-output-names = "osc32k";
  86                 };
  87
  88                 pll1: clk@01c20000 {
  89                         #clock-cells = <0>;
  90                         compatible = "allwinner,sun6i-a31-pll1-clk";
  91                         reg = <0x01c20000 0x4>;
  92                         clocks = <&osc24M>;
  93                         clock-output-names = "pll1";
  94                 };
  95
  96                 pll6: clk@01c20028 {
  97                         #clock-cells = <0>;
  98                         compatible = "allwinner,sun6i-a31-pll6-clk";
  99                         reg = <0x01c20028 0x4>;
 100                         clocks = <&osc24M>;
 101                         clock-output-names = "pll6";
 102                 };
 103
 104                 cpu: cpu@01c20050 {
 105                         #clock-cells = <0>;
 106                         compatible = "allwinner,sun4i-a10-cpu-clk";
 107                         reg = <0x01c20050 0x4>;
 108
 109                         /*
 110                          * PLL1 is listed twice here.
 111                          * While it looks suspicious, it's actually documented
 112                          * that way both in the datasheet and in the code from
 113                          * Allwinner.
 114                          */
 115                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 116                         clock-output-names = "cpu";
 117                 };
 118
 119                 axi: axi@01c20050 {
 120                         #clock-cells = <0>;
 121                         compatible = "allwinner,sun4i-a10-axi-clk";
 122                         reg = <0x01c20050 0x4>;
 123                         clocks = <&cpu>;
 124                         clock-output-names = "axi";
 125                 };
 126
 127                 ahb1_mux: ahb1_mux@01c20054 {
 128                         #clock-cells = <0>;
 129                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 130                         reg = <0x01c20054 0x4>;
 131                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 132                         clock-output-names = "ahb1_mux";
 133                 };
 134
 135                 ahb1: ahb1@01c20054 {
 136                         #clock-cells = <0>;
 137                         compatible = "allwinner,sun4i-a10-ahb-clk";
 138                         reg = <0x01c20054 0x4>;
 139                         clocks = <&ahb1_mux>;
 140                         clock-output-names = "ahb1";
 141                 };
 142
 143                 ahb1_gates: clk@01c20060 {
 144                         #clock-cells = <1>;
 145                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 146                         reg = <0x01c20060 0x8>;
 147                         clocks = <&ahb1>;
 148                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 149                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 150                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 151                                         "ahb1_nand0", "ahb1_sdram",
 152                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 153                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 154                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 155                                         "ahb1_ehci1", "ahb1_ohci0",
 156                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 157                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 158                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 159                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 160                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 161                                         "ahb1_drc0", "ahb1_drc1";
 162                 };
 163
 164                 apb1: apb1@01c20054 {
 165                         #clock-cells = <0>;
 166                         compatible = "allwinner,sun4i-a10-apb0-clk";
 167                         reg = <0x01c20054 0x4>;
 168                         clocks = <&ahb1>;
 169                         clock-output-names = "apb1";
 170                 };
 171
 172                 apb1_gates: clk@01c20068 {
 173                         #clock-cells = <1>;
 174                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 175                         reg = <0x01c20068 0x4>;
 176                         clocks = <&apb1>;
 177                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 178                                         "apb1_pio", "apb1_daudio0",
 179                                         "apb1_daudio1";
 180                 };
 181
 182                 apb2_mux: apb2_mux@01c20058 {
 183                         #clock-cells = <0>;
 184                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 185                         reg = <0x01c20058 0x4>;
 186                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 187                         clock-output-names = "apb2_mux";
 188                 };
 189
 190                 apb2: apb2@01c20058 {
 191                         #clock-cells = <0>;
 192                         compatible = "allwinner,sun6i-a31-apb2-div-clk";
 193                         reg = <0x01c20058 0x4>;
 194                         clocks = <&apb2_mux>;
 195                         clock-output-names = "apb2";
 196                 };
 197
 198                 apb2_gates: clk@01c2006c {
 199                         #clock-cells = <1>;
 200                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 201                         reg = <0x01c2006c 0x4>;
 202                         clocks = <&apb2>;
 203                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 204                                         "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
 205                                         "apb2_uart1", "apb2_uart2", "apb2_uart3",
 206                                         "apb2_uart4", "apb2_uart5";
 207                 };
 208
 209                 spi0_clk: clk@01c200a0 {
 210                         #clock-cells = <0>;
 211                         compatible = "allwinner,sun4i-a10-mod0-clk";
 212                         reg = <0x01c200a0 0x4>;
 213                         clocks = <&osc24M>, <&pll6>;
 214                         clock-output-names = "spi0";
 215                 };
 216
 217                 spi1_clk: clk@01c200a4 {
 218                         #clock-cells = <0>;
 219                         compatible = "allwinner,sun4i-a10-mod0-clk";
 220                         reg = <0x01c200a4 0x4>;
 221                         clocks = <&osc24M>, <&pll6>;
 222                         clock-output-names = "spi1";
 223                 };
 224
 225                 spi2_clk: clk@01c200a8 {
 226                         #clock-cells = <0>;
 227                         compatible = "allwinner,sun4i-a10-mod0-clk";
 228                         reg = <0x01c200a8 0x4>;
 229                         clocks = <&osc24M>, <&pll6>;
 230                         clock-output-names = "spi2";
 231                 };
 232
 233                 spi3_clk: clk@01c200ac {
 234                         #clock-cells = <0>;
 235                         compatible = "allwinner,sun4i-a10-mod0-clk";
 236                         reg = <0x01c200ac 0x4>;
 237                         clocks = <&osc24M>, <&pll6>;
 238                         clock-output-names = "spi3";
 239                 };
 240         };
 241
 242         soc@01c00000 {
 243                 compatible = "simple-bus";
 244                 #address-cells = <1>;
 245                 #size-cells = <1>;
 246                 ranges;
 247
 248                 dma: dma-controller@01c02000 {
 249                         compatible = "allwinner,sun6i-a31-dma";
 250                         reg = <0x01c02000 0x1000>;
 251                         interrupts = <0 50 4>;
 252                         clocks = <&ahb1_gates 6>;
 253                         resets = <&ahb1_rst 6>;
 254                         #dma-cells = <1>;
 255                 };
 256
 257                 pio: pinctrl@01c20800 {
 258                         compatible = "allwinner,sun6i-a31-pinctrl";
 259                         reg = <0x01c20800 0x400>;
 260                         interrupts = <0 11 4>,
 261                                      <0 15 4>,
 262                                      <0 16 4>,
 263                                      <0 17 4>;
 264                         clocks = <&apb1_gates 5>;
 265                         gpio-controller;
 266                         interrupt-controller;
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                         #gpio-cells = <3>;
 270
 271                         uart0_pins_a: uart0@0 {
 272                                 allwinner,pins = "PH20", "PH21";
 273                                 allwinner,function = "uart0";
 274                                 allwinner,drive = <0>;
 275                                 allwinner,pull = <0>;
 276                         };
 277
 278                         i2c0_pins_a: i2c0@0 {
 279                                 allwinner,pins = "PH14", "PH15";
 280                                 allwinner,function = "i2c0";
 281                                 allwinner,drive = <0>;
 282                                 allwinner,pull = <0>;
 283                         };
 284
 285                         i2c1_pins_a: i2c1@0 {
 286                                 allwinner,pins = "PH16", "PH17";
 287                                 allwinner,function = "i2c1";
 288                                 allwinner,drive = <0>;
 289                                 allwinner,pull = <0>;
 290                         };
 291
 292                         i2c2_pins_a: i2c2@0 {
 293                                 allwinner,pins = "PH18", "PH19";
 294                                 allwinner,function = "i2c2";
 295                                 allwinner,drive = <0>;
 296                                 allwinner,pull = <0>;
 297                         };
 298
 299                         mmc0_pins_a: mmc0@0 {
 300                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 301                                 allwinner,function = "mmc0";
 302                                 allwinner,drive = <2>;
 303                                 allwinner,pull = <0>;
 304                         };
 305                 };
 306
 307                 ahb1_rst: reset@01c202c0 {
 308                         #reset-cells = <1>;
 309                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 310                         reg = <0x01c202c0 0xc>;
 311                 };
 312
 313                 apb1_rst: reset@01c202d0 {
 314                         #reset-cells = <1>;
 315                         compatible = "allwinner,sun6i-a31-clock-reset";
 316                         reg = <0x01c202d0 0x4>;
 317                 };
 318
 319                 apb2_rst: reset@01c202d8 {
 320                         #reset-cells = <1>;
 321                         compatible = "allwinner,sun6i-a31-clock-reset";
 322                         reg = <0x01c202d8 0x4>;
 323                 };
 324
 325                 timer@01c20c00 {
 326                         compatible = "allwinner,sun4i-a10-timer";
 327                         reg = <0x01c20c00 0xa0>;
 328                         interrupts = <0 18 4>,
 329                                      <0 19 4>,
 330                                      <0 20 4>,
 331                                      <0 21 4>,
 332                                      <0 22 4>;
 333                         clocks = <&osc24M>;
 334                 };
 335
 336                 wdt1: watchdog@01c20ca0 {
 337                         compatible = "allwinner,sun6i-a31-wdt";
 338                         reg = <0x01c20ca0 0x20>;
 339                 };
 340
 341                 uart0: serial@01c28000 {
 342                         compatible = "snps,dw-apb-uart";
 343                         reg = <0x01c28000 0x400>;
 344                         interrupts = <0 0 4>;
 345                         reg-shift = <2>;
 346                         reg-io-width = <4>;
 347                         clocks = <&apb2_gates 16>;
 348                         resets = <&apb2_rst 16>;
 349                         dmas = <&dma 6>, <&dma 6>;
 350                         dma-names = "rx", "tx";
 351                         status = "disabled";
 352                 };
 353
 354                 uart1: serial@01c28400 {
 355                         compatible = "snps,dw-apb-uart";
 356                         reg = <0x01c28400 0x400>;
 357                         interrupts = <0 1 4>;
 358                         reg-shift = <2>;
 359                         reg-io-width = <4>;
 360                         clocks = <&apb2_gates 17>;
 361                         resets = <&apb2_rst 17>;
 362                         dmas = <&dma 7>, <&dma 7>;
 363                         dma-names = "rx", "tx";
 364                         status = "disabled";
 365                 };
 366
 367                 uart2: serial@01c28800 {
 368                         compatible = "snps,dw-apb-uart";
 369                         reg = <0x01c28800 0x400>;
 370                         interrupts = <0 2 4>;
 371                         reg-shift = <2>;
 372                         reg-io-width = <4>;
 373                         clocks = <&apb2_gates 18>;
 374                         resets = <&apb2_rst 18>;
 375                         dmas = <&dma 8>, <&dma 8>;
 376                         dma-names = "rx", "tx";
 377                         status = "disabled";
 378                 };
 379
 380                 uart3: serial@01c28c00 {
 381                         compatible = "snps,dw-apb-uart";
 382                         reg = <0x01c28c00 0x400>;
 383                         interrupts = <0 3 4>;
 384                         reg-shift = <2>;
 385                         reg-io-width = <4>;
 386                         clocks = <&apb2_gates 19>;
 387                         resets = <&apb2_rst 19>;
 388                         dmas = <&dma 9>, <&dma 9>;
 389                         dma-names = "rx", "tx";
 390                         status = "disabled";
 391                 };
 392
 393                 uart4: serial@01c29000 {
 394                         compatible = "snps,dw-apb-uart";
 395                         reg = <0x01c29000 0x400>;
 396                         interrupts = <0 4 4>;
 397                         reg-shift = <2>;
 398                         reg-io-width = <4>;
 399                         clocks = <&apb2_gates 20>;
 400                         resets = <&apb2_rst 20>;
 401                         dmas = <&dma 10>, <&dma 10>;
 402                         dma-names = "rx", "tx";
 403                         status = "disabled";
 404                 };
 405
 406                 uart5: serial@01c29400 {
 407                         compatible = "snps,dw-apb-uart";
 408                         reg = <0x01c29400 0x400>;
 409                         interrupts = <0 5 4>;
 410                         reg-shift = <2>;
 411                         reg-io-width = <4>;
 412                         clocks = <&apb2_gates 21>;
 413                         resets = <&apb2_rst 21>;
 414                         dmas = <&dma 22>, <&dma 22>;
 415                         dma-names = "rx", "tx";
 416                         status = "disabled";
 417                 };
 418
 419                 i2c0: i2c@01c2ac00 {
 420                         compatible = "allwinner,sun6i-a31-i2c";
 421                         reg = <0x01c2ac00 0x400>;
 422                         interrupts = <0 6 4>;
 423                         clocks = <&apb2_gates 0>;
 424                         clock-frequency = <100000>;
 425                         resets = <&apb2_rst 0>;
 426                         status = "disabled";
 427                 };
 428
 429                 i2c1: i2c@01c2b000 {
 430                         compatible = "allwinner,sun6i-a31-i2c";
 431                         reg = <0x01c2b000 0x400>;
 432                         interrupts = <0 7 4>;
 433                         clocks = <&apb2_gates 1>;
 434                         clock-frequency = <100000>;
 435                         resets = <&apb2_rst 1>;
 436                         status = "disabled";
 437                 };
 438
 439                 i2c2: i2c@01c2b400 {
 440                         compatible = "allwinner,sun6i-a31-i2c";
 441                         reg = <0x01c2b400 0x400>;
 442                         interrupts = <0 8 4>;
 443                         clocks = <&apb2_gates 2>;
 444                         clock-frequency = <100000>;
 445                         resets = <&apb2_rst 2>;
 446                         status = "disabled";
 447                 };
 448
 449                 i2c3: i2c@01c2b800 {
 450                         compatible = "allwinner,sun6i-a31-i2c";
 451                         reg = <0x01c2b800 0x400>;
 452                         interrupts = <0 9 4>;
 453                         clocks = <&apb2_gates 3>;
 454                         clock-frequency = <100000>;
 455                         resets = <&apb2_rst 3>;
 456                         status = "disabled";
 457                 };
 458
 459                 spi0: spi@01c68000 {
 460                         compatible = "allwinner,sun6i-a31-spi";
 461                         reg = <0x01c68000 0x1000>;
 462                         interrupts = <0 65 4>;
 463                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 464                         clock-names = "ahb", "mod";
 465                         dmas = <&dma 23>, <&dma 23>;
 466                         dma-names = "rx", "tx";
 467                         resets = <&ahb1_rst 20>;
 468                         status = "disabled";
 469                 };
 470
 471                 spi1: spi@01c69000 {
 472                         compatible = "allwinner,sun6i-a31-spi";
 473                         reg = <0x01c69000 0x1000>;
 474                         interrupts = <0 66 4>;
 475                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 476                         clock-names = "ahb", "mod";
 477                         dmas = <&dma 24>, <&dma 24>;
 478                         dma-names = "rx", "tx";
 479                         resets = <&ahb1_rst 21>;
 480                         status = "disabled";
 481                 };
 482
 483                 spi2: spi@01c6a000 {
 484                         compatible = "allwinner,sun6i-a31-spi";
 485                         reg = <0x01c6a000 0x1000>;
 486                         interrupts = <0 67 4>;
 487                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 488                         clock-names = "ahb", "mod";
 489                         dmas = <&dma 25>, <&dma 25>;
 490                         dma-names = "rx", "tx";
 491                         resets = <&ahb1_rst 22>;
 492                         status = "disabled";
 493                 };
 494
 495                 spi3: spi@01c6b000 {
 496                         compatible = "allwinner,sun6i-a31-spi";
 497                         reg = <0x01c6b000 0x1000>;
 498                         interrupts = <0 68 4>;
 499                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 500                         clock-names = "ahb", "mod";
 501                         dmas = <&dma 26>, <&dma 26>;
 502                         dma-names = "rx", "tx";
 503                         resets = <&ahb1_rst 23>;
 504                         status = "disabled";
 505                 };
 506
 507                 gic: interrupt-controller@01c81000 {
 508                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 509                         reg = <0x01c81000 0x1000>,
 510                               <0x01c82000 0x1000>,
 511                               <0x01c84000 0x2000>,
 512                               <0x01c86000 0x2000>;
 513                         interrupt-controller;
 514                         #interrupt-cells = <3>;
 515                         interrupts = <1 9 0xf04>;
 516                 };
 517
 518                 nmi_intc: interrupt-controller@01f00c0c {
 519                         compatible = "allwinner,sun6i-a31-sc-nmi";
 520                         interrupt-controller;
 521                         #interrupt-cells = <2>;
 522                         reg = <0x01f00c0c 0x38>;
 523                         interrupts = <0 32 4>;
 524                 };
 525
 526                 prcm@01f01400 {
 527                         compatible = "allwinner,sun6i-a31-prcm";
 528                         reg = <0x01f01400 0x200>;
 529                 };
 530
 531                 cpucfg@01f01c00 {
 532                         compatible = "allwinner,sun6i-a31-cpuconfig";
 533                         reg = <0x01f01c00 0x300>;
 534                 };
 535         };
 536 };