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Merge tag 'zynq-dt-for-3.19' of https://github.com/Xilinx/linux-xlnx into next/dt
[deliverable/linux.git] / arch / arm / boot / dts / sun6i-a31.dtsi
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50 /include/ "skeleton.dtsi"
51
52 / {
53 interrupt-parent = <&gic>;
54
55 aliases {
56 serial0 = &uart0;
57 serial1 = &uart1;
58 serial2 = &uart2;
59 serial3 = &uart3;
60 serial4 = &uart4;
61 serial5 = &uart5;
62 ethernet0 = &gmac;
63 };
64
65 chosen {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges;
69
70 framebuffer@0 {
71 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
72 allwinner,pipeline = "de_be0-lcd0-hdmi";
73 clocks = <&pll6 0>;
74 status = "disabled";
75 };
76 };
77
78 cpus {
79 enable-method = "allwinner,sun6i-a31";
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 cpu@0 {
84 compatible = "arm,cortex-a7";
85 device_type = "cpu";
86 reg = <0>;
87 };
88
89 cpu@1 {
90 compatible = "arm,cortex-a7";
91 device_type = "cpu";
92 reg = <1>;
93 };
94
95 cpu@2 {
96 compatible = "arm,cortex-a7";
97 device_type = "cpu";
98 reg = <2>;
99 };
100
101 cpu@3 {
102 compatible = "arm,cortex-a7";
103 device_type = "cpu";
104 reg = <3>;
105 };
106 };
107
108 memory {
109 reg = <0x40000000 0x80000000>;
110 };
111
112 pmu {
113 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
114 interrupts = <0 120 4>,
115 <0 121 4>,
116 <0 122 4>,
117 <0 123 4>;
118 };
119
120 clocks {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges;
124
125 osc24M: osc24M {
126 #clock-cells = <0>;
127 compatible = "fixed-clock";
128 clock-frequency = <24000000>;
129 };
130
131 osc32k: clk@0 {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 clock-frequency = <32768>;
135 clock-output-names = "osc32k";
136 };
137
138 pll1: clk@01c20000 {
139 #clock-cells = <0>;
140 compatible = "allwinner,sun6i-a31-pll1-clk";
141 reg = <0x01c20000 0x4>;
142 clocks = <&osc24M>;
143 clock-output-names = "pll1";
144 };
145
146 pll6: clk@01c20028 {
147 #clock-cells = <1>;
148 compatible = "allwinner,sun6i-a31-pll6-clk";
149 reg = <0x01c20028 0x4>;
150 clocks = <&osc24M>;
151 clock-output-names = "pll6", "pll6x2";
152 };
153
154 cpu: cpu@01c20050 {
155 #clock-cells = <0>;
156 compatible = "allwinner,sun4i-a10-cpu-clk";
157 reg = <0x01c20050 0x4>;
158
159 /*
160 * PLL1 is listed twice here.
161 * While it looks suspicious, it's actually documented
162 * that way both in the datasheet and in the code from
163 * Allwinner.
164 */
165 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
166 clock-output-names = "cpu";
167 };
168
169 axi: axi@01c20050 {
170 #clock-cells = <0>;
171 compatible = "allwinner,sun4i-a10-axi-clk";
172 reg = <0x01c20050 0x4>;
173 clocks = <&cpu>;
174 clock-output-names = "axi";
175 };
176
177 ahb1_mux: ahb1_mux@01c20054 {
178 #clock-cells = <0>;
179 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
180 reg = <0x01c20054 0x4>;
181 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
182 clock-output-names = "ahb1_mux";
183 };
184
185 ahb1: ahb1@01c20054 {
186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-a10-ahb-clk";
188 reg = <0x01c20054 0x4>;
189 clocks = <&ahb1_mux>;
190 clock-output-names = "ahb1";
191 };
192
193 ahb1_gates: clk@01c20060 {
194 #clock-cells = <1>;
195 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
196 reg = <0x01c20060 0x8>;
197 clocks = <&ahb1>;
198 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
199 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
200 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
201 "ahb1_nand0", "ahb1_sdram",
202 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
203 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
204 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
205 "ahb1_ehci1", "ahb1_ohci0",
206 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
207 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
208 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
209 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
210 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
211 "ahb1_drc0", "ahb1_drc1";
212 };
213
214 apb1: apb1@01c20054 {
215 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-a10-apb0-clk";
217 reg = <0x01c20054 0x4>;
218 clocks = <&ahb1>;
219 clock-output-names = "apb1";
220 };
221
222 apb1_gates: clk@01c20068 {
223 #clock-cells = <1>;
224 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
225 reg = <0x01c20068 0x4>;
226 clocks = <&apb1>;
227 clock-output-names = "apb1_codec", "apb1_digital_mic",
228 "apb1_pio", "apb1_daudio0",
229 "apb1_daudio1";
230 };
231
232 apb2_mux: apb2_mux@01c20058 {
233 #clock-cells = <0>;
234 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
235 reg = <0x01c20058 0x4>;
236 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
237 clock-output-names = "apb2_mux";
238 };
239
240 apb2: apb2@01c20058 {
241 #clock-cells = <0>;
242 compatible = "allwinner,sun6i-a31-apb2-div-clk";
243 reg = <0x01c20058 0x4>;
244 clocks = <&apb2_mux>;
245 clock-output-names = "apb2";
246 };
247
248 apb2_gates: clk@01c2006c {
249 #clock-cells = <1>;
250 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
251 reg = <0x01c2006c 0x4>;
252 clocks = <&apb2>;
253 clock-output-names = "apb2_i2c0", "apb2_i2c1",
254 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
255 "apb2_uart1", "apb2_uart2", "apb2_uart3",
256 "apb2_uart4", "apb2_uart5";
257 };
258
259 mmc0_clk: clk@01c20088 {
260 #clock-cells = <0>;
261 compatible = "allwinner,sun4i-a10-mod0-clk";
262 reg = <0x01c20088 0x4>;
263 clocks = <&osc24M>, <&pll6 0>;
264 clock-output-names = "mmc0";
265 };
266
267 mmc1_clk: clk@01c2008c {
268 #clock-cells = <0>;
269 compatible = "allwinner,sun4i-a10-mod0-clk";
270 reg = <0x01c2008c 0x4>;
271 clocks = <&osc24M>, <&pll6 0>;
272 clock-output-names = "mmc1";
273 };
274
275 mmc2_clk: clk@01c20090 {
276 #clock-cells = <0>;
277 compatible = "allwinner,sun4i-a10-mod0-clk";
278 reg = <0x01c20090 0x4>;
279 clocks = <&osc24M>, <&pll6 0>;
280 clock-output-names = "mmc2";
281 };
282
283 mmc3_clk: clk@01c20094 {
284 #clock-cells = <0>;
285 compatible = "allwinner,sun4i-a10-mod0-clk";
286 reg = <0x01c20094 0x4>;
287 clocks = <&osc24M>, <&pll6 0>;
288 clock-output-names = "mmc3";
289 };
290
291 spi0_clk: clk@01c200a0 {
292 #clock-cells = <0>;
293 compatible = "allwinner,sun4i-a10-mod0-clk";
294 reg = <0x01c200a0 0x4>;
295 clocks = <&osc24M>, <&pll6 0>;
296 clock-output-names = "spi0";
297 };
298
299 spi1_clk: clk@01c200a4 {
300 #clock-cells = <0>;
301 compatible = "allwinner,sun4i-a10-mod0-clk";
302 reg = <0x01c200a4 0x4>;
303 clocks = <&osc24M>, <&pll6 0>;
304 clock-output-names = "spi1";
305 };
306
307 spi2_clk: clk@01c200a8 {
308 #clock-cells = <0>;
309 compatible = "allwinner,sun4i-a10-mod0-clk";
310 reg = <0x01c200a8 0x4>;
311 clocks = <&osc24M>, <&pll6 0>;
312 clock-output-names = "spi2";
313 };
314
315 spi3_clk: clk@01c200ac {
316 #clock-cells = <0>;
317 compatible = "allwinner,sun4i-a10-mod0-clk";
318 reg = <0x01c200ac 0x4>;
319 clocks = <&osc24M>, <&pll6 0>;
320 clock-output-names = "spi3";
321 };
322
323 usb_clk: clk@01c200cc {
324 #clock-cells = <1>;
325 #reset-cells = <1>;
326 compatible = "allwinner,sun6i-a31-usb-clk";
327 reg = <0x01c200cc 0x4>;
328 clocks = <&osc24M>;
329 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
330 "usb_ohci0", "usb_ohci1",
331 "usb_ohci2";
332 };
333
334 /*
335 * The following two are dummy clocks, placeholders used in the gmac_tx
336 * clock. The gmac driver will choose one parent depending on the PHY
337 * interface mode, using clk_set_rate auto-reparenting.
338 * The actual TX clock rate is not controlled by the gmac_tx clock.
339 */
340 mii_phy_tx_clk: clk@1 {
341 #clock-cells = <0>;
342 compatible = "fixed-clock";
343 clock-frequency = <25000000>;
344 clock-output-names = "mii_phy_tx";
345 };
346
347 gmac_int_tx_clk: clk@2 {
348 #clock-cells = <0>;
349 compatible = "fixed-clock";
350 clock-frequency = <125000000>;
351 clock-output-names = "gmac_int_tx";
352 };
353
354 gmac_tx_clk: clk@01c200d0 {
355 #clock-cells = <0>;
356 compatible = "allwinner,sun7i-a20-gmac-clk";
357 reg = <0x01c200d0 0x4>;
358 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
359 clock-output-names = "gmac_tx";
360 };
361 };
362
363 soc@01c00000 {
364 compatible = "simple-bus";
365 #address-cells = <1>;
366 #size-cells = <1>;
367 ranges;
368
369 dma: dma-controller@01c02000 {
370 compatible = "allwinner,sun6i-a31-dma";
371 reg = <0x01c02000 0x1000>;
372 interrupts = <0 50 4>;
373 clocks = <&ahb1_gates 6>;
374 resets = <&ahb1_rst 6>;
375 #dma-cells = <1>;
376
377 /* DMA controller requires AHB1 clocked from PLL6 */
378 assigned-clocks = <&ahb1_mux>;
379 assigned-clock-parents = <&pll6 0>;
380 };
381
382 mmc0: mmc@01c0f000 {
383 compatible = "allwinner,sun5i-a13-mmc";
384 reg = <0x01c0f000 0x1000>;
385 clocks = <&ahb1_gates 8>, <&mmc0_clk>;
386 clock-names = "ahb", "mmc";
387 resets = <&ahb1_rst 8>;
388 reset-names = "ahb";
389 interrupts = <0 60 4>;
390 status = "disabled";
391 };
392
393 mmc1: mmc@01c10000 {
394 compatible = "allwinner,sun5i-a13-mmc";
395 reg = <0x01c10000 0x1000>;
396 clocks = <&ahb1_gates 9>, <&mmc1_clk>;
397 clock-names = "ahb", "mmc";
398 resets = <&ahb1_rst 9>;
399 reset-names = "ahb";
400 interrupts = <0 61 4>;
401 status = "disabled";
402 };
403
404 mmc2: mmc@01c11000 {
405 compatible = "allwinner,sun5i-a13-mmc";
406 reg = <0x01c11000 0x1000>;
407 clocks = <&ahb1_gates 10>, <&mmc2_clk>;
408 clock-names = "ahb", "mmc";
409 resets = <&ahb1_rst 10>;
410 reset-names = "ahb";
411 interrupts = <0 62 4>;
412 status = "disabled";
413 };
414
415 mmc3: mmc@01c12000 {
416 compatible = "allwinner,sun5i-a13-mmc";
417 reg = <0x01c12000 0x1000>;
418 clocks = <&ahb1_gates 11>, <&mmc3_clk>;
419 clock-names = "ahb", "mmc";
420 resets = <&ahb1_rst 11>;
421 reset-names = "ahb";
422 interrupts = <0 63 4>;
423 status = "disabled";
424 };
425
426 usbphy: phy@01c19400 {
427 compatible = "allwinner,sun6i-a31-usb-phy";
428 reg = <0x01c19400 0x10>,
429 <0x01c1a800 0x4>,
430 <0x01c1b800 0x4>;
431 reg-names = "phy_ctrl",
432 "pmu1",
433 "pmu2";
434 clocks = <&usb_clk 8>,
435 <&usb_clk 9>,
436 <&usb_clk 10>;
437 clock-names = "usb0_phy",
438 "usb1_phy",
439 "usb2_phy";
440 resets = <&usb_clk 0>,
441 <&usb_clk 1>,
442 <&usb_clk 2>;
443 reset-names = "usb0_reset",
444 "usb1_reset",
445 "usb2_reset";
446 status = "disabled";
447 #phy-cells = <1>;
448 };
449
450 ehci0: usb@01c1a000 {
451 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
452 reg = <0x01c1a000 0x100>;
453 interrupts = <0 72 4>;
454 clocks = <&ahb1_gates 26>;
455 resets = <&ahb1_rst 26>;
456 phys = <&usbphy 1>;
457 phy-names = "usb";
458 status = "disabled";
459 };
460
461 ohci0: usb@01c1a400 {
462 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
463 reg = <0x01c1a400 0x100>;
464 interrupts = <0 73 4>;
465 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
466 resets = <&ahb1_rst 29>;
467 phys = <&usbphy 1>;
468 phy-names = "usb";
469 status = "disabled";
470 };
471
472 ehci1: usb@01c1b000 {
473 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
474 reg = <0x01c1b000 0x100>;
475 interrupts = <0 74 4>;
476 clocks = <&ahb1_gates 27>;
477 resets = <&ahb1_rst 27>;
478 phys = <&usbphy 2>;
479 phy-names = "usb";
480 status = "disabled";
481 };
482
483 ohci1: usb@01c1b400 {
484 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
485 reg = <0x01c1b400 0x100>;
486 interrupts = <0 75 4>;
487 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
488 resets = <&ahb1_rst 30>;
489 phys = <&usbphy 2>;
490 phy-names = "usb";
491 status = "disabled";
492 };
493
494 ohci2: usb@01c1c400 {
495 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
496 reg = <0x01c1c400 0x100>;
497 interrupts = <0 77 4>;
498 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
499 resets = <&ahb1_rst 31>;
500 status = "disabled";
501 };
502
503 pio: pinctrl@01c20800 {
504 compatible = "allwinner,sun6i-a31-pinctrl";
505 reg = <0x01c20800 0x400>;
506 interrupts = <0 11 4>,
507 <0 15 4>,
508 <0 16 4>,
509 <0 17 4>;
510 clocks = <&apb1_gates 5>;
511 gpio-controller;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 #size-cells = <0>;
515 #gpio-cells = <3>;
516
517 uart0_pins_a: uart0@0 {
518 allwinner,pins = "PH20", "PH21";
519 allwinner,function = "uart0";
520 allwinner,drive = <0>;
521 allwinner,pull = <0>;
522 };
523
524 i2c0_pins_a: i2c0@0 {
525 allwinner,pins = "PH14", "PH15";
526 allwinner,function = "i2c0";
527 allwinner,drive = <0>;
528 allwinner,pull = <0>;
529 };
530
531 i2c1_pins_a: i2c1@0 {
532 allwinner,pins = "PH16", "PH17";
533 allwinner,function = "i2c1";
534 allwinner,drive = <0>;
535 allwinner,pull = <0>;
536 };
537
538 i2c2_pins_a: i2c2@0 {
539 allwinner,pins = "PH18", "PH19";
540 allwinner,function = "i2c2";
541 allwinner,drive = <0>;
542 allwinner,pull = <0>;
543 };
544
545 mmc0_pins_a: mmc0@0 {
546 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
547 allwinner,function = "mmc0";
548 allwinner,drive = <2>;
549 allwinner,pull = <0>;
550 };
551
552 gmac_pins_mii_a: gmac_mii@0 {
553 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
554 "PA8", "PA9", "PA11",
555 "PA12", "PA13", "PA14", "PA19",
556 "PA20", "PA21", "PA22", "PA23",
557 "PA24", "PA26", "PA27";
558 allwinner,function = "gmac";
559 allwinner,drive = <0>;
560 allwinner,pull = <0>;
561 };
562
563 gmac_pins_gmii_a: gmac_gmii@0 {
564 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
565 "PA4", "PA5", "PA6", "PA7",
566 "PA8", "PA9", "PA10", "PA11",
567 "PA12", "PA13", "PA14", "PA15",
568 "PA16", "PA17", "PA18", "PA19",
569 "PA20", "PA21", "PA22", "PA23",
570 "PA24", "PA25", "PA26", "PA27";
571 allwinner,function = "gmac";
572 /*
573 * data lines in GMII mode run at 125MHz and
574 * might need a higher signal drive strength
575 */
576 allwinner,drive = <2>;
577 allwinner,pull = <0>;
578 };
579
580 gmac_pins_rgmii_a: gmac_rgmii@0 {
581 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
582 "PA9", "PA10", "PA11",
583 "PA12", "PA13", "PA14", "PA19",
584 "PA20", "PA25", "PA26", "PA27";
585 allwinner,function = "gmac";
586 /*
587 * data lines in RGMII mode use DDR mode
588 * and need a higher signal drive strength
589 */
590 allwinner,drive = <3>;
591 allwinner,pull = <0>;
592 };
593 };
594
595 ahb1_rst: reset@01c202c0 {
596 #reset-cells = <1>;
597 compatible = "allwinner,sun6i-a31-ahb1-reset";
598 reg = <0x01c202c0 0xc>;
599 };
600
601 apb1_rst: reset@01c202d0 {
602 #reset-cells = <1>;
603 compatible = "allwinner,sun6i-a31-clock-reset";
604 reg = <0x01c202d0 0x4>;
605 };
606
607 apb2_rst: reset@01c202d8 {
608 #reset-cells = <1>;
609 compatible = "allwinner,sun6i-a31-clock-reset";
610 reg = <0x01c202d8 0x4>;
611 };
612
613 timer@01c20c00 {
614 compatible = "allwinner,sun4i-a10-timer";
615 reg = <0x01c20c00 0xa0>;
616 interrupts = <0 18 4>,
617 <0 19 4>,
618 <0 20 4>,
619 <0 21 4>,
620 <0 22 4>;
621 clocks = <&osc24M>;
622 };
623
624 wdt1: watchdog@01c20ca0 {
625 compatible = "allwinner,sun6i-a31-wdt";
626 reg = <0x01c20ca0 0x20>;
627 };
628
629 uart0: serial@01c28000 {
630 compatible = "snps,dw-apb-uart";
631 reg = <0x01c28000 0x400>;
632 interrupts = <0 0 4>;
633 reg-shift = <2>;
634 reg-io-width = <4>;
635 clocks = <&apb2_gates 16>;
636 resets = <&apb2_rst 16>;
637 dmas = <&dma 6>, <&dma 6>;
638 dma-names = "rx", "tx";
639 status = "disabled";
640 };
641
642 uart1: serial@01c28400 {
643 compatible = "snps,dw-apb-uart";
644 reg = <0x01c28400 0x400>;
645 interrupts = <0 1 4>;
646 reg-shift = <2>;
647 reg-io-width = <4>;
648 clocks = <&apb2_gates 17>;
649 resets = <&apb2_rst 17>;
650 dmas = <&dma 7>, <&dma 7>;
651 dma-names = "rx", "tx";
652 status = "disabled";
653 };
654
655 uart2: serial@01c28800 {
656 compatible = "snps,dw-apb-uart";
657 reg = <0x01c28800 0x400>;
658 interrupts = <0 2 4>;
659 reg-shift = <2>;
660 reg-io-width = <4>;
661 clocks = <&apb2_gates 18>;
662 resets = <&apb2_rst 18>;
663 dmas = <&dma 8>, <&dma 8>;
664 dma-names = "rx", "tx";
665 status = "disabled";
666 };
667
668 uart3: serial@01c28c00 {
669 compatible = "snps,dw-apb-uart";
670 reg = <0x01c28c00 0x400>;
671 interrupts = <0 3 4>;
672 reg-shift = <2>;
673 reg-io-width = <4>;
674 clocks = <&apb2_gates 19>;
675 resets = <&apb2_rst 19>;
676 dmas = <&dma 9>, <&dma 9>;
677 dma-names = "rx", "tx";
678 status = "disabled";
679 };
680
681 uart4: serial@01c29000 {
682 compatible = "snps,dw-apb-uart";
683 reg = <0x01c29000 0x400>;
684 interrupts = <0 4 4>;
685 reg-shift = <2>;
686 reg-io-width = <4>;
687 clocks = <&apb2_gates 20>;
688 resets = <&apb2_rst 20>;
689 dmas = <&dma 10>, <&dma 10>;
690 dma-names = "rx", "tx";
691 status = "disabled";
692 };
693
694 uart5: serial@01c29400 {
695 compatible = "snps,dw-apb-uart";
696 reg = <0x01c29400 0x400>;
697 interrupts = <0 5 4>;
698 reg-shift = <2>;
699 reg-io-width = <4>;
700 clocks = <&apb2_gates 21>;
701 resets = <&apb2_rst 21>;
702 dmas = <&dma 22>, <&dma 22>;
703 dma-names = "rx", "tx";
704 status = "disabled";
705 };
706
707 i2c0: i2c@01c2ac00 {
708 compatible = "allwinner,sun6i-a31-i2c";
709 reg = <0x01c2ac00 0x400>;
710 interrupts = <0 6 4>;
711 clocks = <&apb2_gates 0>;
712 resets = <&apb2_rst 0>;
713 status = "disabled";
714 #address-cells = <1>;
715 #size-cells = <0>;
716 };
717
718 i2c1: i2c@01c2b000 {
719 compatible = "allwinner,sun6i-a31-i2c";
720 reg = <0x01c2b000 0x400>;
721 interrupts = <0 7 4>;
722 clocks = <&apb2_gates 1>;
723 resets = <&apb2_rst 1>;
724 status = "disabled";
725 #address-cells = <1>;
726 #size-cells = <0>;
727 };
728
729 i2c2: i2c@01c2b400 {
730 compatible = "allwinner,sun6i-a31-i2c";
731 reg = <0x01c2b400 0x400>;
732 interrupts = <0 8 4>;
733 clocks = <&apb2_gates 2>;
734 resets = <&apb2_rst 2>;
735 status = "disabled";
736 #address-cells = <1>;
737 #size-cells = <0>;
738 };
739
740 i2c3: i2c@01c2b800 {
741 compatible = "allwinner,sun6i-a31-i2c";
742 reg = <0x01c2b800 0x400>;
743 interrupts = <0 9 4>;
744 clocks = <&apb2_gates 3>;
745 resets = <&apb2_rst 3>;
746 status = "disabled";
747 #address-cells = <1>;
748 #size-cells = <0>;
749 };
750
751 gmac: ethernet@01c30000 {
752 compatible = "allwinner,sun7i-a20-gmac";
753 reg = <0x01c30000 0x1054>;
754 interrupts = <0 82 4>;
755 interrupt-names = "macirq";
756 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
757 clock-names = "stmmaceth", "allwinner_gmac_tx";
758 resets = <&ahb1_rst 17>;
759 reset-names = "stmmaceth";
760 snps,pbl = <2>;
761 snps,fixed-burst;
762 snps,force_sf_dma_mode;
763 status = "disabled";
764 #address-cells = <1>;
765 #size-cells = <0>;
766 };
767
768 timer@01c60000 {
769 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
770 reg = <0x01c60000 0x1000>;
771 interrupts = <0 51 4>,
772 <0 52 4>,
773 <0 53 4>,
774 <0 54 4>;
775 clocks = <&ahb1_gates 19>;
776 resets = <&ahb1_rst 19>;
777 };
778
779 spi0: spi@01c68000 {
780 compatible = "allwinner,sun6i-a31-spi";
781 reg = <0x01c68000 0x1000>;
782 interrupts = <0 65 4>;
783 clocks = <&ahb1_gates 20>, <&spi0_clk>;
784 clock-names = "ahb", "mod";
785 dmas = <&dma 23>, <&dma 23>;
786 dma-names = "rx", "tx";
787 resets = <&ahb1_rst 20>;
788 status = "disabled";
789 };
790
791 spi1: spi@01c69000 {
792 compatible = "allwinner,sun6i-a31-spi";
793 reg = <0x01c69000 0x1000>;
794 interrupts = <0 66 4>;
795 clocks = <&ahb1_gates 21>, <&spi1_clk>;
796 clock-names = "ahb", "mod";
797 dmas = <&dma 24>, <&dma 24>;
798 dma-names = "rx", "tx";
799 resets = <&ahb1_rst 21>;
800 status = "disabled";
801 };
802
803 spi2: spi@01c6a000 {
804 compatible = "allwinner,sun6i-a31-spi";
805 reg = <0x01c6a000 0x1000>;
806 interrupts = <0 67 4>;
807 clocks = <&ahb1_gates 22>, <&spi2_clk>;
808 clock-names = "ahb", "mod";
809 dmas = <&dma 25>, <&dma 25>;
810 dma-names = "rx", "tx";
811 resets = <&ahb1_rst 22>;
812 status = "disabled";
813 };
814
815 spi3: spi@01c6b000 {
816 compatible = "allwinner,sun6i-a31-spi";
817 reg = <0x01c6b000 0x1000>;
818 interrupts = <0 68 4>;
819 clocks = <&ahb1_gates 23>, <&spi3_clk>;
820 clock-names = "ahb", "mod";
821 dmas = <&dma 26>, <&dma 26>;
822 dma-names = "rx", "tx";
823 resets = <&ahb1_rst 23>;
824 status = "disabled";
825 };
826
827 gic: interrupt-controller@01c81000 {
828 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
829 reg = <0x01c81000 0x1000>,
830 <0x01c82000 0x1000>,
831 <0x01c84000 0x2000>,
832 <0x01c86000 0x2000>;
833 interrupt-controller;
834 #interrupt-cells = <3>;
835 interrupts = <1 9 0xf04>;
836 };
837
838 rtc: rtc@01f00000 {
839 compatible = "allwinner,sun6i-a31-rtc";
840 reg = <0x01f00000 0x54>;
841 interrupts = <0 40 4>, <0 41 4>;
842 };
843
844 nmi_intc: interrupt-controller@01f00c0c {
845 compatible = "allwinner,sun6i-a31-sc-nmi";
846 interrupt-controller;
847 #interrupt-cells = <2>;
848 reg = <0x01f00c0c 0x38>;
849 interrupts = <0 32 4>;
850 };
851
852 prcm@01f01400 {
853 compatible = "allwinner,sun6i-a31-prcm";
854 reg = <0x01f01400 0x200>;
855
856 ar100: ar100_clk {
857 compatible = "allwinner,sun6i-a31-ar100-clk";
858 #clock-cells = <0>;
859 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
860 clock-output-names = "ar100";
861 };
862
863 ahb0: ahb0_clk {
864 compatible = "fixed-factor-clock";
865 #clock-cells = <0>;
866 clock-div = <1>;
867 clock-mult = <1>;
868 clocks = <&ar100>;
869 clock-output-names = "ahb0";
870 };
871
872 apb0: apb0_clk {
873 compatible = "allwinner,sun6i-a31-apb0-clk";
874 #clock-cells = <0>;
875 clocks = <&ahb0>;
876 clock-output-names = "apb0";
877 };
878
879 apb0_gates: apb0_gates_clk {
880 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
881 #clock-cells = <1>;
882 clocks = <&apb0>;
883 clock-output-names = "apb0_pio", "apb0_ir",
884 "apb0_timer", "apb0_p2wi",
885 "apb0_uart", "apb0_1wire",
886 "apb0_i2c";
887 };
888
889 apb0_rst: apb0_rst {
890 compatible = "allwinner,sun6i-a31-clock-reset";
891 #reset-cells = <1>;
892 };
893 };
894
895 cpucfg@01f01c00 {
896 compatible = "allwinner,sun6i-a31-cpuconfig";
897 reg = <0x01f01c00 0x300>;
898 };
899
900 r_pio: pinctrl@01f02c00 {
901 compatible = "allwinner,sun6i-a31-r-pinctrl";
902 reg = <0x01f02c00 0x400>;
903 interrupts = <0 45 4>,
904 <0 46 4>;
905 clocks = <&apb0_gates 0>;
906 resets = <&apb0_rst 0>;
907 gpio-controller;
908 interrupt-controller;
909 #interrupt-cells = <2>;
910 #size-cells = <0>;
911 #gpio-cells = <3>;
912 };
913 };
914 };
Linux kernel - Deliverables
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