arch/arm/boot/dts/sun8i-a23.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 serial2 = &uart2;
  23                 serial3 = &uart3;
  24                 serial4 = &uart4;
  25                 serial5 = &r_uart;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         compatible = "arm,cortex-a7";
  34                         device_type = "cpu";
  35                         reg = <0>;
  36                 };
  37
  38                 cpu@1 {
  39                         compatible = "arm,cortex-a7";
  40                         device_type = "cpu";
  41                         reg = <1>;
  42                 };
  43         };
  44
  45         memory {
  46                 reg = <0x40000000 0x40000000>;
  47         };
  48
  49         clocks {
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 ranges;
  53
  54                 osc24M: osc24M_clk {
  55                         #clock-cells = <0>;
  56                         compatible = "fixed-clock";
  57                         clock-frequency = <24000000>;
  58                         clock-output-names = "osc24M";
  59                 };
  60
  61                 osc32k: osc32k_clk {
  62                         #clock-cells = <0>;
  63                         compatible = "fixed-clock";
  64                         clock-frequency = <32768>;
  65                         clock-output-names = "osc32k";
  66                 };
  67
  68                 pll1: clk@01c20000 {
  69                         #clock-cells = <0>;
  70                         compatible = "allwinner,sun8i-a23-pll1-clk";
  71                         reg = <0x01c20000 0x4>;
  72                         clocks = <&osc24M>;
  73                         clock-output-names = "pll1";
  74                 };
  75
  76                 /* dummy clock until actually implemented */
  77                 pll6: pll6_clk {
  78                         #clock-cells = <0>;
  79                         compatible = "fixed-clock";
  80                         clock-frequency = <600000000>;
  81                         clock-output-names = "pll6";
  82                 };
  83
  84                 cpu: cpu_clk@01c20050 {
  85                         #clock-cells = <0>;
  86                         compatible = "allwinner,sun4i-a10-cpu-clk";
  87                         reg = <0x01c20050 0x4>;
  88
  89                         /*
  90                          * PLL1 is listed twice here.
  91                          * While it looks suspicious, it's actually documented
  92                          * that way both in the datasheet and in the code from
  93                          * Allwinner.
  94                          */
  95                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
  96                         clock-output-names = "cpu";
  97                 };
  98
  99                 axi: axi_clk@01c20050 {
 100                         #clock-cells = <0>;
 101                         compatible = "allwinner,sun8i-a23-axi-clk";
 102                         reg = <0x01c20050 0x4>;
 103                         clocks = <&cpu>;
 104                         clock-output-names = "axi";
 105                 };
 106
 107                 ahb1_mux: ahb1_mux_clk@01c20054 {
 108                         #clock-cells = <0>;
 109                         compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
 110                         reg = <0x01c20054 0x4>;
 111                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 112                         clock-output-names = "ahb1_mux";
 113                 };
 114
 115                 ahb1: ahb1_clk@01c20054 {
 116                         #clock-cells = <0>;
 117                         compatible = "allwinner,sun4i-a10-ahb-clk";
 118                         reg = <0x01c20054 0x4>;
 119                         clocks = <&ahb1_mux>;
 120                         clock-output-names = "ahb1";
 121                 };
 122
 123                 apb1: apb1_clk@01c20054 {
 124                         #clock-cells = <0>;
 125                         compatible = "allwinner,sun4i-a10-apb0-clk";
 126                         reg = <0x01c20054 0x4>;
 127                         clocks = <&ahb1>;
 128                         clock-output-names = "apb1";
 129                 };
 130
 131                 ahb1_gates: clk@01c20060 {
 132                         #clock-cells = <1>;
 133                         compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
 134                         reg = <0x01c20060 0x8>;
 135                         clocks = <&ahb1>;
 136                         clock-output-names = "ahb1_mipidsi", "ahb1_dma",
 137                                         "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
 138                                         "ahb1_nand", "ahb1_sdram",
 139                                         "ahb1_hstimer", "ahb1_spi0",
 140                                         "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
 141                                         "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
 142                                         "ahb1_csi", "ahb1_be",  "ahb1_fe",
 143                                         "ahb1_gpu", "ahb1_spinlock",
 144                                         "ahb1_drc";
 145                 };
 146
 147                 apb1_gates: clk@01c20068 {
 148                         #clock-cells = <1>;
 149                         compatible = "allwinner,sun8i-a23-apb1-gates-clk";
 150                         reg = <0x01c20068 0x4>;
 151                         clocks = <&apb1>;
 152                         clock-output-names = "apb1_codec", "apb1_pio",
 153                                         "apb1_daudio0", "apb1_daudio1";
 154                 };
 155
 156                 apb2_mux: apb2_mux_clk@01c20058 {
 157                         #clock-cells = <0>;
 158                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 159                         reg = <0x01c20058 0x4>;
 160                         clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
 161                         clock-output-names = "apb2_mux";
 162                 };
 163
 164                 apb2: apb2_clk@01c20058 {
 165                         #clock-cells = <0>;
 166                         compatible = "allwinner,sun6i-a31-apb2-div-clk";
 167                         reg = <0x01c20058 0x4>;
 168                         clocks = <&apb2_mux>;
 169                         clock-output-names = "apb2";
 170                 };
 171
 172                 apb2_gates: clk@01c2006c {
 173                         #clock-cells = <1>;
 174                         compatible = "allwinner,sun8i-a23-apb2-gates-clk";
 175                         reg = <0x01c2006c 0x4>;
 176                         clocks = <&apb2>;
 177                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 178                                         "apb2_i2c2", "apb2_uart0",
 179                                         "apb2_uart1", "apb2_uart2",
 180                                         "apb2_uart3", "apb2_uart4";
 181                 };
 182         };
 183
 184         soc@01c00000 {
 185                 compatible = "simple-bus";
 186                 #address-cells = <1>;
 187                 #size-cells = <1>;
 188                 ranges;
 189
 190                 ahb1_rst: reset@01c202c0 {
 191                         #reset-cells = <1>;
 192                         compatible = "allwinner,sun6i-a31-clock-reset";
 193                         reg = <0x01c202c0 0xc>;
 194                 };
 195
 196                 apb1_rst: reset@01c202d0 {
 197                         #reset-cells = <1>;
 198                         compatible = "allwinner,sun6i-a31-clock-reset";
 199                         reg = <0x01c202d0 0x4>;
 200                 };
 201
 202                 apb2_rst: reset@01c202d8 {
 203                         #reset-cells = <1>;
 204                         compatible = "allwinner,sun6i-a31-clock-reset";
 205                         reg = <0x01c202d8 0x4>;
 206                 };
 207
 208                 timer@01c20c00 {
 209                         compatible = "allwinner,sun4i-a10-timer";
 210                         reg = <0x01c20c00 0xa0>;
 211                         interrupts = <0 18 4>,
 212                                      <0 19 4>;
 213                         clocks = <&osc24M>;
 214                 };
 215
 216                 wdt0: watchdog@01c20ca0 {
 217                         compatible = "allwinner,sun6i-a31-wdt";
 218                         reg = <0x01c20ca0 0x20>;
 219                         interrupts = <0 25 4>;
 220                 };
 221
 222                 uart0: serial@01c28000 {
 223                         compatible = "snps,dw-apb-uart";
 224                         reg = <0x01c28000 0x400>;
 225                         interrupts = <0 0 4>;
 226                         reg-shift = <2>;
 227                         reg-io-width = <4>;
 228                         clocks = <&apb2_gates 16>;
 229                         resets = <&apb2_rst 16>;
 230                         status = "disabled";
 231                 };
 232
 233                 uart1: serial@01c28400 {
 234                         compatible = "snps,dw-apb-uart";
 235                         reg = <0x01c28400 0x400>;
 236                         interrupts = <0 1 4>;
 237                         reg-shift = <2>;
 238                         reg-io-width = <4>;
 239                         clocks = <&apb2_gates 17>;
 240                         resets = <&apb2_rst 17>;
 241                         status = "disabled";
 242                 };
 243
 244                 uart2: serial@01c28800 {
 245                         compatible = "snps,dw-apb-uart";
 246                         reg = <0x01c28800 0x400>;
 247                         interrupts = <0 2 4>;
 248                         reg-shift = <2>;
 249                         reg-io-width = <4>;
 250                         clocks = <&apb2_gates 18>;
 251                         resets = <&apb2_rst 18>;
 252                         status = "disabled";
 253                 };
 254
 255                 uart3: serial@01c28c00 {
 256                         compatible = "snps,dw-apb-uart";
 257                         reg = <0x01c28c00 0x400>;
 258                         interrupts = <0 3 4>;
 259                         reg-shift = <2>;
 260                         reg-io-width = <4>;
 261                         clocks = <&apb2_gates 19>;
 262                         resets = <&apb2_rst 19>;
 263                         status = "disabled";
 264                 };
 265
 266                 uart4: serial@01c29000 {
 267                         compatible = "snps,dw-apb-uart";
 268                         reg = <0x01c29000 0x400>;
 269                         interrupts = <0 4 4>;
 270                         reg-shift = <2>;
 271                         reg-io-width = <4>;
 272                         clocks = <&apb2_gates 20>;
 273                         resets = <&apb2_rst 20>;
 274                         status = "disabled";
 275                 };
 276
 277                 gic: interrupt-controller@01c81000 {
 278                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 279                         reg = <0x01c81000 0x1000>,
 280                               <0x01c82000 0x1000>,
 281                               <0x01c84000 0x2000>,
 282                               <0x01c86000 0x2000>;
 283                         interrupt-controller;
 284                         #interrupt-cells = <3>;
 285                         interrupts = <1 9 0xf04>;
 286                 };
 287
 288                 prcm@01f01400 {
 289                         compatible = "allwinner,sun8i-a23-prcm";
 290                         reg = <0x01f01400 0x200>;
 291
 292                         ar100: ar100_clk {
 293                                 compatible = "fixed-factor-clock";
 294                                 #clock-cells = <0>;
 295                                 clock-div = <1>;
 296                                 clock-mult = <1>;
 297                                 clocks = <&osc24M>;
 298                                 clock-output-names = "ar100";
 299                         };
 300
 301                         ahb0: ahb0_clk {
 302                                 compatible = "fixed-factor-clock";
 303                                 #clock-cells = <0>;
 304                                 clock-div = <1>;
 305                                 clock-mult = <1>;
 306                                 clocks = <&ar100>;
 307                                 clock-output-names = "ahb0";
 308                         };
 309
 310                         apb0: apb0_clk {
 311                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 312                                 #clock-cells = <0>;
 313                                 clocks = <&ahb0>;
 314                                 clock-output-names = "apb0";
 315                         };
 316
 317                         apb0_gates: apb0_gates_clk {
 318                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 319                                 #clock-cells = <1>;
 320                                 clocks = <&apb0>;
 321                                 clock-output-names = "apb0_pio", "apb0_timer",
 322                                                 "apb0_rsb", "apb0_uart",
 323                                                 "apb0_i2c";
 324                         };
 325
 326                         apb0_rst: apb0_rst {
 327                                 compatible = "allwinner,sun6i-a31-clock-reset";
 328                                 #reset-cells = <1>;
 329                         };
 330                 };
 331
 332                 r_uart: serial@01f02800 {
 333                         compatible = "snps,dw-apb-uart";
 334                         reg = <0x01f02800 0x400>;
 335                         interrupts = <0 38 4>;
 336                         reg-shift = <2>;
 337                         reg-io-width = <4>;
 338                         clocks = <&apb0_gates 4>;
 339                         resets = <&apb0_rst 4>;
 340                         status = "disabled";
 341                 };
 342         };
 343 };