arch/arm/boot/dts/tegra114.dtsi

   1 #include <dt-bindings/clock/tegra114-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra114";
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uarta;
  14                 serial1 = &uartb;
  15                 serial2 = &uartc;
  16                 serial3 = &uartd;
  17         };
  18
  19         host1x@50000000 {
  20                 compatible = "nvidia,tegra114-host1x", "simple-bus";
  21                 reg = <0x50000000 0x00028000>;
  22                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  23                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  24                 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
  25                 resets = <&tegra_car 28>;
  26                 reset-names = "host1x";
  27
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30
  31                 ranges = <0x54000000 0x54000000 0x01000000>;
  32
  33                 gr2d@54140000 {
  34                         compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
  35                         reg = <0x54140000 0x00040000>;
  36                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  37                         clocks = <&tegra_car TEGRA114_CLK_GR2D>;
  38                         resets = <&tegra_car 21>;
  39                         reset-names = "2d";
  40                 };
  41
  42                 gr3d@54180000 {
  43                         compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
  44                         reg = <0x54180000 0x00040000>;
  45                         clocks = <&tegra_car TEGRA114_CLK_GR3D>;
  46                         resets = <&tegra_car 24>;
  47                         reset-names = "3d";
  48                 };
  49
  50                 dc@54200000 {
  51                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  52                         reg = <0x54200000 0x00040000>;
  53                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&tegra_car TEGRA114_CLK_DISP1>,
  55                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  56                         clock-names = "dc", "parent";
  57                         resets = <&tegra_car 27>;
  58                         reset-names = "dc";
  59
  60                         nvidia,head = <0>;
  61
  62                         rgb {
  63                                 status = "disabled";
  64                         };
  65                 };
  66
  67                 dc@54240000 {
  68                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  69                         reg = <0x54240000 0x00040000>;
  70                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  71                         clocks = <&tegra_car TEGRA114_CLK_DISP2>,
  72                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  73                         clock-names = "dc", "parent";
  74                         resets = <&tegra_car 26>;
  75                         reset-names = "dc";
  76
  77                         nvidia,head = <1>;
  78
  79                         rgb {
  80                                 status = "disabled";
  81                         };
  82                 };
  83
  84                 hdmi@54280000 {
  85                         compatible = "nvidia,tegra114-hdmi";
  86                         reg = <0x54280000 0x00040000>;
  87                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  88                         clocks = <&tegra_car TEGRA114_CLK_HDMI>,
  89                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
  90                         clock-names = "hdmi", "parent";
  91                         resets = <&tegra_car 51>;
  92                         reset-names = "hdmi";
  93                         status = "disabled";
  94                 };
  95
  96                 dsi@54300000 {
  97                         compatible = "nvidia,tegra114-dsi";
  98                         reg = <0x54300000 0x00040000>;
  99                         clocks = <&tegra_car TEGRA114_CLK_DSIA>,
 100                                  <&tegra_car TEGRA114_CLK_DSIALP>,
 101                                  <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
 102                         clock-names = "dsi", "lp", "parent";
 103                         resets = <&tegra_car 48>;
 104                         reset-names = "dsi";
 105                         nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
 106                         status = "disabled";
 107
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                 };
 111
 112                 dsi@54400000 {
 113                         compatible = "nvidia,tegra114-dsi";
 114                         reg = <0x54400000 0x00040000>;
 115                         clocks = <&tegra_car TEGRA114_CLK_DSIB>,
 116                                  <&tegra_car TEGRA114_CLK_DSIBLP>,
 117                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
 118                         clock-names = "dsi", "lp", "parent";
 119                         resets = <&tegra_car 82>;
 120                         reset-names = "dsi";
 121                         nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
 122                         status = "disabled";
 123
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                 };
 127         };
 128
 129         gic: interrupt-controller@50041000 {
 130                 compatible = "arm,cortex-a15-gic";
 131                 #interrupt-cells = <3>;
 132                 interrupt-controller;
 133                 reg = <0x50041000 0x1000>,
 134                       <0x50042000 0x1000>,
 135                       <0x50044000 0x2000>,
 136                       <0x50046000 0x2000>;
 137                 interrupts = <GIC_PPI 9
 138                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 139         };
 140
 141         timer@60005000 {
 142                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 143                 reg = <0x60005000 0x400>;
 144                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 150                 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
 151         };
 152
 153         tegra_car: clock@60006000 {
 154                 compatible = "nvidia,tegra114-car";
 155                 reg = <0x60006000 0x1000>;
 156                 #clock-cells = <1>;
 157                 #reset-cells = <1>;
 158         };
 159
 160         flow-controller@60007000 {
 161                 compatible = "nvidia,tegra114-flowctrl";
 162                 reg = <0x60007000 0x1000>;
 163         };
 164
 165         apbdma: dma@6000a000 {
 166                 compatible = "nvidia,tegra114-apbdma";
 167                 reg = <0x6000a000 0x1400>;
 168                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 201                 resets = <&tegra_car 34>;
 202                 reset-names = "dma";
 203                 #dma-cells = <1>;
 204         };
 205
 206         ahb: ahb@6000c004 {
 207                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
 208                 reg = <0x6000c004 0x14c>;
 209         };
 210
 211         gpio: gpio@6000d000 {
 212                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 213                 reg = <0x6000d000 0x1000>;
 214                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 222                 #gpio-cells = <2>;
 223                 gpio-controller;
 224                 #interrupt-cells = <2>;
 225                 interrupt-controller;
 226         };
 227
 228         apbmisc@70000800 {
 229                 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
 230                 reg = <0x70000800 0x64   /* Chip revision */
 231                        0x70000008 0x04>; /* Strapping options */
 232         };
 233
 234         pinmux: pinmux@70000868 {
 235                 compatible = "nvidia,tegra114-pinmux";
 236                 reg = <0x70000868 0x148         /* Pad control registers */
 237                        0x70003000 0x40c>;       /* Mux registers */
 238         };
 239
 240         /*
 241          * There are two serial driver i.e. 8250 based simple serial
 242          * driver and APB DMA based serial driver for higher baudrate
 243          * and performace. To enable the 8250 based driver, the compatible
 244          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
 245          * the APB DMA based serial driver, the comptible is
 246          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 247          */
 248         uarta: serial@70006000 {
 249                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 250                 reg = <0x70006000 0x40>;
 251                 reg-shift = <2>;
 252                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 253                 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 254                 resets = <&tegra_car 6>;
 255                 reset-names = "serial";
 256                 dmas = <&apbdma 8>, <&apbdma 8>;
 257                 dma-names = "rx", "tx";
 258                 status = "disabled";
 259         };
 260
 261         uartb: serial@70006040 {
 262                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 263                 reg = <0x70006040 0x40>;
 264                 reg-shift = <2>;
 265                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 266                 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 267                 resets = <&tegra_car 7>;
 268                 reset-names = "serial";
 269                 dmas = <&apbdma 9>, <&apbdma 9>;
 270                 dma-names = "rx", "tx";
 271                 status = "disabled";
 272         };
 273
 274         uartc: serial@70006200 {
 275                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 276                 reg = <0x70006200 0x100>;
 277                 reg-shift = <2>;
 278                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 280                 resets = <&tegra_car 55>;
 281                 reset-names = "serial";
 282                 dmas = <&apbdma 10>, <&apbdma 10>;
 283                 dma-names = "rx", "tx";
 284                 status = "disabled";
 285         };
 286
 287         uartd: serial@70006300 {
 288                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 289                 reg = <0x70006300 0x100>;
 290                 reg-shift = <2>;
 291                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 292                 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 293                 resets = <&tegra_car 65>;
 294                 reset-names = "serial";
 295                 dmas = <&apbdma 19>, <&apbdma 19>;
 296                 dma-names = "rx", "tx";
 297                 status = "disabled";
 298         };
 299
 300         pwm: pwm@7000a000 {
 301                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 302                 reg = <0x7000a000 0x100>;
 303                 #pwm-cells = <2>;
 304                 clocks = <&tegra_car TEGRA114_CLK_PWM>;
 305                 resets = <&tegra_car 17>;
 306                 reset-names = "pwm";
 307                 status = "disabled";
 308         };
 309
 310         i2c@7000c000 {
 311                 compatible = "nvidia,tegra114-i2c";
 312                 reg = <0x7000c000 0x100>;
 313                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 317                 clock-names = "div-clk";
 318                 resets = <&tegra_car 12>;
 319                 reset-names = "i2c";
 320                 dmas = <&apbdma 21>, <&apbdma 21>;
 321                 dma-names = "rx", "tx";
 322                 status = "disabled";
 323         };
 324
 325         i2c@7000c400 {
 326                 compatible = "nvidia,tegra114-i2c";
 327                 reg = <0x7000c400 0x100>;
 328                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 332                 clock-names = "div-clk";
 333                 resets = <&tegra_car 54>;
 334                 reset-names = "i2c";
 335                 dmas = <&apbdma 22>, <&apbdma 22>;
 336                 dma-names = "rx", "tx";
 337                 status = "disabled";
 338         };
 339
 340         i2c@7000c500 {
 341                 compatible = "nvidia,tegra114-i2c";
 342                 reg = <0x7000c500 0x100>;
 343                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 344                 #address-cells = <1>;
 345                 #size-cells = <0>;
 346                 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 347                 clock-names = "div-clk";
 348                 resets = <&tegra_car 67>;
 349                 reset-names = "i2c";
 350                 dmas = <&apbdma 23>, <&apbdma 23>;
 351                 dma-names = "rx", "tx";
 352                 status = "disabled";
 353         };
 354
 355         i2c@7000c700 {
 356                 compatible = "nvidia,tegra114-i2c";
 357                 reg = <0x7000c700 0x100>;
 358                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 362                 clock-names = "div-clk";
 363                 resets = <&tegra_car 103>;
 364                 reset-names = "i2c";
 365                 dmas = <&apbdma 26>, <&apbdma 26>;
 366                 dma-names = "rx", "tx";
 367                 status = "disabled";
 368         };
 369
 370         i2c@7000d000 {
 371                 compatible = "nvidia,tegra114-i2c";
 372                 reg = <0x7000d000 0x100>;
 373                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 377                 clock-names = "div-clk";
 378                 resets = <&tegra_car 47>;
 379                 reset-names = "i2c";
 380                 dmas = <&apbdma 24>, <&apbdma 24>;
 381                 dma-names = "rx", "tx";
 382                 status = "disabled";
 383         };
 384
 385         spi@7000d400 {
 386                 compatible = "nvidia,tegra114-spi";
 387                 reg = <0x7000d400 0x200>;
 388                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391                 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 392                 clock-names = "spi";
 393                 resets = <&tegra_car 41>;
 394                 reset-names = "spi";
 395                 dmas = <&apbdma 15>, <&apbdma 15>;
 396                 dma-names = "rx", "tx";
 397                 status = "disabled";
 398         };
 399
 400         spi@7000d600 {
 401                 compatible = "nvidia,tegra114-spi";
 402                 reg = <0x7000d600 0x200>;
 403                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 407                 clock-names = "spi";
 408                 resets = <&tegra_car 44>;
 409                 reset-names = "spi";
 410                 dmas = <&apbdma 16>, <&apbdma 16>;
 411                 dma-names = "rx", "tx";
 412                 status = "disabled";
 413         };
 414
 415         spi@7000d800 {
 416                 compatible = "nvidia,tegra114-spi";
 417                 reg = <0x7000d800 0x200>;
 418                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421                 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 422                 clock-names = "spi";
 423                 resets = <&tegra_car 46>;
 424                 reset-names = "spi";
 425                 dmas = <&apbdma 17>, <&apbdma 17>;
 426                 dma-names = "rx", "tx";
 427                 status = "disabled";
 428         };
 429
 430         spi@7000da00 {
 431                 compatible = "nvidia,tegra114-spi";
 432                 reg = <0x7000da00 0x200>;
 433                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 437                 clock-names = "spi";
 438                 resets = <&tegra_car 68>;
 439                 reset-names = "spi";
 440                 dmas = <&apbdma 18>, <&apbdma 18>;
 441                 dma-names = "rx", "tx";
 442                 status = "disabled";
 443         };
 444
 445         spi@7000dc00 {
 446                 compatible = "nvidia,tegra114-spi";
 447                 reg = <0x7000dc00 0x200>;
 448                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 452                 clock-names = "spi";
 453                 resets = <&tegra_car 104>;
 454                 reset-names = "spi";
 455                 dmas = <&apbdma 27>, <&apbdma 27>;
 456                 dma-names = "rx", "tx";
 457                 status = "disabled";
 458         };
 459
 460         spi@7000de00 {
 461                 compatible = "nvidia,tegra114-spi";
 462                 reg = <0x7000de00 0x200>;
 463                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 464                 #address-cells = <1>;
 465                 #size-cells = <0>;
 466                 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 467                 clock-names = "spi";
 468                 resets = <&tegra_car 105>;
 469                 reset-names = "spi";
 470                 dmas = <&apbdma 28>, <&apbdma 28>;
 471                 dma-names = "rx", "tx";
 472                 status = "disabled";
 473         };
 474
 475         rtc@7000e000 {
 476                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 477                 reg = <0x7000e000 0x100>;
 478                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 479                 clocks = <&tegra_car TEGRA114_CLK_RTC>;
 480         };
 481
 482         kbc@7000e200 {
 483                 compatible = "nvidia,tegra114-kbc";
 484                 reg = <0x7000e200 0x100>;
 485                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 486                 clocks = <&tegra_car TEGRA114_CLK_KBC>;
 487                 resets = <&tegra_car 36>;
 488                 reset-names = "kbc";
 489                 status = "disabled";
 490         };
 491
 492         pmc@7000e400 {
 493                 compatible = "nvidia,tegra114-pmc";
 494                 reg = <0x7000e400 0x400>;
 495                 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
 496                 clock-names = "pclk", "clk32k_in";
 497         };
 498
 499         fuse@7000f800 {
 500                 compatible = "nvidia,tegra114-efuse";
 501                 reg = <0x7000f800 0x400>;
 502                 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
 503                 clock-names = "fuse";
 504                 resets = <&tegra_car 39>;
 505                 reset-names = "fuse";
 506         };
 507
 508         iommu@70019010 {
 509                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
 510                 reg = <0x70019010 0x02c
 511                        0x700191f0 0x010
 512                        0x70019228 0x074>;
 513                 nvidia,#asids = <4>;
 514                 dma-window = <0 0x40000000>;
 515                 nvidia,swgroups = <0x18659fe>;
 516                 nvidia,ahb = <&ahb>;
 517         };
 518
 519         ahub@70080000 {
 520                 compatible = "nvidia,tegra114-ahub";
 521                 reg = <0x70080000 0x200>,
 522                       <0x70080200 0x100>,
 523                       <0x70081000 0x200>;
 524                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 525                 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 526                          <&tegra_car TEGRA114_CLK_APBIF>;
 527                 clock-names = "d_audio", "apbif";
 528                 resets = <&tegra_car 106>, /* d_audio */
 529                          <&tegra_car 107>, /* apbif */
 530                          <&tegra_car 30>,  /* i2s0 */
 531                          <&tegra_car 11>,  /* i2s1 */
 532                          <&tegra_car 18>,  /* i2s2 */
 533                          <&tegra_car 101>, /* i2s3 */
 534                          <&tegra_car 102>, /* i2s4 */
 535                          <&tegra_car 108>, /* dam0 */
 536                          <&tegra_car 109>, /* dam1 */
 537                          <&tegra_car 110>, /* dam2 */
 538                          <&tegra_car 10>,  /* spdif */
 539                          <&tegra_car 153>, /* amx */
 540                          <&tegra_car 154>; /* adx */
 541                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 542                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 543                               "spdif", "amx", "adx";
 544                 dmas = <&apbdma 1>, <&apbdma 1>,
 545                        <&apbdma 2>, <&apbdma 2>,
 546                        <&apbdma 3>, <&apbdma 3>,
 547                        <&apbdma 4>, <&apbdma 4>,
 548                        <&apbdma 6>, <&apbdma 6>,
 549                        <&apbdma 7>, <&apbdma 7>,
 550                        <&apbdma 12>, <&apbdma 12>,
 551                        <&apbdma 13>, <&apbdma 13>,
 552                        <&apbdma 14>, <&apbdma 14>,
 553                        <&apbdma 29>, <&apbdma 29>;
 554                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 555                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 556                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 557                             "rx9", "tx9";
 558                 ranges;
 559                 #address-cells = <1>;
 560                 #size-cells = <1>;
 561
 562                 tegra_i2s0: i2s@70080300 {
 563                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 564                         reg = <0x70080300 0x100>;
 565                         nvidia,ahub-cif-ids = <4 4>;
 566                         clocks = <&tegra_car TEGRA114_CLK_I2S0>;
 567                         resets = <&tegra_car 30>;
 568                         reset-names = "i2s";
 569                         status = "disabled";
 570                 };
 571
 572                 tegra_i2s1: i2s@70080400 {
 573                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 574                         reg = <0x70080400 0x100>;
 575                         nvidia,ahub-cif-ids = <5 5>;
 576                         clocks = <&tegra_car TEGRA114_CLK_I2S1>;
 577                         resets = <&tegra_car 11>;
 578                         reset-names = "i2s";
 579                         status = "disabled";
 580                 };
 581
 582                 tegra_i2s2: i2s@70080500 {
 583                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 584                         reg = <0x70080500 0x100>;
 585                         nvidia,ahub-cif-ids = <6 6>;
 586                         clocks = <&tegra_car TEGRA114_CLK_I2S2>;
 587                         resets = <&tegra_car 18>;
 588                         reset-names = "i2s";
 589                         status = "disabled";
 590                 };
 591
 592                 tegra_i2s3: i2s@70080600 {
 593                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 594                         reg = <0x70080600 0x100>;
 595                         nvidia,ahub-cif-ids = <7 7>;
 596                         clocks = <&tegra_car TEGRA114_CLK_I2S3>;
 597                         resets = <&tegra_car 101>;
 598                         reset-names = "i2s";
 599                         status = "disabled";
 600                 };
 601
 602                 tegra_i2s4: i2s@70080700 {
 603                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 604                         reg = <0x70080700 0x100>;
 605                         nvidia,ahub-cif-ids = <8 8>;
 606                         clocks = <&tegra_car TEGRA114_CLK_I2S4>;
 607                         resets = <&tegra_car 102>;
 608                         reset-names = "i2s";
 609                         status = "disabled";
 610                 };
 611         };
 612
 613         mipi: mipi@700e3000 {
 614                 compatible = "nvidia,tegra114-mipi";
 615                 reg = <0x700e3000 0x100>;
 616                 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
 617                 #nvidia,mipi-calibrate-cells = <1>;
 618         };
 619
 620         sdhci@78000000 {
 621                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 622                 reg = <0x78000000 0x200>;
 623                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
 625                 resets = <&tegra_car 14>;
 626                 reset-names = "sdhci";
 627                 status = "disabled";
 628         };
 629
 630         sdhci@78000200 {
 631                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 632                 reg = <0x78000200 0x200>;
 633                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
 635                 resets = <&tegra_car 9>;
 636                 reset-names = "sdhci";
 637                 status = "disabled";
 638         };
 639
 640         sdhci@78000400 {
 641                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 642                 reg = <0x78000400 0x200>;
 643                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 644                 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
 645                 resets = <&tegra_car 69>;
 646                 reset-names = "sdhci";
 647                 status = "disabled";
 648         };
 649
 650         sdhci@78000600 {
 651                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 652                 reg = <0x78000600 0x200>;
 653                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 654                 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
 655                 resets = <&tegra_car 15>;
 656                 reset-names = "sdhci";
 657                 status = "disabled";
 658         };
 659
 660         usb@7d000000 {
 661                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 662                 reg = <0x7d000000 0x4000>;
 663                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 664                 phy_type = "utmi";
 665                 clocks = <&tegra_car TEGRA114_CLK_USBD>;
 666                 resets = <&tegra_car 22>;
 667                 reset-names = "usb";
 668                 nvidia,phy = <&phy1>;
 669                 status = "disabled";
 670         };
 671
 672         phy1: usb-phy@7d000000 {
 673                 compatible = "nvidia,tegra30-usb-phy";
 674                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 675                 phy_type = "utmi";
 676                 clocks = <&tegra_car TEGRA114_CLK_USBD>,
 677                          <&tegra_car TEGRA114_CLK_PLL_U>,
 678                          <&tegra_car TEGRA114_CLK_USBD>;
 679                 clock-names = "reg", "pll_u", "utmi-pads";
 680                 resets = <&tegra_car 22>, <&tegra_car 22>;
 681                 reset-names = "usb", "utmi-pads";
 682                 nvidia,hssync-start-delay = <0>;
 683                 nvidia,idle-wait-delay = <17>;
 684                 nvidia,elastic-limit = <16>;
 685                 nvidia,term-range-adj = <6>;
 686                 nvidia,xcvr-setup = <9>;
 687                 nvidia,xcvr-lsfslew = <0>;
 688                 nvidia,xcvr-lsrslew = <3>;
 689                 nvidia,hssquelch-level = <2>;
 690                 nvidia,hsdiscon-level = <5>;
 691                 nvidia,xcvr-hsslew = <12>;
 692                 nvidia,has-utmi-pad-registers;
 693                 status = "disabled";
 694         };
 695
 696         usb@7d008000 {
 697                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 698                 reg = <0x7d008000 0x4000>;
 699                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 700                 phy_type = "utmi";
 701                 clocks = <&tegra_car TEGRA114_CLK_USB3>;
 702                 resets = <&tegra_car 59>;
 703                 reset-names = "usb";
 704                 nvidia,phy = <&phy3>;
 705                 status = "disabled";
 706         };
 707
 708         phy3: usb-phy@7d008000 {
 709                 compatible = "nvidia,tegra30-usb-phy";
 710                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 711                 phy_type = "utmi";
 712                 clocks = <&tegra_car TEGRA114_CLK_USB3>,
 713                          <&tegra_car TEGRA114_CLK_PLL_U>,
 714                          <&tegra_car TEGRA114_CLK_USBD>;
 715                 clock-names = "reg", "pll_u", "utmi-pads";
 716                 resets = <&tegra_car 59>, <&tegra_car 22>;
 717                 reset-names = "usb", "utmi-pads";
 718                 nvidia,hssync-start-delay = <0>;
 719                 nvidia,idle-wait-delay = <17>;
 720                 nvidia,elastic-limit = <16>;
 721                 nvidia,term-range-adj = <6>;
 722                 nvidia,xcvr-setup = <9>;
 723                 nvidia,xcvr-lsfslew = <0>;
 724                 nvidia,xcvr-lsrslew = <3>;
 725                 nvidia,hssquelch-level = <2>;
 726                 nvidia,hsdiscon-level = <5>;
 727                 nvidia,xcvr-hsslew = <12>;
 728                 status = "disabled";
 729         };
 730
 731         cpus {
 732                 #address-cells = <1>;
 733                 #size-cells = <0>;
 734
 735                 cpu@0 {
 736                         device_type = "cpu";
 737                         compatible = "arm,cortex-a15";
 738                         reg = <0>;
 739                 };
 740
 741                 cpu@1 {
 742                         device_type = "cpu";
 743                         compatible = "arm,cortex-a15";
 744                         reg = <1>;
 745                 };
 746
 747                 cpu@2 {
 748                         device_type = "cpu";
 749                         compatible = "arm,cortex-a15";
 750                         reg = <2>;
 751                 };
 752
 753                 cpu@3 {
 754                         device_type = "cpu";
 755                         compatible = "arm,cortex-a15";
 756                         reg = <3>;
 757                 };
 758         };
 759
 760         timer {
 761                 compatible = "arm,armv7-timer";
 762                 interrupts =
 763                         <GIC_PPI 13
 764                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 765                         <GIC_PPI 14
 766                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 767                         <GIC_PPI 11
 768                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 769                         <GIC_PPI 10
 770                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 771         };
 772 };