arch/arm/boot/dts/tegra114.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra114";
   5         interrupt-parent = <&gic>;
   6
   7         gic: interrupt-controller {
   8                 compatible = "arm,cortex-a15-gic";
   9                 #interrupt-cells = <3>;
  10                 interrupt-controller;
  11                 reg = <0x50041000 0x1000>,
  12                       <0x50042000 0x1000>,
  13                       <0x50044000 0x2000>,
  14                       <0x50046000 0x2000>;
  15                 interrupts = <1 9 0xf04>;
  16         };
  17
  18         timer@60005000 {
  19                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
  20                 reg = <0x60005000 0x400>;
  21                 interrupts = <0 0 0x04
  22                               0 1 0x04
  23                               0 41 0x04
  24                               0 42 0x04
  25                               0 121 0x04
  26                               0 122 0x04>;
  27                 clocks = <&tegra_car 5>;
  28         };
  29
  30         tegra_car: clock {
  31                 compatible = "nvidia,tegra114-car";
  32                 reg = <0x60006000 0x1000>;
  33                 #clock-cells = <1>;
  34         };
  35
  36         ahb: ahb {
  37                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
  38                 reg = <0x6000c004 0x14c>;
  39         };
  40
  41         gpio: gpio {
  42                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
  43                 reg = <0x6000d000 0x1000>;
  44                 interrupts = <0 32 0x04
  45                               0 33 0x04
  46                               0 34 0x04
  47                               0 35 0x04
  48                               0 55 0x04
  49                               0 87 0x04
  50                               0 89 0x04
  51                               0 125 0x04>;
  52                 #gpio-cells = <2>;
  53                 gpio-controller;
  54                 #interrupt-cells = <2>;
  55                 interrupt-controller;
  56         };
  57
  58         pinmux: pinmux {
  59                 compatible = "nvidia,tegra114-pinmux";
  60                 reg = <0x70000868 0x148         /* Pad control registers */
  61                        0x70003000 0x40c>;       /* Mux registers */
  62         };
  63
  64         serial@70006000 {
  65                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  66                 reg = <0x70006000 0x40>;
  67                 reg-shift = <2>;
  68                 interrupts = <0 36 0x04>;
  69                 status = "disabled";
  70                 clocks = <&tegra_car 6>;
  71         };
  72
  73         serial@70006040 {
  74                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  75                 reg = <0x70006040 0x40>;
  76                 reg-shift = <2>;
  77                 interrupts = <0 37 0x04>;
  78                 status = "disabled";
  79                 clocks = <&tegra_car 192>;
  80         };
  81
  82         serial@70006200 {
  83                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  84                 reg = <0x70006200 0x100>;
  85                 reg-shift = <2>;
  86                 interrupts = <0 46 0x04>;
  87                 status = "disabled";
  88                 clocks = <&tegra_car 55>;
  89         };
  90
  91         serial@70006300 {
  92                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  93                 reg = <0x70006300 0x100>;
  94                 reg-shift = <2>;
  95                 interrupts = <0 90 0x04>;
  96                 status = "disabled";
  97                 clocks = <&tegra_car 65>;
  98         };
  99
 100         rtc {
 101                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 102                 reg = <0x7000e000 0x100>;
 103                 interrupts = <0 2 0x04>;
 104                 clocks = <&tegra_car 4>;
 105         };
 106
 107         pmc {
 108                 compatible = "nvidia,tegra114-pmc";
 109                 reg = <0x7000e400 0x400>;
 110                 clocks = <&tegra_car 261>, <&clk32k_in>;
 111                 clock-names = "pclk", "clk32k_in";
 112         };
 113
 114         iommu {
 115                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
 116                 reg = <0x7000f010 0x02c
 117                        0x7000f1f0 0x010
 118                        0x7000f228 0x074>;
 119                 nvidia,#asids = <4>;
 120                 dma-window = <0 0x40000000>;
 121                 nvidia,swgroups = <0x18659fe>;
 122                 nvidia,ahb = <&ahb>;
 123         };
 124
 125         cpus {
 126                 #address-cells = <1>;
 127                 #size-cells = <0>;
 128
 129                 cpu@0 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a15";
 132                         reg = <0>;
 133                 };
 134
 135                 cpu@1 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a15";
 138                         reg = <1>;
 139                 };
 140
 141                 cpu@2 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-a15";
 144                         reg = <2>;
 145                 };
 146
 147                 cpu@3 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a15";
 150                         reg = <3>;
 151                 };
 152         };
 153
 154         timer {
 155                 compatible = "arm,armv7-timer";
 156                 interrupts = <1 13 0xf08>,
 157                              <1 14 0xf08>,
 158                              <1 11 0xf08>,
 159                              <1 10 0xf08>;
 160         };
 161 };