arch/arm/boot/dts/tegra114.dtsi

   1 #include <dt-bindings/gpio/tegra-gpio.h>
   2
   3 #include "skeleton.dtsi"
   4
   5 / {
   6         compatible = "nvidia,tegra114";
   7         interrupt-parent = <&gic>;
   8
   9         aliases {
  10                 serial0 = &uarta;
  11                 serial1 = &uartb;
  12                 serial2 = &uartc;
  13                 serial3 = &uartd;
  14         };
  15
  16         gic: interrupt-controller {
  17                 compatible = "arm,cortex-a15-gic";
  18                 #interrupt-cells = <3>;
  19                 interrupt-controller;
  20                 reg = <0x50041000 0x1000>,
  21                       <0x50042000 0x1000>,
  22                       <0x50044000 0x2000>,
  23                       <0x50046000 0x2000>;
  24                 interrupts = <1 9 0xf04>;
  25         };
  26
  27         timer@60005000 {
  28                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
  29                 reg = <0x60005000 0x400>;
  30                 interrupts = <0 0 0x04
  31                               0 1 0x04
  32                               0 41 0x04
  33                               0 42 0x04
  34                               0 121 0x04
  35                               0 122 0x04>;
  36                 clocks = <&tegra_car 5>;
  37         };
  38
  39         tegra_car: clock {
  40                 compatible = "nvidia,tegra114-car";
  41                 reg = <0x60006000 0x1000>;
  42                 #clock-cells = <1>;
  43         };
  44
  45         apbdma: dma {
  46                 compatible = "nvidia,tegra114-apbdma";
  47                 reg = <0x6000a000 0x1400>;
  48                 interrupts = <0 104 0x04
  49                               0 105 0x04
  50                               0 106 0x04
  51                               0 107 0x04
  52                               0 108 0x04
  53                               0 109 0x04
  54                               0 110 0x04
  55                               0 111 0x04
  56                               0 112 0x04
  57                               0 113 0x04
  58                               0 114 0x04
  59                               0 115 0x04
  60                               0 116 0x04
  61                               0 117 0x04
  62                               0 118 0x04
  63                               0 119 0x04
  64                               0 128 0x04
  65                               0 129 0x04
  66                               0 130 0x04
  67                               0 131 0x04
  68                               0 132 0x04
  69                               0 133 0x04
  70                               0 134 0x04
  71                               0 135 0x04
  72                               0 136 0x04
  73                               0 137 0x04
  74                               0 138 0x04
  75                               0 139 0x04
  76                               0 140 0x04
  77                               0 141 0x04
  78                               0 142 0x04
  79                               0 143 0x04>;
  80                 clocks = <&tegra_car 34>;
  81         };
  82
  83         ahb: ahb {
  84                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
  85                 reg = <0x6000c004 0x14c>;
  86         };
  87
  88         gpio: gpio {
  89                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
  90                 reg = <0x6000d000 0x1000>;
  91                 interrupts = <0 32 0x04
  92                               0 33 0x04
  93                               0 34 0x04
  94                               0 35 0x04
  95                               0 55 0x04
  96                               0 87 0x04
  97                               0 89 0x04
  98                               0 125 0x04>;
  99                 #gpio-cells = <2>;
 100                 gpio-controller;
 101                 #interrupt-cells = <2>;
 102                 interrupt-controller;
 103         };
 104
 105         pinmux: pinmux {
 106                 compatible = "nvidia,tegra114-pinmux";
 107                 reg = <0x70000868 0x148         /* Pad control registers */
 108                        0x70003000 0x40c>;       /* Mux registers */
 109         };
 110
 111         /*
 112          * There are two serial driver i.e. 8250 based simple serial
 113          * driver and APB DMA based serial driver for higher baudrate
 114          * and performace. To enable the 8250 based driver, the compatible
 115          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
 116          * the APB DMA based serial driver, the comptible is
 117          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 118          */
 119         uarta: serial@70006000 {
 120                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 121                 reg = <0x70006000 0x40>;
 122                 reg-shift = <2>;
 123                 interrupts = <0 36 0x04>;
 124                 nvidia,dma-request-selector = <&apbdma 8>;
 125                 status = "disabled";
 126                 clocks = <&tegra_car 6>;
 127         };
 128
 129         uartb: serial@70006040 {
 130                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 131                 reg = <0x70006040 0x40>;
 132                 reg-shift = <2>;
 133                 interrupts = <0 37 0x04>;
 134                 nvidia,dma-request-selector = <&apbdma 9>;
 135                 status = "disabled";
 136                 clocks = <&tegra_car 192>;
 137         };
 138
 139         uartc: serial@70006200 {
 140                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 141                 reg = <0x70006200 0x100>;
 142                 reg-shift = <2>;
 143                 interrupts = <0 46 0x04>;
 144                 nvidia,dma-request-selector = <&apbdma 10>;
 145                 status = "disabled";
 146                 clocks = <&tegra_car 55>;
 147         };
 148
 149         uartd: serial@70006300 {
 150                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 151                 reg = <0x70006300 0x100>;
 152                 reg-shift = <2>;
 153                 interrupts = <0 90 0x04>;
 154                 nvidia,dma-request-selector = <&apbdma 19>;
 155                 status = "disabled";
 156                 clocks = <&tegra_car 65>;
 157         };
 158
 159         pwm: pwm {
 160                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 161                 reg = <0x7000a000 0x100>;
 162                 #pwm-cells = <2>;
 163                 clocks = <&tegra_car 17>;
 164                 status = "disabled";
 165         };
 166
 167         i2c@7000c000 {
 168                 compatible = "nvidia,tegra114-i2c";
 169                 reg = <0x7000c000 0x100>;
 170                 interrupts = <0 38 0x04>;
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173                 clocks = <&tegra_car 12>;
 174                 clock-names = "div-clk";
 175                 status = "disabled";
 176         };
 177
 178         i2c@7000c400 {
 179                 compatible = "nvidia,tegra114-i2c";
 180                 reg = <0x7000c400 0x100>;
 181                 interrupts = <0 84 0x04>;
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 clocks = <&tegra_car 54>;
 185                 clock-names = "div-clk";
 186                 status = "disabled";
 187         };
 188
 189         i2c@7000c500 {
 190                 compatible = "nvidia,tegra114-i2c";
 191                 reg = <0x7000c500 0x100>;
 192                 interrupts = <0 92 0x04>;
 193                 #address-cells = <1>;
 194                 #size-cells = <0>;
 195                 clocks = <&tegra_car 67>;
 196                 clock-names = "div-clk";
 197                 status = "disabled";
 198         };
 199
 200         i2c@7000c700 {
 201                 compatible = "nvidia,tegra114-i2c";
 202                 reg = <0x7000c700 0x100>;
 203                 interrupts = <0 120 0x04>;
 204                 #address-cells = <1>;
 205                 #size-cells = <0>;
 206                 clocks = <&tegra_car 103>;
 207                 clock-names = "div-clk";
 208                 status = "disabled";
 209         };
 210
 211         i2c@7000d000 {
 212                 compatible = "nvidia,tegra114-i2c";
 213                 reg = <0x7000d000 0x100>;
 214                 interrupts = <0 53 0x04>;
 215                 #address-cells = <1>;
 216                 #size-cells = <0>;
 217                 clocks = <&tegra_car 47>;
 218                 clock-names = "div-clk";
 219                 status = "disabled";
 220         };
 221
 222         spi@7000d400 {
 223                 compatible = "nvidia,tegra114-spi";
 224                 reg = <0x7000d400 0x200>;
 225                 interrupts = <0 59 0x04>;
 226                 nvidia,dma-request-selector = <&apbdma 15>;
 227                 #address-cells = <1>;
 228                 #size-cells = <0>;
 229                 clocks = <&tegra_car 41>;
 230                 clock-names = "spi";
 231                 status = "disabled";
 232         };
 233
 234         spi@7000d600 {
 235                 compatible = "nvidia,tegra114-spi";
 236                 reg = <0x7000d600 0x200>;
 237                 interrupts = <0 82 0x04>;
 238                 nvidia,dma-request-selector = <&apbdma 16>;
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241                 clocks = <&tegra_car 44>;
 242                 clock-names = "spi";
 243                 status = "disabled";
 244         };
 245
 246         spi@7000d800 {
 247                 compatible = "nvidia,tegra114-spi";
 248                 reg = <0x7000d800 0x200>;
 249                 interrupts = <0 83 0x04>;
 250                 nvidia,dma-request-selector = <&apbdma 17>;
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 clocks = <&tegra_car 46>;
 254                 clock-names = "spi";
 255                 status = "disabled";
 256         };
 257
 258         spi@7000da00 {
 259                 compatible = "nvidia,tegra114-spi";
 260                 reg = <0x7000da00 0x200>;
 261                 interrupts = <0 93 0x04>;
 262                 nvidia,dma-request-selector = <&apbdma 18>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265                 clocks = <&tegra_car 68>;
 266                 clock-names = "spi";
 267                 status = "disabled";
 268         };
 269
 270         spi@7000dc00 {
 271                 compatible = "nvidia,tegra114-spi";
 272                 reg = <0x7000dc00 0x200>;
 273                 interrupts = <0 94 0x04>;
 274                 nvidia,dma-request-selector = <&apbdma 27>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 clocks = <&tegra_car 104>;
 278                 clock-names = "spi";
 279                 status = "disabled";
 280         };
 281
 282         spi@7000de00 {
 283                 compatible = "nvidia,tegra114-spi";
 284                 reg = <0x7000de00 0x200>;
 285                 interrupts = <0 79 0x04>;
 286                 nvidia,dma-request-selector = <&apbdma 28>;
 287                 #address-cells = <1>;
 288                 #size-cells = <0>;
 289                 clocks = <&tegra_car 105>;
 290                 clock-names = "spi";
 291                 status = "disabled";
 292         };
 293
 294         rtc {
 295                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 296                 reg = <0x7000e000 0x100>;
 297                 interrupts = <0 2 0x04>;
 298                 clocks = <&tegra_car 4>;
 299         };
 300
 301         kbc {
 302                 compatible = "nvidia,tegra114-kbc";
 303                 reg = <0x7000e200 0x100>;
 304                 interrupts = <0 85 0x04>;
 305                 clocks = <&tegra_car 36>;
 306                 status = "disabled";
 307         };
 308
 309         pmc {
 310                 compatible = "nvidia,tegra114-pmc";
 311                 reg = <0x7000e400 0x400>;
 312                 clocks = <&tegra_car 261>, <&clk32k_in>;
 313                 clock-names = "pclk", "clk32k_in";
 314         };
 315
 316         iommu {
 317                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
 318                 reg = <0x7000f010 0x02c
 319                        0x7000f1f0 0x010
 320                        0x7000f228 0x074>;
 321                 nvidia,#asids = <4>;
 322                 dma-window = <0 0x40000000>;
 323                 nvidia,swgroups = <0x18659fe>;
 324                 nvidia,ahb = <&ahb>;
 325         };
 326
 327         sdhci@78000000 {
 328                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 329                 reg = <0x78000000 0x200>;
 330                 interrupts = <0 14 0x04>;
 331                 clocks = <&tegra_car 14>;
 332                 status = "disable";
 333         };
 334
 335         sdhci@78000200 {
 336                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 337                 reg = <0x78000200 0x200>;
 338                 interrupts = <0 15 0x04>;
 339                 clocks = <&tegra_car 9>;
 340                 status = "disable";
 341         };
 342
 343         sdhci@78000400 {
 344                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 345                 reg = <0x78000400 0x200>;
 346                 interrupts = <0 19 0x04>;
 347                 clocks = <&tegra_car 69>;
 348                 status = "disable";
 349         };
 350
 351         sdhci@78000600 {
 352                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 353                 reg = <0x78000600 0x200>;
 354                 interrupts = <0 31 0x04>;
 355                 clocks = <&tegra_car 15>;
 356                 status = "disable";
 357         };
 358
 359         cpus {
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362
 363                 cpu@0 {
 364                         device_type = "cpu";
 365                         compatible = "arm,cortex-a15";
 366                         reg = <0>;
 367                 };
 368
 369                 cpu@1 {
 370                         device_type = "cpu";
 371                         compatible = "arm,cortex-a15";
 372                         reg = <1>;
 373                 };
 374
 375                 cpu@2 {
 376                         device_type = "cpu";
 377                         compatible = "arm,cortex-a15";
 378                         reg = <2>;
 379                 };
 380
 381                 cpu@3 {
 382                         device_type = "cpu";
 383                         compatible = "arm,cortex-a15";
 384                         reg = <3>;
 385                 };
 386         };
 387
 388         timer {
 389                 compatible = "arm,armv7-timer";
 390                 interrupts = <1 13 0xf08>,
 391                              <1 14 0xf08>,
 392                              <1 11 0xf08>,
 393                              <1 10 0xf08>;
 394         };
 395 };