arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra124";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         host1x@0,50000000 {
  15                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  16                 reg = <0x0 0x50000000 0x0 0x00034000>;
  17                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  18                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  19                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  20                 resets = <&tegra_car 28>;
  21                 reset-names = "host1x";
  22
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25
  26                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  27
  28                 dc@0,54200000 {
  29                         compatible = "nvidia,tegra124-dc";
  30                         reg = <0x0 0x54200000 0x0 0x00040000>;
  31                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  32                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
  33                                  <&tegra_car TEGRA124_CLK_PLL_P>;
  34                         clock-names = "dc", "parent";
  35                         resets = <&tegra_car 27>;
  36                         reset-names = "dc";
  37
  38                         nvidia,head = <0>;
  39                 };
  40
  41                 dc@0,54240000 {
  42                         compatible = "nvidia,tegra124-dc";
  43                         reg = <0x0 0x54240000 0x0 0x00040000>;
  44                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  45                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
  46                                  <&tegra_car TEGRA124_CLK_PLL_P>;
  47                         clock-names = "dc", "parent";
  48                         resets = <&tegra_car 26>;
  49                         reset-names = "dc";
  50
  51                         nvidia,head = <1>;
  52                 };
  53
  54                 hdmi@0,54280000 {
  55                         compatible = "nvidia,tegra124-hdmi";
  56                         reg = <0x0 0x54280000 0x0 0x00040000>;
  57                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  58                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
  59                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
  60                         clock-names = "hdmi", "parent";
  61                         resets = <&tegra_car 51>;
  62                         reset-names = "hdmi";
  63                         status = "disabled";
  64                 };
  65
  66                 sor@0,54540000 {
  67                         compatible = "nvidia,tegra124-sor";
  68                         reg = <0x0 0x54540000 0x0 0x00040000>;
  69                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  70                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
  71                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
  72                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
  73                                  <&tegra_car TEGRA124_CLK_CLK_M>;
  74                         clock-names = "sor", "parent", "dp", "safe";
  75                         resets = <&tegra_car 182>;
  76                         reset-names = "sor";
  77                         status = "disabled";
  78                 };
  79
  80                 dpaux@0,545c0000 {
  81                         compatible = "nvidia,tegra124-dpaux";
  82                         reg = <0x0 0x545c0000 0x0 0x00040000>;
  83                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  84                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
  85                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
  86                         clock-names = "dpaux", "parent";
  87                         resets = <&tegra_car 181>;
  88                         reset-names = "dpaux";
  89                         status = "disabled";
  90                 };
  91         };
  92
  93         gic: interrupt-controller@0,50041000 {
  94                 compatible = "arm,cortex-a15-gic";
  95                 #interrupt-cells = <3>;
  96                 interrupt-controller;
  97                 reg = <0x0 0x50041000 0x0 0x1000>,
  98                       <0x0 0x50042000 0x0 0x1000>,
  99                       <0x0 0x50044000 0x0 0x2000>,
 100                       <0x0 0x50046000 0x0 0x2000>;
 101                 interrupts = <GIC_PPI 9
 102                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 103         };
 104
 105         timer@0,60005000 {
 106                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
 107                 reg = <0x0 0x60005000 0x0 0x400>;
 108                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 109                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 110                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 111                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 112                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 113                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 114                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 115         };
 116
 117         tegra_car: clock@0,60006000 {
 118                 compatible = "nvidia,tegra124-car";
 119                 reg = <0x0 0x60006000 0x0 0x1000>;
 120                 #clock-cells = <1>;
 121                 #reset-cells = <1>;
 122         };
 123
 124         gpio: gpio@0,6000d000 {
 125                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 126                 reg = <0x0 0x6000d000 0x0 0x1000>;
 127                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 128                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 129                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 130                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 131                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 132                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 133                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 134                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 135                 #gpio-cells = <2>;
 136                 gpio-controller;
 137                 #interrupt-cells = <2>;
 138                 interrupt-controller;
 139         };
 140
 141         apbdma: dma@0,60020000 {
 142                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 143                 reg = <0x0 0x60020000 0x0 0x1400>;
 144                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 157                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 158                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 162                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 163                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 177                 resets = <&tegra_car 34>;
 178                 reset-names = "dma";
 179                 #dma-cells = <1>;
 180         };
 181
 182         pinmux: pinmux@0,70000868 {
 183                 compatible = "nvidia,tegra124-pinmux";
 184                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 185                       <0x0 0x70003000 0x0 0x434>; /* Mux registers */
 186         };
 187
 188         /*
 189          * There are two serial driver i.e. 8250 based simple serial
 190          * driver and APB DMA based serial driver for higher baudrate
 191          * and performace. To enable the 8250 based driver, the compatible
 192          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 193          * the APB DMA based serial driver, the comptible is
 194          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 195          */
 196         serial@0,70006000 {
 197                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 198                 reg = <0x0 0x70006000 0x0 0x40>;
 199                 reg-shift = <2>;
 200                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 202                 resets = <&tegra_car 6>;
 203                 reset-names = "serial";
 204                 dmas = <&apbdma 8>, <&apbdma 8>;
 205                 dma-names = "rx", "tx";
 206                 status = "disabled";
 207         };
 208
 209         serial@0,70006040 {
 210                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 211                 reg = <0x0 0x70006040 0x0 0x40>;
 212                 reg-shift = <2>;
 213                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 215                 resets = <&tegra_car 7>;
 216                 reset-names = "serial";
 217                 dmas = <&apbdma 9>, <&apbdma 9>;
 218                 dma-names = "rx", "tx";
 219                 status = "disabled";
 220         };
 221
 222         serial@0,70006200 {
 223                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 224                 reg = <0x0 0x70006200 0x0 0x40>;
 225                 reg-shift = <2>;
 226                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 227                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 228                 resets = <&tegra_car 55>;
 229                 reset-names = "serial";
 230                 dmas = <&apbdma 10>, <&apbdma 10>;
 231                 dma-names = "rx", "tx";
 232                 status = "disabled";
 233         };
 234
 235         serial@0,70006300 {
 236                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 237                 reg = <0x0 0x70006300 0x0 0x40>;
 238                 reg-shift = <2>;
 239                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 240                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 241                 resets = <&tegra_car 65>;
 242                 reset-names = "serial";
 243                 dmas = <&apbdma 19>, <&apbdma 19>;
 244                 dma-names = "rx", "tx";
 245                 status = "disabled";
 246         };
 247
 248         pwm@0,7000a000 {
 249                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 250                 reg = <0x0 0x7000a000 0x0 0x100>;
 251                 #pwm-cells = <2>;
 252                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 253                 resets = <&tegra_car 17>;
 254                 reset-names = "pwm";
 255                 status = "disabled";
 256         };
 257
 258         i2c@0,7000c000 {
 259                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 260                 reg = <0x0 0x7000c000 0x0 0x100>;
 261                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 265                 clock-names = "div-clk";
 266                 resets = <&tegra_car 12>;
 267                 reset-names = "i2c";
 268                 dmas = <&apbdma 21>, <&apbdma 21>;
 269                 dma-names = "rx", "tx";
 270                 status = "disabled";
 271         };
 272
 273         i2c@0,7000c400 {
 274                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 275                 reg = <0x0 0x7000c400 0x0 0x100>;
 276                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 280                 clock-names = "div-clk";
 281                 resets = <&tegra_car 54>;
 282                 reset-names = "i2c";
 283                 dmas = <&apbdma 22>, <&apbdma 22>;
 284                 dma-names = "rx", "tx";
 285                 status = "disabled";
 286         };
 287
 288         i2c@0,7000c500 {
 289                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 290                 reg = <0x0 0x7000c500 0x0 0x100>;
 291                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 295                 clock-names = "div-clk";
 296                 resets = <&tegra_car 67>;
 297                 reset-names = "i2c";
 298                 dmas = <&apbdma 23>, <&apbdma 23>;
 299                 dma-names = "rx", "tx";
 300                 status = "disabled";
 301         };
 302
 303         i2c@0,7000c700 {
 304                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 305                 reg = <0x0 0x7000c700 0x0 0x100>;
 306                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 310                 clock-names = "div-clk";
 311                 resets = <&tegra_car 103>;
 312                 reset-names = "i2c";
 313                 dmas = <&apbdma 26>, <&apbdma 26>;
 314                 dma-names = "rx", "tx";
 315                 status = "disabled";
 316         };
 317
 318         i2c@0,7000d000 {
 319                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 320                 reg = <0x0 0x7000d000 0x0 0x100>;
 321                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 325                 clock-names = "div-clk";
 326                 resets = <&tegra_car 47>;
 327                 reset-names = "i2c";
 328                 dmas = <&apbdma 24>, <&apbdma 24>;
 329                 dma-names = "rx", "tx";
 330                 status = "disabled";
 331         };
 332
 333         i2c@0,7000d100 {
 334                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 335                 reg = <0x0 0x7000d100 0x0 0x100>;
 336                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 340                 clock-names = "div-clk";
 341                 resets = <&tegra_car 166>;
 342                 reset-names = "i2c";
 343                 dmas = <&apbdma 30>, <&apbdma 30>;
 344                 dma-names = "rx", "tx";
 345                 status = "disabled";
 346         };
 347
 348         spi@0,7000d400 {
 349                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 350                 reg = <0x0 0x7000d400 0x0 0x200>;
 351                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 355                 clock-names = "spi";
 356                 resets = <&tegra_car 41>;
 357                 reset-names = "spi";
 358                 dmas = <&apbdma 15>, <&apbdma 15>;
 359                 dma-names = "rx", "tx";
 360                 status = "disabled";
 361         };
 362
 363         spi@0,7000d600 {
 364                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 365                 reg = <0x0 0x7000d600 0x0 0x200>;
 366                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 370                 clock-names = "spi";
 371                 resets = <&tegra_car 44>;
 372                 reset-names = "spi";
 373                 dmas = <&apbdma 16>, <&apbdma 16>;
 374                 dma-names = "rx", "tx";
 375                 status = "disabled";
 376         };
 377
 378         spi@0,7000d800 {
 379                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 380                 reg = <0x0 0x7000d800 0x0 0x200>;
 381                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 385                 clock-names = "spi";
 386                 resets = <&tegra_car 46>;
 387                 reset-names = "spi";
 388                 dmas = <&apbdma 17>, <&apbdma 17>;
 389                 dma-names = "rx", "tx";
 390                 status = "disabled";
 391         };
 392
 393         spi@0,7000da00 {
 394                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 395                 reg = <0x0 0x7000da00 0x0 0x200>;
 396                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 400                 clock-names = "spi";
 401                 resets = <&tegra_car 68>;
 402                 reset-names = "spi";
 403                 dmas = <&apbdma 18>, <&apbdma 18>;
 404                 dma-names = "rx", "tx";
 405                 status = "disabled";
 406         };
 407
 408         spi@0,7000dc00 {
 409                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 410                 reg = <0x0 0x7000dc00 0x0 0x200>;
 411                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 415                 clock-names = "spi";
 416                 resets = <&tegra_car 104>;
 417                 reset-names = "spi";
 418                 dmas = <&apbdma 27>, <&apbdma 27>;
 419                 dma-names = "rx", "tx";
 420                 status = "disabled";
 421         };
 422
 423         spi@0,7000de00 {
 424                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 425                 reg = <0x0 0x7000de00 0x0 0x200>;
 426                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 430                 clock-names = "spi";
 431                 resets = <&tegra_car 105>;
 432                 reset-names = "spi";
 433                 dmas = <&apbdma 28>, <&apbdma 28>;
 434                 dma-names = "rx", "tx";
 435                 status = "disabled";
 436         };
 437
 438         rtc@0,7000e000 {
 439                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 440                 reg = <0x0 0x7000e000 0x0 0x100>;
 441                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 443         };
 444
 445         pmc@0,7000e400 {
 446                 compatible = "nvidia,tegra124-pmc";
 447                 reg = <0x0 0x7000e400 0x0 0x400>;
 448                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 449                 clock-names = "pclk", "clk32k_in";
 450         };
 451
 452         sdhci@0,700b0000 {
 453                 compatible = "nvidia,tegra124-sdhci";
 454                 reg = <0x0 0x700b0000 0x0 0x200>;
 455                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 456                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 457                 resets = <&tegra_car 14>;
 458                 reset-names = "sdhci";
 459                 status = "disabled";
 460         };
 461
 462         sdhci@0,700b0200 {
 463                 compatible = "nvidia,tegra124-sdhci";
 464                 reg = <0x0 0x700b0200 0x0 0x200>;
 465                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 466                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 467                 resets = <&tegra_car 9>;
 468                 reset-names = "sdhci";
 469                 status = "disabled";
 470         };
 471
 472         sdhci@0,700b0400 {
 473                 compatible = "nvidia,tegra124-sdhci";
 474                 reg = <0x0 0x700b0400 0x0 0x200>;
 475                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 476                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 477                 resets = <&tegra_car 69>;
 478                 reset-names = "sdhci";
 479                 status = "disabled";
 480         };
 481
 482         sdhci@0,700b0600 {
 483                 compatible = "nvidia,tegra124-sdhci";
 484                 reg = <0x0 0x700b0600 0x0 0x200>;
 485                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 486                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 487                 resets = <&tegra_car 15>;
 488                 reset-names = "sdhci";
 489                 status = "disabled";
 490         };
 491
 492         ahub@0,70300000 {
 493                 compatible = "nvidia,tegra124-ahub";
 494                 reg = <0x0 0x70300000 0x0 0x200>,
 495                       <0x0 0x70300800 0x0 0x800>,
 496                       <0x0 0x70300200 0x0 0x600>;
 497                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 499                          <&tegra_car TEGRA124_CLK_APBIF>;
 500                 clock-names = "d_audio", "apbif";
 501                 resets = <&tegra_car 106>, /* d_audio */
 502                          <&tegra_car 107>, /* apbif */
 503                          <&tegra_car 30>,  /* i2s0 */
 504                          <&tegra_car 11>,  /* i2s1 */
 505                          <&tegra_car 18>,  /* i2s2 */
 506                          <&tegra_car 101>, /* i2s3 */
 507                          <&tegra_car 102>, /* i2s4 */
 508                          <&tegra_car 108>, /* dam0 */
 509                          <&tegra_car 109>, /* dam1 */
 510                          <&tegra_car 110>, /* dam2 */
 511                          <&tegra_car 10>,  /* spdif */
 512                          <&tegra_car 153>, /* amx */
 513                          <&tegra_car 185>, /* amx1 */
 514                          <&tegra_car 154>, /* adx */
 515                          <&tegra_car 180>, /* adx1 */
 516                          <&tegra_car 186>, /* afc0 */
 517                          <&tegra_car 187>, /* afc1 */
 518                          <&tegra_car 188>, /* afc2 */
 519                          <&tegra_car 189>, /* afc3 */
 520                          <&tegra_car 190>, /* afc4 */
 521                          <&tegra_car 191>; /* afc5 */
 522                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 523                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 524                               "spdif", "amx", "amx1", "adx", "adx1",
 525                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 526                 dmas = <&apbdma 1>, <&apbdma 1>,
 527                        <&apbdma 2>, <&apbdma 2>,
 528                        <&apbdma 3>, <&apbdma 3>,
 529                        <&apbdma 4>, <&apbdma 4>,
 530                        <&apbdma 6>, <&apbdma 6>,
 531                        <&apbdma 7>, <&apbdma 7>,
 532                        <&apbdma 12>, <&apbdma 12>,
 533                        <&apbdma 13>, <&apbdma 13>,
 534                        <&apbdma 14>, <&apbdma 14>,
 535                        <&apbdma 29>, <&apbdma 29>;
 536                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 537                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 538                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 539                             "rx9", "tx9";
 540                 ranges;
 541                 #address-cells = <2>;
 542                 #size-cells = <2>;
 543
 544                 tegra_i2s0: i2s@0,70301000 {
 545                         compatible = "nvidia,tegra124-i2s";
 546                         reg = <0x0 0x70301000 0x0 0x100>;
 547                         nvidia,ahub-cif-ids = <4 4>;
 548                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 549                         resets = <&tegra_car 30>;
 550                         reset-names = "i2s";
 551                         status = "disabled";
 552                 };
 553
 554                 tegra_i2s1: i2s@0,70301100 {
 555                         compatible = "nvidia,tegra124-i2s";
 556                         reg = <0x0 0x70301100 0x0 0x100>;
 557                         nvidia,ahub-cif-ids = <5 5>;
 558                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 559                         resets = <&tegra_car 11>;
 560                         reset-names = "i2s";
 561                         status = "disabled";
 562                 };
 563
 564                 tegra_i2s2: i2s@0,70301200 {
 565                         compatible = "nvidia,tegra124-i2s";
 566                         reg = <0x0 0x70301200 0x0 0x100>;
 567                         nvidia,ahub-cif-ids = <6 6>;
 568                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 569                         resets = <&tegra_car 18>;
 570                         reset-names = "i2s";
 571                         status = "disabled";
 572                 };
 573
 574                 tegra_i2s3: i2s@0,70301300 {
 575                         compatible = "nvidia,tegra124-i2s";
 576                         reg = <0x0 0x70301300 0x0 0x100>;
 577                         nvidia,ahub-cif-ids = <7 7>;
 578                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 579                         resets = <&tegra_car 101>;
 580                         reset-names = "i2s";
 581                         status = "disabled";
 582                 };
 583
 584                 tegra_i2s4: i2s@0,70301400 {
 585                         compatible = "nvidia,tegra124-i2s";
 586                         reg = <0x0 0x70301400 0x0 0x100>;
 587                         nvidia,ahub-cif-ids = <8 8>;
 588                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 589                         resets = <&tegra_car 102>;
 590                         reset-names = "i2s";
 591                         status = "disabled";
 592                 };
 593         };
 594
 595         usb@0,7d000000 {
 596                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 597                 reg = <0x0 0x7d000000 0x0 0x4000>;
 598                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 599                 phy_type = "utmi";
 600                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
 601                 resets = <&tegra_car 22>;
 602                 reset-names = "usb";
 603                 nvidia,phy = <&phy1>;
 604                 status = "disabled";
 605         };
 606
 607         phy1: usb-phy@0,7d000000 {
 608                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 609                 reg = <0x0 0x7d000000 0x0 0x4000>,
 610                       <0x0 0x7d000000 0x0 0x4000>;
 611                 phy_type = "utmi";
 612                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
 613                          <&tegra_car TEGRA124_CLK_PLL_U>,
 614                          <&tegra_car TEGRA124_CLK_USBD>;
 615                 clock-names = "reg", "pll_u", "utmi-pads";
 616                 nvidia,hssync-start-delay = <0>;
 617                 nvidia,idle-wait-delay = <17>;
 618                 nvidia,elastic-limit = <16>;
 619                 nvidia,term-range-adj = <6>;
 620                 nvidia,xcvr-setup = <9>;
 621                 nvidia,xcvr-lsfslew = <0>;
 622                 nvidia,xcvr-lsrslew = <3>;
 623                 nvidia,hssquelch-level = <2>;
 624                 nvidia,hsdiscon-level = <5>;
 625                 nvidia,xcvr-hsslew = <12>;
 626                 status = "disabled";
 627         };
 628
 629         usb@0,7d004000 {
 630                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 631                 reg = <0x0 0x7d004000 0x0 0x4000>;
 632                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 633                 phy_type = "utmi";
 634                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
 635                 resets = <&tegra_car 58>;
 636                 reset-names = "usb";
 637                 nvidia,phy = <&phy2>;
 638                 status = "disabled";
 639         };
 640
 641         phy2: usb-phy@0,7d004000 {
 642                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 643                 reg = <0x0 0x7d004000 0x0 0x4000>,
 644                       <0x0 0x7d000000 0x0 0x4000>;
 645                 phy_type = "utmi";
 646                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
 647                          <&tegra_car TEGRA124_CLK_PLL_U>,
 648                          <&tegra_car TEGRA124_CLK_USBD>;
 649                 clock-names = "reg", "pll_u", "utmi-pads";
 650                 nvidia,hssync-start-delay = <0>;
 651                 nvidia,idle-wait-delay = <17>;
 652                 nvidia,elastic-limit = <16>;
 653                 nvidia,term-range-adj = <6>;
 654                 nvidia,xcvr-setup = <9>;
 655                 nvidia,xcvr-lsfslew = <0>;
 656                 nvidia,xcvr-lsrslew = <3>;
 657                 nvidia,hssquelch-level = <2>;
 658                 nvidia,hsdiscon-level = <5>;
 659                 nvidia,xcvr-hsslew = <12>;
 660                 status = "disabled";
 661         };
 662
 663         usb@0,7d008000 {
 664                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 665                 reg = <0x0 0x7d008000 0x0 0x4000>;
 666                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 667                 phy_type = "utmi";
 668                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
 669                 resets = <&tegra_car 59>;
 670                 reset-names = "usb";
 671                 nvidia,phy = <&phy3>;
 672                 status = "disabled";
 673         };
 674
 675         phy3: usb-phy@0,7d008000 {
 676                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
 677                 reg = <0x0 0x7d008000 0x0 0x4000>,
 678                       <0x0 0x7d000000 0x0 0x4000>;
 679                 phy_type = "utmi";
 680                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
 681                          <&tegra_car TEGRA124_CLK_PLL_U>,
 682                          <&tegra_car TEGRA124_CLK_USBD>;
 683                 clock-names = "reg", "pll_u", "utmi-pads";
 684                 nvidia,hssync-start-delay = <0>;
 685                 nvidia,idle-wait-delay = <17>;
 686                 nvidia,elastic-limit = <16>;
 687                 nvidia,term-range-adj = <6>;
 688                 nvidia,xcvr-setup = <9>;
 689                 nvidia,xcvr-lsfslew = <0>;
 690                 nvidia,xcvr-lsrslew = <3>;
 691                 nvidia,hssquelch-level = <2>;
 692                 nvidia,hsdiscon-level = <5>;
 693                 nvidia,xcvr-hsslew = <12>;
 694                 status = "disabled";
 695         };
 696
 697         cpus {
 698                 #address-cells = <1>;
 699                 #size-cells = <0>;
 700
 701                 cpu@0 {
 702                         device_type = "cpu";
 703                         compatible = "arm,cortex-a15";
 704                         reg = <0>;
 705                 };
 706
 707                 cpu@1 {
 708                         device_type = "cpu";
 709                         compatible = "arm,cortex-a15";
 710                         reg = <1>;
 711                 };
 712
 713                 cpu@2 {
 714                         device_type = "cpu";
 715                         compatible = "arm,cortex-a15";
 716                         reg = <2>;
 717                 };
 718
 719                 cpu@3 {
 720                         device_type = "cpu";
 721                         compatible = "arm,cortex-a15";
 722                         reg = <3>;
 723                 };
 724         };
 725
 726         timer {
 727                 compatible = "arm,armv7-timer";
 728                 interrupts = <GIC_PPI 13
 729                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 730                              <GIC_PPI 14
 731                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 732                              <GIC_PPI 11
 733                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 734                              <GIC_PPI 10
 735                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 736         };
 737 };