1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/reset/tegra124-car.h>
7 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include "skeleton.dtsi"
12 compatible = "nvidia,tegra124";
13 interrupt-parent = <&lic>;
17 pcie-controller@01003000 {
18 compatible = "nvidia,tegra124-pcie";
20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
23 reg-names = "pads", "afi", "cs";
24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
26 interrupt-names = "intr", "msi";
28 #interrupt-cells = <1>;
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
43 <&tegra_car TEGRA124_CLK_AFI>,
44 <&tegra_car TEGRA124_CLK_PLL_E>,
45 <&tegra_car TEGRA124_CLK_CML0>;
46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
50 reset-names = "pex", "afi", "pcie_x";
55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
63 nvidia,num-lanes = <2>;
68 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
69 reg = <0x001000 0 0 0 0>;
76 nvidia,num-lanes = <1>;
81 compatible = "nvidia,tegra124-host1x", "simple-bus";
82 reg = <0x0 0x50000000 0x0 0x00034000>;
83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
84 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
85 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
86 resets = <&tegra_car 28>;
87 reset-names = "host1x";
92 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
95 compatible = "nvidia,tegra124-dc";
96 reg = <0x0 0x54200000 0x0 0x00040000>;
97 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
99 <&tegra_car TEGRA124_CLK_PLL_P>;
100 clock-names = "dc", "parent";
101 resets = <&tegra_car 27>;
104 iommus = <&mc TEGRA_SWGROUP_DC>;
110 compatible = "nvidia,tegra124-dc";
111 reg = <0x0 0x54240000 0x0 0x00040000>;
112 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
114 <&tegra_car TEGRA124_CLK_PLL_P>;
115 clock-names = "dc", "parent";
116 resets = <&tegra_car 26>;
119 iommus = <&mc TEGRA_SWGROUP_DCB>;
125 compatible = "nvidia,tegra124-hdmi";
126 reg = <0x0 0x54280000 0x0 0x00040000>;
127 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
129 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
130 clock-names = "hdmi", "parent";
131 resets = <&tegra_car 51>;
132 reset-names = "hdmi";
137 compatible = "nvidia,tegra124-sor";
138 reg = <0x0 0x54540000 0x0 0x00040000>;
139 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
141 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
142 <&tegra_car TEGRA124_CLK_PLL_DP>,
143 <&tegra_car TEGRA124_CLK_CLK_M>;
144 clock-names = "sor", "parent", "dp", "safe";
145 resets = <&tegra_car 182>;
150 dpaux: dpaux@545c0000 {
151 compatible = "nvidia,tegra124-dpaux";
152 reg = <0x0 0x545c0000 0x0 0x00040000>;
153 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
155 <&tegra_car TEGRA124_CLK_PLL_DP>;
156 clock-names = "dpaux", "parent";
157 resets = <&tegra_car 181>;
158 reset-names = "dpaux";
163 gic: interrupt-controller@50041000 {
164 compatible = "arm,cortex-a15-gic";
165 #interrupt-cells = <3>;
166 interrupt-controller;
167 reg = <0x0 0x50041000 0x0 0x1000>,
168 <0x0 0x50042000 0x0 0x1000>,
169 <0x0 0x50044000 0x0 0x2000>,
170 <0x0 0x50046000 0x0 0x2000>;
171 interrupts = <GIC_PPI 9
172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
173 interrupt-parent = <&gic>;
177 * Please keep the following 0, notation in place as a former mainline
178 * U-Boot version was looking for that particular notation in order to
179 * perform required fix-ups on that GPU node.
182 compatible = "nvidia,gk20a";
183 reg = <0x0 0x57000000 0x0 0x01000000>,
184 <0x0 0x58000000 0x0 0x01000000>;
185 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-names = "stall", "nonstall";
188 clocks = <&tegra_car TEGRA124_CLK_GPU>,
189 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
190 clock-names = "gpu", "pwr";
191 resets = <&tegra_car 184>;
194 iommus = <&mc TEGRA_SWGROUP_GPU>;
199 lic: interrupt-controller@60004000 {
200 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
201 reg = <0x0 0x60004000 0x0 0x100>,
202 <0x0 0x60004100 0x0 0x100>,
203 <0x0 0x60004200 0x0 0x100>,
204 <0x0 0x60004300 0x0 0x100>,
205 <0x0 0x60004400 0x0 0x100>;
206 interrupt-controller;
207 #interrupt-cells = <3>;
208 interrupt-parent = <&gic>;
212 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
213 reg = <0x0 0x60005000 0x0 0x400>;
214 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
223 tegra_car: clock@60006000 {
224 compatible = "nvidia,tegra124-car";
225 reg = <0x0 0x60006000 0x0 0x1000>;
228 nvidia,external-memory-controller = <&emc>;
231 flow-controller@60007000 {
232 compatible = "nvidia,tegra124-flowctrl";
233 reg = <0x0 0x60007000 0x0 0x1000>;
237 compatible = "nvidia,tegra124-actmon";
238 reg = <0x0 0x6000c800 0x0 0x400>;
239 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
241 <&tegra_car TEGRA124_CLK_EMC>;
242 clock-names = "actmon", "emc";
243 resets = <&tegra_car 119>;
244 reset-names = "actmon";
247 gpio: gpio@6000d000 {
248 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
249 reg = <0x0 0x6000d000 0x0 0x1000>;
250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
260 #interrupt-cells = <2>;
261 interrupt-controller;
263 gpio-ranges = <&pinmux 0 0 251>;
267 apbdma: dma@60020000 {
268 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
269 reg = <0x0 0x60020000 0x0 0x1400>;
270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
303 resets = <&tegra_car 34>;
309 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
310 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
311 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
314 pinmux: pinmux@70000868 {
315 compatible = "nvidia,tegra124-pinmux";
316 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
317 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
318 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
322 * There are two serial driver i.e. 8250 based simple serial
323 * driver and APB DMA based serial driver for higher baudrate
324 * and performace. To enable the 8250 based driver, the compatible
325 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
326 * the APB DMA based serial driver, the compatible is
327 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
329 uarta: serial@70006000 {
330 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
331 reg = <0x0 0x70006000 0x0 0x40>;
333 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
335 resets = <&tegra_car 6>;
336 reset-names = "serial";
337 dmas = <&apbdma 8>, <&apbdma 8>;
338 dma-names = "rx", "tx";
342 uartb: serial@70006040 {
343 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
344 reg = <0x0 0x70006040 0x0 0x40>;
346 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
348 resets = <&tegra_car 7>;
349 reset-names = "serial";
350 dmas = <&apbdma 9>, <&apbdma 9>;
351 dma-names = "rx", "tx";
355 uartc: serial@70006200 {
356 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
357 reg = <0x0 0x70006200 0x0 0x40>;
359 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
361 resets = <&tegra_car 55>;
362 reset-names = "serial";
363 dmas = <&apbdma 10>, <&apbdma 10>;
364 dma-names = "rx", "tx";
368 uartd: serial@70006300 {
369 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
370 reg = <0x0 0x70006300 0x0 0x40>;
372 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
374 resets = <&tegra_car 65>;
375 reset-names = "serial";
376 dmas = <&apbdma 19>, <&apbdma 19>;
377 dma-names = "rx", "tx";
382 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
383 reg = <0x0 0x7000a000 0x0 0x100>;
385 clocks = <&tegra_car TEGRA124_CLK_PWM>;
386 resets = <&tegra_car 17>;
392 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
393 reg = <0x0 0x7000c000 0x0 0x100>;
394 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
395 #address-cells = <1>;
397 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
398 clock-names = "div-clk";
399 resets = <&tegra_car 12>;
401 dmas = <&apbdma 21>, <&apbdma 21>;
402 dma-names = "rx", "tx";
407 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
408 reg = <0x0 0x7000c400 0x0 0x100>;
409 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
410 #address-cells = <1>;
412 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
413 clock-names = "div-clk";
414 resets = <&tegra_car 54>;
416 dmas = <&apbdma 22>, <&apbdma 22>;
417 dma-names = "rx", "tx";
422 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
423 reg = <0x0 0x7000c500 0x0 0x100>;
424 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
425 #address-cells = <1>;
427 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
428 clock-names = "div-clk";
429 resets = <&tegra_car 67>;
431 dmas = <&apbdma 23>, <&apbdma 23>;
432 dma-names = "rx", "tx";
437 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
438 reg = <0x0 0x7000c700 0x0 0x100>;
439 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
442 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
443 clock-names = "div-clk";
444 resets = <&tegra_car 103>;
446 dmas = <&apbdma 26>, <&apbdma 26>;
447 dma-names = "rx", "tx";
452 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
453 reg = <0x0 0x7000d000 0x0 0x100>;
454 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
457 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
458 clock-names = "div-clk";
459 resets = <&tegra_car 47>;
461 dmas = <&apbdma 24>, <&apbdma 24>;
462 dma-names = "rx", "tx";
467 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
468 reg = <0x0 0x7000d100 0x0 0x100>;
469 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
470 #address-cells = <1>;
472 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
473 clock-names = "div-clk";
474 resets = <&tegra_car 166>;
476 dmas = <&apbdma 30>, <&apbdma 30>;
477 dma-names = "rx", "tx";
482 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
483 reg = <0x0 0x7000d400 0x0 0x200>;
484 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
485 #address-cells = <1>;
487 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
489 resets = <&tegra_car 41>;
491 dmas = <&apbdma 15>, <&apbdma 15>;
492 dma-names = "rx", "tx";
497 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
498 reg = <0x0 0x7000d600 0x0 0x200>;
499 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
500 #address-cells = <1>;
502 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
504 resets = <&tegra_car 44>;
506 dmas = <&apbdma 16>, <&apbdma 16>;
507 dma-names = "rx", "tx";
512 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
513 reg = <0x0 0x7000d800 0x0 0x200>;
514 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
515 #address-cells = <1>;
517 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
519 resets = <&tegra_car 46>;
521 dmas = <&apbdma 17>, <&apbdma 17>;
522 dma-names = "rx", "tx";
527 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
528 reg = <0x0 0x7000da00 0x0 0x200>;
529 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
530 #address-cells = <1>;
532 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
534 resets = <&tegra_car 68>;
536 dmas = <&apbdma 18>, <&apbdma 18>;
537 dma-names = "rx", "tx";
542 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
543 reg = <0x0 0x7000dc00 0x0 0x200>;
544 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
545 #address-cells = <1>;
547 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
549 resets = <&tegra_car 104>;
551 dmas = <&apbdma 27>, <&apbdma 27>;
552 dma-names = "rx", "tx";
557 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
558 reg = <0x0 0x7000de00 0x0 0x200>;
559 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>;
562 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
564 resets = <&tegra_car 105>;
566 dmas = <&apbdma 28>, <&apbdma 28>;
567 dma-names = "rx", "tx";
572 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
573 reg = <0x0 0x7000e000 0x0 0x100>;
574 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&tegra_car TEGRA124_CLK_RTC>;
579 compatible = "nvidia,tegra124-pmc";
580 reg = <0x0 0x7000e400 0x0 0x400>;
581 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
582 clock-names = "pclk", "clk32k_in";
586 compatible = "nvidia,tegra124-efuse";
587 reg = <0x0 0x7000f800 0x0 0x400>;
588 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
589 clock-names = "fuse";
590 resets = <&tegra_car 39>;
591 reset-names = "fuse";
594 mc: memory-controller@70019000 {
595 compatible = "nvidia,tegra124-mc";
596 reg = <0x0 0x70019000 0x0 0x1000>;
597 clocks = <&tegra_car TEGRA124_CLK_MC>;
600 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
606 compatible = "nvidia,tegra124-emc";
607 reg = <0x0 0x7001b000 0x0 0x1000>;
609 nvidia,memory-controller = <&mc>;
613 compatible = "nvidia,tegra124-ahci";
614 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
615 <0x0 0x70020000 0x0 0x7000>; /* SATA */
616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&tegra_car TEGRA124_CLK_SATA>,
618 <&tegra_car TEGRA124_CLK_SATA_OOB>,
619 <&tegra_car TEGRA124_CLK_CML1>,
620 <&tegra_car TEGRA124_CLK_PLL_E>;
621 clock-names = "sata", "sata-oob", "cml1", "pll_e";
622 resets = <&tegra_car 124>,
625 reset-names = "sata", "sata-oob", "sata-cold";
630 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
631 reg = <0x0 0x70030000 0x0 0x10000>;
632 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&tegra_car TEGRA124_CLK_HDA>,
634 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
635 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
636 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
637 resets = <&tegra_car 125>, /* hda */
638 <&tegra_car 128>, /* hda2hdmi */
639 <&tegra_car 111>; /* hda2codec_2x */
640 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
645 compatible = "nvidia,tegra124-xusb";
646 reg = <0x0 0x70090000 0x0 0x8000>,
647 <0x0 0x70098000 0x0 0x1000>,
648 <0x0 0x70099000 0x0 0x1000>;
649 reg-names = "hcd", "fpci", "ipfs";
651 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
655 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
656 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
657 <&tegra_car TEGRA124_CLK_XUSB_SS>,
658 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
659 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
660 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
661 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
662 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
663 <&tegra_car TEGRA124_CLK_CLK_M>,
664 <&tegra_car TEGRA124_CLK_PLL_E>;
665 clock-names = "xusb_host", "xusb_host_src",
666 "xusb_falcon_src", "xusb_ss",
667 "xusb_ss_div2", "xusb_ss_src",
668 "xusb_hs_src", "xusb_fs_src",
669 "pll_u_480m", "clk_m", "pll_e";
670 resets = <&tegra_car 89>, <&tegra_car 156>,
672 reset-names = "xusb_host", "xusb_ss", "xusb_src";
674 nvidia,xusb-padctl = <&padctl>;
679 padctl: padctl@7009f000 {
680 compatible = "nvidia,tegra124-xusb-padctl";
681 reg = <0x0 0x7009f000 0x0 0x1000>;
682 resets = <&tegra_car 142>;
683 reset-names = "padctl";
813 compatible = "nvidia,tegra124-sdhci";
814 reg = <0x0 0x700b0000 0x0 0x200>;
815 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
817 resets = <&tegra_car 14>;
818 reset-names = "sdhci";
823 compatible = "nvidia,tegra124-sdhci";
824 reg = <0x0 0x700b0200 0x0 0x200>;
825 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
827 resets = <&tegra_car 9>;
828 reset-names = "sdhci";
833 compatible = "nvidia,tegra124-sdhci";
834 reg = <0x0 0x700b0400 0x0 0x200>;
835 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
837 resets = <&tegra_car 69>;
838 reset-names = "sdhci";
843 compatible = "nvidia,tegra124-sdhci";
844 reg = <0x0 0x700b0600 0x0 0x200>;
845 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
847 resets = <&tegra_car 15>;
848 reset-names = "sdhci";
852 soctherm: thermal-sensor@700e2000 {
853 compatible = "nvidia,tegra124-soctherm";
854 reg = <0x0 0x700e2000 0x0 0x1000>;
855 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
857 <&tegra_car TEGRA124_CLK_SOC_THERM>;
858 clock-names = "tsensor", "soctherm";
859 resets = <&tegra_car 78>;
860 reset-names = "soctherm";
861 #thermal-sensor-cells = <1>;
864 dfll: clock@70110000 {
865 compatible = "nvidia,tegra124-dfll";
866 reg = <0 0x70110000 0 0x100>, /* DFLL control */
867 <0 0x70110000 0 0x100>, /* I2C output control */
868 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
869 <0 0x70110200 0 0x100>; /* Look-up table RAM */
870 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
872 <&tegra_car TEGRA124_CLK_DFLL_REF>,
873 <&tegra_car TEGRA124_CLK_I2C5>;
874 clock-names = "soc", "ref", "i2c";
875 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
876 reset-names = "dvco";
878 clock-output-names = "dfllCPU_out";
879 nvidia,sample-rate = <12500>;
880 nvidia,droop-ctrl = <0x00000f00>;
881 nvidia,force-mode = <1>;
889 compatible = "nvidia,tegra124-ahub";
890 reg = <0x0 0x70300000 0x0 0x200>,
891 <0x0 0x70300800 0x0 0x800>,
892 <0x0 0x70300200 0x0 0x600>;
893 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
895 <&tegra_car TEGRA124_CLK_APBIF>;
896 clock-names = "d_audio", "apbif";
897 resets = <&tegra_car 106>, /* d_audio */
898 <&tegra_car 107>, /* apbif */
899 <&tegra_car 30>, /* i2s0 */
900 <&tegra_car 11>, /* i2s1 */
901 <&tegra_car 18>, /* i2s2 */
902 <&tegra_car 101>, /* i2s3 */
903 <&tegra_car 102>, /* i2s4 */
904 <&tegra_car 108>, /* dam0 */
905 <&tegra_car 109>, /* dam1 */
906 <&tegra_car 110>, /* dam2 */
907 <&tegra_car 10>, /* spdif */
908 <&tegra_car 153>, /* amx */
909 <&tegra_car 185>, /* amx1 */
910 <&tegra_car 154>, /* adx */
911 <&tegra_car 180>, /* adx1 */
912 <&tegra_car 186>, /* afc0 */
913 <&tegra_car 187>, /* afc1 */
914 <&tegra_car 188>, /* afc2 */
915 <&tegra_car 189>, /* afc3 */
916 <&tegra_car 190>, /* afc4 */
917 <&tegra_car 191>; /* afc5 */
918 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
919 "i2s3", "i2s4", "dam0", "dam1", "dam2",
920 "spdif", "amx", "amx1", "adx", "adx1",
921 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
922 dmas = <&apbdma 1>, <&apbdma 1>,
923 <&apbdma 2>, <&apbdma 2>,
924 <&apbdma 3>, <&apbdma 3>,
925 <&apbdma 4>, <&apbdma 4>,
926 <&apbdma 6>, <&apbdma 6>,
927 <&apbdma 7>, <&apbdma 7>,
928 <&apbdma 12>, <&apbdma 12>,
929 <&apbdma 13>, <&apbdma 13>,
930 <&apbdma 14>, <&apbdma 14>,
931 <&apbdma 29>, <&apbdma 29>;
932 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
933 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
934 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
937 #address-cells = <2>;
940 tegra_i2s0: i2s@70301000 {
941 compatible = "nvidia,tegra124-i2s";
942 reg = <0x0 0x70301000 0x0 0x100>;
943 nvidia,ahub-cif-ids = <4 4>;
944 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
945 resets = <&tegra_car 30>;
950 tegra_i2s1: i2s@70301100 {
951 compatible = "nvidia,tegra124-i2s";
952 reg = <0x0 0x70301100 0x0 0x100>;
953 nvidia,ahub-cif-ids = <5 5>;
954 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
955 resets = <&tegra_car 11>;
960 tegra_i2s2: i2s@70301200 {
961 compatible = "nvidia,tegra124-i2s";
962 reg = <0x0 0x70301200 0x0 0x100>;
963 nvidia,ahub-cif-ids = <6 6>;
964 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
965 resets = <&tegra_car 18>;
970 tegra_i2s3: i2s@70301300 {
971 compatible = "nvidia,tegra124-i2s";
972 reg = <0x0 0x70301300 0x0 0x100>;
973 nvidia,ahub-cif-ids = <7 7>;
974 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
975 resets = <&tegra_car 101>;
980 tegra_i2s4: i2s@70301400 {
981 compatible = "nvidia,tegra124-i2s";
982 reg = <0x0 0x70301400 0x0 0x100>;
983 nvidia,ahub-cif-ids = <8 8>;
984 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
985 resets = <&tegra_car 102>;
992 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
993 reg = <0x0 0x7d000000 0x0 0x4000>;
994 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA124_CLK_USBD>;
997 resets = <&tegra_car 22>;
999 nvidia,phy = <&phy1>;
1000 status = "disabled";
1003 phy1: usb-phy@7d000000 {
1004 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1005 reg = <0x0 0x7d000000 0x0 0x4000>,
1006 <0x0 0x7d000000 0x0 0x4000>;
1008 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1009 <&tegra_car TEGRA124_CLK_PLL_U>,
1010 <&tegra_car TEGRA124_CLK_USBD>;
1011 clock-names = "reg", "pll_u", "utmi-pads";
1012 resets = <&tegra_car 22>, <&tegra_car 22>;
1013 reset-names = "usb", "utmi-pads";
1014 nvidia,hssync-start-delay = <0>;
1015 nvidia,idle-wait-delay = <17>;
1016 nvidia,elastic-limit = <16>;
1017 nvidia,term-range-adj = <6>;
1018 nvidia,xcvr-setup = <9>;
1019 nvidia,xcvr-lsfslew = <0>;
1020 nvidia,xcvr-lsrslew = <3>;
1021 nvidia,hssquelch-level = <2>;
1022 nvidia,hsdiscon-level = <5>;
1023 nvidia,xcvr-hsslew = <12>;
1024 nvidia,has-utmi-pad-registers;
1025 status = "disabled";
1029 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1030 reg = <0x0 0x7d004000 0x0 0x4000>;
1031 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1034 resets = <&tegra_car 58>;
1035 reset-names = "usb";
1036 nvidia,phy = <&phy2>;
1037 status = "disabled";
1040 phy2: usb-phy@7d004000 {
1041 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1042 reg = <0x0 0x7d004000 0x0 0x4000>,
1043 <0x0 0x7d000000 0x0 0x4000>;
1045 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1046 <&tegra_car TEGRA124_CLK_PLL_U>,
1047 <&tegra_car TEGRA124_CLK_USBD>;
1048 clock-names = "reg", "pll_u", "utmi-pads";
1049 resets = <&tegra_car 58>, <&tegra_car 22>;
1050 reset-names = "usb", "utmi-pads";
1051 nvidia,hssync-start-delay = <0>;
1052 nvidia,idle-wait-delay = <17>;
1053 nvidia,elastic-limit = <16>;
1054 nvidia,term-range-adj = <6>;
1055 nvidia,xcvr-setup = <9>;
1056 nvidia,xcvr-lsfslew = <0>;
1057 nvidia,xcvr-lsrslew = <3>;
1058 nvidia,hssquelch-level = <2>;
1059 nvidia,hsdiscon-level = <5>;
1060 nvidia,xcvr-hsslew = <12>;
1061 status = "disabled";
1065 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1066 reg = <0x0 0x7d008000 0x0 0x4000>;
1067 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1070 resets = <&tegra_car 59>;
1071 reset-names = "usb";
1072 nvidia,phy = <&phy3>;
1073 status = "disabled";
1076 phy3: usb-phy@7d008000 {
1077 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1078 reg = <0x0 0x7d008000 0x0 0x4000>,
1079 <0x0 0x7d000000 0x0 0x4000>;
1081 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1082 <&tegra_car TEGRA124_CLK_PLL_U>,
1083 <&tegra_car TEGRA124_CLK_USBD>;
1084 clock-names = "reg", "pll_u", "utmi-pads";
1085 resets = <&tegra_car 59>, <&tegra_car 22>;
1086 reset-names = "usb", "utmi-pads";
1087 nvidia,hssync-start-delay = <0>;
1088 nvidia,idle-wait-delay = <17>;
1089 nvidia,elastic-limit = <16>;
1090 nvidia,term-range-adj = <6>;
1091 nvidia,xcvr-setup = <9>;
1092 nvidia,xcvr-lsfslew = <0>;
1093 nvidia,xcvr-lsrslew = <3>;
1094 nvidia,hssquelch-level = <2>;
1095 nvidia,hsdiscon-level = <5>;
1096 nvidia,xcvr-hsslew = <12>;
1097 status = "disabled";
1101 #address-cells = <1>;
1105 device_type = "cpu";
1106 compatible = "arm,cortex-a15";
1109 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1110 <&tegra_car TEGRA124_CLK_CCLK_LP>,
1111 <&tegra_car TEGRA124_CLK_PLL_X>,
1112 <&tegra_car TEGRA124_CLK_PLL_P>,
1114 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1115 /* FIXME: what's the actual transition time? */
1116 clock-latency = <300000>;
1120 device_type = "cpu";
1121 compatible = "arm,cortex-a15";
1126 device_type = "cpu";
1127 compatible = "arm,cortex-a15";
1132 device_type = "cpu";
1133 compatible = "arm,cortex-a15";
1139 compatible = "arm,cortex-a15-pmu";
1140 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1142 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1143 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1144 interrupt-affinity = <&{/cpus/cpu@0}>,
1152 polling-delay-passive = <1000>;
1153 polling-delay = <1000>;
1156 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1160 polling-delay-passive = <1000>;
1161 polling-delay = <1000>;
1164 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1168 polling-delay-passive = <1000>;
1169 polling-delay = <1000>;
1172 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1176 polling-delay-passive = <1000>;
1177 polling-delay = <1000>;
1180 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1185 compatible = "arm,armv7-timer";
1186 interrupts = <GIC_PPI 13
1187 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1189 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1191 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1194 interrupt-parent = <&gic>;