arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4
   5 / {
   6         compatible = "nvidia,tegra124";
   7         interrupt-parent = <&gic>;
   8
   9         gic: interrupt-controller@50041000 {
  10                 compatible = "arm,cortex-a15-gic";
  11                 #interrupt-cells = <3>;
  12                 interrupt-controller;
  13                 reg = <0x50041000 0x1000>,
  14                       <0x50042000 0x1000>,
  15                       <0x50044000 0x2000>,
  16                       <0x50046000 0x2000>;
  17                 interrupts = <GIC_PPI 9
  18                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  19         };
  20
  21         timer@60005000 {
  22                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
  23                 reg = <0x60005000 0x400>;
  24                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  25                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  26                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  27                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  28                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  29                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  30         };
  31
  32         /*
  33          * There are two serial driver i.e. 8250 based simple serial
  34          * driver and APB DMA based serial driver for higher baudrate
  35          * and performace. To enable the 8250 based driver, the compatible
  36          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
  37          * the APB DMA based serial driver, the comptible is
  38          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
  39          */
  40         serial@70006000 {
  41                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  42                 reg = <0x70006000 0x40>;
  43                 reg-shift = <2>;
  44                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  45                 status = "disabled";
  46         };
  47
  48         serial@70006040 {
  49                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  50                 reg = <0x70006040 0x40>;
  51                 reg-shift = <2>;
  52                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  53                 status = "disabled";
  54         };
  55
  56         serial@70006200 {
  57                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  58                 reg = <0x70006200 0x40>;
  59                 reg-shift = <2>;
  60                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  61                 status = "disabled";
  62         };
  63
  64         serial@70006300 {
  65                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  66                 reg = <0x70006300 0x40>;
  67                 reg-shift = <2>;
  68                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  69                 status = "disabled";
  70         };
  71
  72         serial@70006400 {
  73                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  74                 reg = <0x70006400 0x40>;
  75                 reg-shift = <2>;
  76                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  77                 status = "disabled";
  78         };
  79
  80         rtc@7000e000 {
  81                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
  82                 reg = <0x7000e000 0x100>;
  83                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  84         };
  85
  86         pmc@7000e400 {
  87                 compatible = "nvidia,tegra124-pmc";
  88                 reg = <0x7000e400 0x400>;
  89         };
  90
  91         cpus {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94
  95                 cpu@0 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a15";
  98                         reg = <0>;
  99                 };
 100
 101                 cpu@1 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a15";
 104                         reg = <1>;
 105                 };
 106
 107                 cpu@2 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a15";
 110                         reg = <2>;
 111                 };
 112
 113                 cpu@3 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a15";
 116                         reg = <3>;
 117                 };
 118         };
 119
 120         timer {
 121                 compatible = "arm,armv7-timer";
 122                 interrupts = <GIC_PPI 13
 123                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 124                              <GIC_PPI 14
 125                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 126                              <GIC_PPI 11
 127                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 128                              <GIC_PPI 10
 129                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 130         };
 131 };