arch/arm/boot/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         aliases {
   8                 serial0 = &uarta;
   9                 serial1 = &uartb;
  10                 serial2 = &uartc;
  11                 serial3 = &uartd;
  12                 serial4 = &uarte;
  13         };
  14
  15         host1x {
  16                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  17                 reg = <0x50000000 0x00024000>;
  18                 interrupts = <0 65 0x04   /* mpcore syncpt */
  19                               0 67 0x04>; /* mpcore general */
  20                 clocks = <&tegra_car 28>;
  21
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24
  25                 ranges = <0x54000000 0x54000000 0x04000000>;
  26
  27                 mpe {
  28                         compatible = "nvidia,tegra20-mpe";
  29                         reg = <0x54040000 0x00040000>;
  30                         interrupts = <0 68 0x04>;
  31                         clocks = <&tegra_car 60>;
  32                 };
  33
  34                 vi {
  35                         compatible = "nvidia,tegra20-vi";
  36                         reg = <0x54080000 0x00040000>;
  37                         interrupts = <0 69 0x04>;
  38                         clocks = <&tegra_car 100>;
  39                 };
  40
  41                 epp {
  42                         compatible = "nvidia,tegra20-epp";
  43                         reg = <0x540c0000 0x00040000>;
  44                         interrupts = <0 70 0x04>;
  45                         clocks = <&tegra_car 19>;
  46                 };
  47
  48                 isp {
  49                         compatible = "nvidia,tegra20-isp";
  50                         reg = <0x54100000 0x00040000>;
  51                         interrupts = <0 71 0x04>;
  52                         clocks = <&tegra_car 23>;
  53                 };
  54
  55                 gr2d {
  56                         compatible = "nvidia,tegra20-gr2d";
  57                         reg = <0x54140000 0x00040000>;
  58                         interrupts = <0 72 0x04>;
  59                         clocks = <&tegra_car 21>;
  60                 };
  61
  62                 gr3d {
  63                         compatible = "nvidia,tegra20-gr3d";
  64                         reg = <0x54180000 0x00040000>;
  65                         clocks = <&tegra_car 24>;
  66                 };
  67
  68                 dc@54200000 {
  69                         compatible = "nvidia,tegra20-dc";
  70                         reg = <0x54200000 0x00040000>;
  71                         interrupts = <0 73 0x04>;
  72                         clocks = <&tegra_car 27>, <&tegra_car 121>;
  73                         clock-names = "disp1", "parent";
  74
  75                         rgb {
  76                                 status = "disabled";
  77                         };
  78                 };
  79
  80                 dc@54240000 {
  81                         compatible = "nvidia,tegra20-dc";
  82                         reg = <0x54240000 0x00040000>;
  83                         interrupts = <0 74 0x04>;
  84                         clocks = <&tegra_car 26>, <&tegra_car 121>;
  85                         clock-names = "disp2", "parent";
  86
  87                         rgb {
  88                                 status = "disabled";
  89                         };
  90                 };
  91
  92                 hdmi {
  93                         compatible = "nvidia,tegra20-hdmi";
  94                         reg = <0x54280000 0x00040000>;
  95                         interrupts = <0 75 0x04>;
  96                         clocks = <&tegra_car 51>, <&tegra_car 117>;
  97                         clock-names = "hdmi", "parent";
  98                         status = "disabled";
  99                 };
 100
 101                 tvo {
 102                         compatible = "nvidia,tegra20-tvo";
 103                         reg = <0x542c0000 0x00040000>;
 104                         interrupts = <0 76 0x04>;
 105                         clocks = <&tegra_car 102>;
 106                         status = "disabled";
 107                 };
 108
 109                 dsi {
 110                         compatible = "nvidia,tegra20-dsi";
 111                         reg = <0x54300000 0x00040000>;
 112                         clocks = <&tegra_car 48>;
 113                         status = "disabled";
 114                 };
 115         };
 116
 117         timer@50004600 {
 118                 compatible = "arm,cortex-a9-twd-timer";
 119                 reg = <0x50040600 0x20>;
 120                 interrupts = <1 13 0x304>;
 121         };
 122
 123         intc: interrupt-controller {
 124                 compatible = "arm,cortex-a9-gic";
 125                 reg = <0x50041000 0x1000
 126                        0x50040100 0x0100>;
 127                 interrupt-controller;
 128                 #interrupt-cells = <3>;
 129         };
 130
 131         cache-controller {
 132                 compatible = "arm,pl310-cache";
 133                 reg = <0x50043000 0x1000>;
 134                 arm,data-latency = <5 5 2>;
 135                 arm,tag-latency = <4 4 2>;
 136                 cache-unified;
 137                 cache-level = <2>;
 138         };
 139
 140         timer@60005000 {
 141                 compatible = "nvidia,tegra20-timer";
 142                 reg = <0x60005000 0x60>;
 143                 interrupts = <0 0 0x04
 144                               0 1 0x04
 145                               0 41 0x04
 146                               0 42 0x04>;
 147         };
 148
 149         tegra_car: clock {
 150                 compatible = "nvidia,tegra20-car";
 151                 reg = <0x60006000 0x1000>;
 152                 #clock-cells = <1>;
 153         };
 154
 155         apbdma: dma {
 156                 compatible = "nvidia,tegra20-apbdma";
 157                 reg = <0x6000a000 0x1200>;
 158                 interrupts = <0 104 0x04
 159                               0 105 0x04
 160                               0 106 0x04
 161                               0 107 0x04
 162                               0 108 0x04
 163                               0 109 0x04
 164                               0 110 0x04
 165                               0 111 0x04
 166                               0 112 0x04
 167                               0 113 0x04
 168                               0 114 0x04
 169                               0 115 0x04
 170                               0 116 0x04
 171                               0 117 0x04
 172                               0 118 0x04
 173                               0 119 0x04>;
 174                 clocks = <&tegra_car 34>;
 175         };
 176
 177         ahb {
 178                 compatible = "nvidia,tegra20-ahb";
 179                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 180         };
 181
 182         gpio: gpio {
 183                 compatible = "nvidia,tegra20-gpio";
 184                 reg = <0x6000d000 0x1000>;
 185                 interrupts = <0 32 0x04
 186                               0 33 0x04
 187                               0 34 0x04
 188                               0 35 0x04
 189                               0 55 0x04
 190                               0 87 0x04
 191                               0 89 0x04>;
 192                 #gpio-cells = <2>;
 193                 gpio-controller;
 194                 #interrupt-cells = <2>;
 195                 interrupt-controller;
 196         };
 197
 198         pinmux: pinmux {
 199                 compatible = "nvidia,tegra20-pinmux";
 200                 reg = <0x70000014 0x10   /* Tri-state registers */
 201                        0x70000080 0x20   /* Mux registers */
 202                        0x700000a0 0x14   /* Pull-up/down registers */
 203                        0x70000868 0xa8>; /* Pad control registers */
 204         };
 205
 206         das {
 207                 compatible = "nvidia,tegra20-das";
 208                 reg = <0x70000c00 0x80>;
 209         };
 210
 211         tegra_ac97: ac97 {
 212                 compatible = "nvidia,tegra20-ac97";
 213                 reg = <0x70002000 0x200>;
 214                 interrupts = <0 81 0x04>;
 215                 nvidia,dma-request-selector = <&apbdma 12>;
 216                 clocks = <&tegra_car 3>;
 217                 status = "disabled";
 218         };
 219
 220         tegra_i2s1: i2s@70002800 {
 221                 compatible = "nvidia,tegra20-i2s";
 222                 reg = <0x70002800 0x200>;
 223                 interrupts = <0 13 0x04>;
 224                 nvidia,dma-request-selector = <&apbdma 2>;
 225                 clocks = <&tegra_car 11>;
 226                 status = "disabled";
 227         };
 228
 229         tegra_i2s2: i2s@70002a00 {
 230                 compatible = "nvidia,tegra20-i2s";
 231                 reg = <0x70002a00 0x200>;
 232                 interrupts = <0 3 0x04>;
 233                 nvidia,dma-request-selector = <&apbdma 1>;
 234                 clocks = <&tegra_car 18>;
 235                 status = "disabled";
 236         };
 237
 238         /*
 239          * There are two serial driver i.e. 8250 based simple serial
 240          * driver and APB DMA based serial driver for higher baudrate
 241          * and performace. To enable the 8250 based driver, the compatible
 242          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 243          * driver, the comptible is "nvidia,tegra20-hsuart".
 244          */
 245         uarta: serial@70006000 {
 246                 compatible = "nvidia,tegra20-uart";
 247                 reg = <0x70006000 0x40>;
 248                 reg-shift = <2>;
 249                 interrupts = <0 36 0x04>;
 250                 clock-frequency = <216000000>;
 251                 nvidia,dma-request-selector = <&apbdma 8>;
 252                 clocks = <&tegra_car 6>;
 253                 status = "disabled";
 254         };
 255
 256         uartb: serial@70006040 {
 257                 compatible = "nvidia,tegra20-uart";
 258                 reg = <0x70006040 0x40>;
 259                 reg-shift = <2>;
 260                 interrupts = <0 37 0x04>;
 261                 clock-frequency = <216000000>;
 262                 nvidia,dma-request-selector = <&apbdma 9>;
 263                 clocks = <&tegra_car 96>;
 264                 status = "disabled";
 265         };
 266
 267         uartc: serial@70006200 {
 268                 compatible = "nvidia,tegra20-uart";
 269                 reg = <0x70006200 0x100>;
 270                 reg-shift = <2>;
 271                 interrupts = <0 46 0x04>;
 272                 clock-frequency = <216000000>;
 273                 nvidia,dma-request-selector = <&apbdma 10>;
 274                 clocks = <&tegra_car 55>;
 275                 status = "disabled";
 276         };
 277
 278         uartd: serial@70006300 {
 279                 compatible = "nvidia,tegra20-uart";
 280                 reg = <0x70006300 0x100>;
 281                 reg-shift = <2>;
 282                 interrupts = <0 90 0x04>;
 283                 clock-frequency = <216000000>;
 284                 nvidia,dma-request-selector = <&apbdma 19>;
 285                 clocks = <&tegra_car 65>;
 286                 status = "disabled";
 287         };
 288
 289         uarte: serial@70006400 {
 290                 compatible = "nvidia,tegra20-uart";
 291                 reg = <0x70006400 0x100>;
 292                 reg-shift = <2>;
 293                 interrupts = <0 91 0x04>;
 294                 clock-frequency = <216000000>;
 295                 nvidia,dma-request-selector = <&apbdma 20>;
 296                 clocks = <&tegra_car 66>;
 297                 status = "disabled";
 298         };
 299
 300         pwm: pwm {
 301                 compatible = "nvidia,tegra20-pwm";
 302                 reg = <0x7000a000 0x100>;
 303                 #pwm-cells = <2>;
 304                 clocks = <&tegra_car 17>;
 305         };
 306
 307         rtc {
 308                 compatible = "nvidia,tegra20-rtc";
 309                 reg = <0x7000e000 0x100>;
 310                 interrupts = <0 2 0x04>;
 311         };
 312
 313         i2c@7000c000 {
 314                 compatible = "nvidia,tegra20-i2c";
 315                 reg = <0x7000c000 0x100>;
 316                 interrupts = <0 38 0x04>;
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319                 clocks = <&tegra_car 12>, <&tegra_car 124>;
 320                 clock-names = "div-clk", "fast-clk";
 321                 status = "disabled";
 322         };
 323
 324         spi@7000c380 {
 325                 compatible = "nvidia,tegra20-sflash";
 326                 reg = <0x7000c380 0x80>;
 327                 interrupts = <0 39 0x04>;
 328                 nvidia,dma-request-selector = <&apbdma 11>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 clocks = <&tegra_car 43>;
 332                 status = "disabled";
 333         };
 334
 335         i2c@7000c400 {
 336                 compatible = "nvidia,tegra20-i2c";
 337                 reg = <0x7000c400 0x100>;
 338                 interrupts = <0 84 0x04>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 clocks = <&tegra_car 54>, <&tegra_car 124>;
 342                 clock-names = "div-clk", "fast-clk";
 343                 status = "disabled";
 344         };
 345
 346         i2c@7000c500 {
 347                 compatible = "nvidia,tegra20-i2c";
 348                 reg = <0x7000c500 0x100>;
 349                 interrupts = <0 92 0x04>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 clocks = <&tegra_car 67>, <&tegra_car 124>;
 353                 clock-names = "div-clk", "fast-clk";
 354                 status = "disabled";
 355         };
 356
 357         i2c@7000d000 {
 358                 compatible = "nvidia,tegra20-i2c-dvc";
 359                 reg = <0x7000d000 0x200>;
 360                 interrupts = <0 53 0x04>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 clocks = <&tegra_car 47>, <&tegra_car 124>;
 364                 clock-names = "div-clk", "fast-clk";
 365                 status = "disabled";
 366         };
 367
 368         spi@7000d400 {
 369                 compatible = "nvidia,tegra20-slink";
 370                 reg = <0x7000d400 0x200>;
 371                 interrupts = <0 59 0x04>;
 372                 nvidia,dma-request-selector = <&apbdma 15>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clocks = <&tegra_car 41>;
 376                 status = "disabled";
 377         };
 378
 379         spi@7000d600 {
 380                 compatible = "nvidia,tegra20-slink";
 381                 reg = <0x7000d600 0x200>;
 382                 interrupts = <0 82 0x04>;
 383                 nvidia,dma-request-selector = <&apbdma 16>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 clocks = <&tegra_car 44>;
 387                 status = "disabled";
 388         };
 389
 390         spi@7000d800 {
 391                 compatible = "nvidia,tegra20-slink";
 392                 reg = <0x7000d480 0x200>;
 393                 interrupts = <0 83 0x04>;
 394                 nvidia,dma-request-selector = <&apbdma 17>;
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 clocks = <&tegra_car 46>;
 398                 status = "disabled";
 399         };
 400
 401         spi@7000da00 {
 402                 compatible = "nvidia,tegra20-slink";
 403                 reg = <0x7000da00 0x200>;
 404                 interrupts = <0 93 0x04>;
 405                 nvidia,dma-request-selector = <&apbdma 18>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clocks = <&tegra_car 68>;
 409                 status = "disabled";
 410         };
 411
 412         kbc {
 413                 compatible = "nvidia,tegra20-kbc";
 414                 reg = <0x7000e200 0x100>;
 415                 interrupts = <0 85 0x04>;
 416                 clocks = <&tegra_car 36>;
 417                 status = "disabled";
 418         };
 419
 420         pmc {
 421                 compatible = "nvidia,tegra20-pmc";
 422                 reg = <0x7000e400 0x400>;
 423         };
 424
 425         memory-controller@7000f000 {
 426                 compatible = "nvidia,tegra20-mc";
 427                 reg = <0x7000f000 0x024
 428                        0x7000f03c 0x3c4>;
 429                 interrupts = <0 77 0x04>;
 430         };
 431
 432         gart {
 433                 compatible = "nvidia,tegra20-gart";
 434                 reg = <0x7000f024 0x00000018    /* controller registers */
 435                        0x58000000 0x02000000>;  /* GART aperture */
 436         };
 437
 438         memory-controller@7000f400 {
 439                 compatible = "nvidia,tegra20-emc";
 440                 reg = <0x7000f400 0x200>;
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443         };
 444
 445         phy1: usb-phy@c5000400 {
 446                 compatible = "nvidia,tegra20-usb-phy";
 447                 reg = <0xc5000400 0x3c00>;
 448                 phy_type = "utmi";
 449                 nvidia,has-legacy-mode;
 450                 clocks = <&tegra_car 22>, <&tegra_car 127>;
 451                 clock-names = "phy", "pll_u";
 452         };
 453
 454         phy2: usb-phy@c5004400 {
 455                 compatible = "nvidia,tegra20-usb-phy";
 456                 reg = <0xc5004400 0x3c00>;
 457                 phy_type = "ulpi";
 458                 clocks = <&tegra_car 94>, <&tegra_car 127>;
 459                 clock-names = "phy", "pll_u";
 460         };
 461
 462         phy3: usb-phy@c5008400 {
 463                 compatible = "nvidia,tegra20-usb-phy";
 464                 reg = <0xc5008400 0x3C00>;
 465                 phy_type = "utmi";
 466                 clocks = <&tegra_car 22>, <&tegra_car 127>;
 467                 clock-names = "phy", "pll_u";
 468         };
 469
 470         usb@c5000000 {
 471                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 472                 reg = <0xc5000000 0x4000>;
 473                 interrupts = <0 20 0x04>;
 474                 phy_type = "utmi";
 475                 nvidia,has-legacy-mode;
 476                 clocks = <&tegra_car 22>;
 477                 nvidia,needs-double-reset;
 478                 nvidia,phy = <&phy1>;
 479                 status = "disabled";
 480         };
 481
 482         usb@c5004000 {
 483                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 484                 reg = <0xc5004000 0x4000>;
 485                 interrupts = <0 21 0x04>;
 486                 phy_type = "ulpi";
 487                 clocks = <&tegra_car 58>;
 488                 nvidia,phy = <&phy2>;
 489                 status = "disabled";
 490         };
 491
 492         usb@c5008000 {
 493                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 494                 reg = <0xc5008000 0x4000>;
 495                 interrupts = <0 97 0x04>;
 496                 phy_type = "utmi";
 497                 clocks = <&tegra_car 59>;
 498                 nvidia,phy = <&phy3>;
 499                 status = "disabled";
 500         };
 501
 502         sdhci@c8000000 {
 503                 compatible = "nvidia,tegra20-sdhci";
 504                 reg = <0xc8000000 0x200>;
 505                 interrupts = <0 14 0x04>;
 506                 clocks = <&tegra_car 14>;
 507                 status = "disabled";
 508         };
 509
 510         sdhci@c8000200 {
 511                 compatible = "nvidia,tegra20-sdhci";
 512                 reg = <0xc8000200 0x200>;
 513                 interrupts = <0 15 0x04>;
 514                 clocks = <&tegra_car 9>;
 515                 status = "disabled";
 516         };
 517
 518         sdhci@c8000400 {
 519                 compatible = "nvidia,tegra20-sdhci";
 520                 reg = <0xc8000400 0x200>;
 521                 interrupts = <0 19 0x04>;
 522                 clocks = <&tegra_car 69>;
 523                 status = "disabled";
 524         };
 525
 526         sdhci@c8000600 {
 527                 compatible = "nvidia,tegra20-sdhci";
 528                 reg = <0xc8000600 0x200>;
 529                 interrupts = <0 31 0x04>;
 530                 clocks = <&tegra_car 15>;
 531                 status = "disabled";
 532         };
 533
 534         cpus {
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537
 538                 cpu@0 {
 539                         device_type = "cpu";
 540                         compatible = "arm,cortex-a9";
 541                         reg = <0>;
 542                 };
 543
 544                 cpu@1 {
 545                         device_type = "cpu";
 546                         compatible = "arm,cortex-a9";
 547                         reg = <1>;
 548                 };
 549         };
 550
 551         pmu {
 552                 compatible = "arm,cortex-a9-pmu";
 553                 interrupts = <0 56 0x04
 554                               0 57 0x04>;
 555         };
 556 };