ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
[deliverable/linux.git] / arch / arm / boot / dts / tegra30-colibri.dtsi
1 #include <dt-bindings/input/input.h>
2 #include "tegra30.dtsi"
3
4 /*
5 * Toradex Colibri T30 Device Tree
6 * Compatible for Revisions 1.1B/1.1C/1.1D
7 */
8 / {
9 model = "Toradex Colibri T30";
10 compatible = "toradex,colibri_t30", "nvidia,tegra30";
11
12 memory {
13 reg = <0x80000000 0x40000000>;
14 };
15
16 host1x@50000000 {
17 hdmi@54280000 {
18 vdd-supply = <&sys_3v3_reg>;
19 pll-supply = <&vio_reg>;
20
21 nvidia,hpd-gpio =
22 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
23 nvidia,ddc-i2c-bus = <&hdmiddc>;
24 };
25 };
26
27 pinmux@70000868 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
30
31 state_default: pinmux {
32 /* Colibri BL_ON */
33 pv2 {
34 nvidia,pins = "pv2";
35 nvidia,function = "rsvd4";
36 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <TEGRA_PIN_DISABLE>;
38 };
39
40 /* Colibri Backlight PWM<A> */
41 sdmmc3_dat3_pb4 {
42 nvidia,pins = "sdmmc3_dat3_pb4";
43 nvidia,function = "pwm0";
44 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
45 nvidia,tristate = <TEGRA_PIN_DISABLE>;
46 };
47
48 /* Colibri CAN_INT */
49 kb_row8_ps0 {
50 nvidia,pins = "kb_row8_ps0";
51 nvidia,function = "kbc";
52 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
53 nvidia,tristate = <TEGRA_PIN_DISABLE>;
54 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
55 };
56
57 /*
58 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
59 * todays display need DE, disable LCD_M1
60 */
61 lcd_m1_pw1 {
62 nvidia,pins = "lcd_m1_pw1";
63 nvidia,function = "rsvd3";
64 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
65 nvidia,tristate = <TEGRA_PIN_DISABLE>;
66 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
67 };
68
69 /* Thermal alert, need to be disabled */
70 lcd_dc1_pd2 {
71 nvidia,pins = "lcd_dc1_pd2";
72 nvidia,function = "rsvd3";
73 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
76 };
77
78 /* Colibri MMC */
79 kb_row10_ps2 {
80 nvidia,pins = "kb_row10_ps2";
81 nvidia,function = "sdmmc2";
82 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_DISABLE>;
84 };
85 kb_row11_ps3 {
86 nvidia,pins = "kb_row11_ps3",
87 "kb_row12_ps4",
88 "kb_row13_ps5",
89 "kb_row14_ps6",
90 "kb_row15_ps7";
91 nvidia,function = "sdmmc2";
92 nvidia,pull = <TEGRA_PIN_PULL_UP>;
93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 };
95
96 /* Colibri SSP */
97 ulpi_clk_py0 {
98 nvidia,pins = "ulpi_clk_py0",
99 "ulpi_dir_py1",
100 "ulpi_nxt_py2",
101 "ulpi_stp_py3";
102 nvidia,function = "spi1";
103 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
105 };
106 sdmmc3_dat6_pd3 {
107 nvidia,pins = "sdmmc3_dat6_pd3",
108 "sdmmc3_dat7_pd4";
109 nvidia,function = "spdif";
110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <TEGRA_PIN_ENABLE>;
112 };
113
114 /* Colibri UART_A */
115 ulpi_data0 {
116 nvidia,pins = "ulpi_data0_po1",
117 "ulpi_data1_po2",
118 "ulpi_data2_po3",
119 "ulpi_data3_po4",
120 "ulpi_data4_po5",
121 "ulpi_data5_po6",
122 "ulpi_data6_po7",
123 "ulpi_data7_po0";
124 nvidia,function = "uarta";
125 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
127 };
128
129 /* Colibri UART_B */
130 gmi_a16_pj7 {
131 nvidia,pins = "gmi_a16_pj7",
132 "gmi_a17_pb0",
133 "gmi_a18_pb1",
134 "gmi_a19_pk7";
135 nvidia,function = "uartd";
136 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
138 };
139
140 /* Colibri UART_C */
141 uart2_rxd {
142 nvidia,pins = "uart2_rxd_pc3",
143 "uart2_txd_pc2";
144 nvidia,function = "uartb";
145 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
147 };
148
149 /* eMMC */
150 sdmmc4_clk_pcc4 {
151 nvidia,pins = "sdmmc4_clk_pcc4",
152 "sdmmc4_rst_n_pcc3";
153 nvidia,function = "sdmmc4";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 };
157 sdmmc4_dat0_paa0 {
158 nvidia,pins = "sdmmc4_dat0_paa0",
159 "sdmmc4_dat1_paa1",
160 "sdmmc4_dat2_paa2",
161 "sdmmc4_dat3_paa3",
162 "sdmmc4_dat4_paa4",
163 "sdmmc4_dat5_paa5",
164 "sdmmc4_dat6_paa6",
165 "sdmmc4_dat7_paa7";
166 nvidia,function = "sdmmc4";
167 nvidia,pull = <TEGRA_PIN_PULL_UP>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 };
170 };
171 };
172
173 hdmiddc: i2c@7000c700 {
174 clock-frequency = <100000>;
175 };
176
177 /*
178 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
179 * touch screen controller
180 */
181 i2c@7000d000 {
182 status = "okay";
183 clock-frequency = <100000>;
184
185 pmic: tps65911@2d {
186 compatible = "ti,tps65911";
187 reg = <0x2d>;
188
189 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
190 #interrupt-cells = <2>;
191 interrupt-controller;
192
193 ti,system-power-controller;
194
195 #gpio-cells = <2>;
196 gpio-controller;
197
198 vcc1-supply = <&sys_3v3_reg>;
199 vcc2-supply = <&sys_3v3_reg>;
200 vcc3-supply = <&vio_reg>;
201 vcc4-supply = <&sys_3v3_reg>;
202 vcc5-supply = <&sys_3v3_reg>;
203 vcc6-supply = <&vio_reg>;
204 vcc7-supply = <&charge_pump_5v0_reg>;
205 vccio-supply = <&sys_3v3_reg>;
206
207 regulators {
208 /* SW1: +V1.35_VDDIO_DDR */
209 vdd1_reg: vdd1 {
210 regulator-name = "vddio_ddr_1v35";
211 regulator-min-microvolt = <1350000>;
212 regulator-max-microvolt = <1350000>;
213 regulator-always-on;
214 };
215
216 /* SW2: unused */
217
218 /* SW CTRL: +V1.0_VDD_CPU */
219 vddctrl_reg: vddctrl {
220 regulator-name = "vdd_cpu,vdd_sys";
221 regulator-min-microvolt = <1150000>;
222 regulator-max-microvolt = <1150000>;
223 regulator-always-on;
224 };
225
226 /* SWIO: +V1.8 */
227 vio_reg: vio {
228 regulator-name = "vdd_1v8_gen";
229 regulator-min-microvolt = <1800000>;
230 regulator-max-microvolt = <1800000>;
231 regulator-always-on;
232 };
233
234 /* LDO1: unused */
235
236 /*
237 * EN_+V3.3 switching via FET:
238 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
239 * see also v3_3 fixed supply
240 */
241 ldo2_reg: ldo2 {
242 regulator-name = "en_3v3";
243 regulator-min-microvolt = <3300000>;
244 regulator-max-microvolt = <3300000>;
245 regulator-always-on;
246 };
247
248 /* LDO3: unused */
249
250 /* +V1.2_VDD_RTC */
251 ldo4_reg: ldo4 {
252 regulator-name = "vdd_rtc";
253 regulator-min-microvolt = <1200000>;
254 regulator-max-microvolt = <1200000>;
255 regulator-always-on;
256 };
257
258 /*
259 * +V2.8_AVDD_VDAC:
260 * only required for analog RGB
261 */
262 ldo5_reg: ldo5 {
263 regulator-name = "avdd_vdac";
264 regulator-min-microvolt = <2800000>;
265 regulator-max-microvolt = <2800000>;
266 regulator-always-on;
267 };
268
269 /*
270 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
271 * but LDO6 can't set voltage in 50mV
272 * granularity
273 */
274 ldo6_reg: ldo6 {
275 regulator-name = "avdd_plle";
276 regulator-min-microvolt = <1100000>;
277 regulator-max-microvolt = <1100000>;
278 };
279
280 /* +V1.2_AVDD_PLL */
281 ldo7_reg: ldo7 {
282 regulator-name = "avdd_pll";
283 regulator-min-microvolt = <1200000>;
284 regulator-max-microvolt = <1200000>;
285 regulator-always-on;
286 };
287
288 /* +V1.0_VDD_DDR_HS */
289 ldo8_reg: ldo8 {
290 regulator-name = "vdd_ddr_hs";
291 regulator-min-microvolt = <1000000>;
292 regulator-max-microvolt = <1000000>;
293 regulator-always-on;
294 };
295 };
296 };
297
298 /*
299 * LM95245 temperature sensor
300 * Note: OVERT_N directly connected to PMIC PWRDN
301 */
302 temp-sensor@4c {
303 compatible = "national,lm95245";
304 reg = <0x4c>;
305 };
306
307 /* SW: +V1.2_VDD_CORE */
308 tps62362@60 {
309 compatible = "ti,tps62362";
310 reg = <0x60>;
311
312 regulator-name = "tps62362-vout";
313 regulator-min-microvolt = <900000>;
314 regulator-max-microvolt = <1400000>;
315 regulator-boot-on;
316 regulator-always-on;
317 ti,vsel0-state-low;
318 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
319 ti,vsel1-state-low;
320 };
321 };
322
323 pmc@7000e400 {
324 nvidia,invert-interrupt;
325 nvidia,suspend-mode = <1>;
326 nvidia,cpu-pwr-good-time = <5000>;
327 nvidia,cpu-pwr-off-time = <5000>;
328 nvidia,core-pwr-good-time = <3845 3845>;
329 nvidia,core-pwr-off-time = <0>;
330 nvidia,core-power-req-active-high;
331 nvidia,sys-clock-req-active-high;
332 };
333
334 emmc: sdhci@78000600 {
335 status = "okay";
336 bus-width = <8>;
337 non-removable;
338 };
339
340 /* EHCI instance 1: USB2_DP/N -> AX88772B */
341 usb@7d004000 {
342 status = "okay";
343 };
344
345 usb-phy@7d004000 {
346 status = "okay";
347 nvidia,is-wired = <1>;
348 };
349
350 clocks {
351 compatible = "simple-bus";
352 #address-cells = <1>;
353 #size-cells = <0>;
354
355 clk32k_in: clk@0 {
356 compatible = "fixed-clock";
357 reg=<0>;
358 #clock-cells = <0>;
359 clock-frequency = <32768>;
360 };
361 };
362
363 regulators {
364 compatible = "simple-bus";
365 #address-cells = <1>;
366 #size-cells = <0>;
367
368 sys_3v3_reg: regulator@100 {
369 compatible = "regulator-fixed";
370 reg = <100>;
371 regulator-name = "3v3";
372 regulator-min-microvolt = <3300000>;
373 regulator-max-microvolt = <3300000>;
374 regulator-always-on;
375 };
376
377 charge_pump_5v0_reg: regulator@101 {
378 compatible = "regulator-fixed";
379 reg = <101>;
380 regulator-name = "5v0";
381 regulator-min-microvolt = <5000000>;
382 regulator-max-microvolt = <5000000>;
383 regulator-always-on;
384 };
385 };
386 };
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