arch/arm/boot/dts/tegra30.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra30";
   5         interrupt-parent = <&intc>;
   6
   7         host1x {
   8                 compatible = "nvidia,tegra30-host1x", "simple-bus";
   9                 reg = <0x50000000 0x00024000>;
  10                 interrupts = <0 65 0x04   /* mpcore syncpt */
  11                               0 67 0x04>; /* mpcore general */
  12
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15
  16                 ranges = <0x54000000 0x54000000 0x04000000>;
  17
  18                 mpe {
  19                         compatible = "nvidia,tegra30-mpe";
  20                         reg = <0x54040000 0x00040000>;
  21                         interrupts = <0 68 0x04>;
  22                 };
  23
  24                 vi {
  25                         compatible = "nvidia,tegra30-vi";
  26                         reg = <0x54080000 0x00040000>;
  27                         interrupts = <0 69 0x04>;
  28                 };
  29
  30                 epp {
  31                         compatible = "nvidia,tegra30-epp";
  32                         reg = <0x540c0000 0x00040000>;
  33                         interrupts = <0 70 0x04>;
  34                 };
  35
  36                 isp {
  37                         compatible = "nvidia,tegra30-isp";
  38                         reg = <0x54100000 0x00040000>;
  39                         interrupts = <0 71 0x04>;
  40                 };
  41
  42                 gr2d {
  43                         compatible = "nvidia,tegra30-gr2d";
  44                         reg = <0x54140000 0x00040000>;
  45                         interrupts = <0 72 0x04>;
  46                 };
  47
  48                 gr3d {
  49                         compatible = "nvidia,tegra30-gr3d";
  50                         reg = <0x54180000 0x00040000>;
  51                 };
  52
  53                 dc@54200000 {
  54                         compatible = "nvidia,tegra30-dc";
  55                         reg = <0x54200000 0x00040000>;
  56                         interrupts = <0 73 0x04>;
  57
  58                         rgb {
  59                                 status = "disabled";
  60                         };
  61                 };
  62
  63                 dc@54240000 {
  64                         compatible = "nvidia,tegra30-dc";
  65                         reg = <0x54240000 0x00040000>;
  66                         interrupts = <0 74 0x04>;
  67
  68                         rgb {
  69                                 status = "disabled";
  70                         };
  71                 };
  72
  73                 hdmi {
  74                         compatible = "nvidia,tegra30-hdmi";
  75                         reg = <0x54280000 0x00040000>;
  76                         interrupts = <0 75 0x04>;
  77                         status = "disabled";
  78                 };
  79
  80                 tvo {
  81                         compatible = "nvidia,tegra30-tvo";
  82                         reg = <0x542c0000 0x00040000>;
  83                         interrupts = <0 76 0x04>;
  84                         status = "disabled";
  85                 };
  86
  87                 dsi {
  88                         compatible = "nvidia,tegra30-dsi";
  89                         reg = <0x54300000 0x00040000>;
  90                         status = "disabled";
  91                 };
  92         };
  93
  94         cache-controller@50043000 {
  95                 compatible = "arm,pl310-cache";
  96                 reg = <0x50043000 0x1000>;
  97                 arm,data-latency = <6 6 2>;
  98                 arm,tag-latency = <5 5 2>;
  99                 cache-unified;
 100                 cache-level = <2>;
 101         };
 102
 103         intc: interrupt-controller {
 104                 compatible = "arm,cortex-a9-gic";
 105                 reg = <0x50041000 0x1000
 106                        0x50040100 0x0100>;
 107                 interrupt-controller;
 108                 #interrupt-cells = <3>;
 109         };
 110
 111         timer@60005000 {
 112                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 113                 reg = <0x60005000 0x400>;
 114                 interrupts = <0 0 0x04
 115                               0 1 0x04
 116                               0 41 0x04
 117                               0 42 0x04
 118                               0 121 0x04
 119                               0 122 0x04>;
 120         };
 121
 122         apbdma: dma {
 123                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 124                 reg = <0x6000a000 0x1400>;
 125                 interrupts = <0 104 0x04
 126                               0 105 0x04
 127                               0 106 0x04
 128                               0 107 0x04
 129                               0 108 0x04
 130                               0 109 0x04
 131                               0 110 0x04
 132                               0 111 0x04
 133                               0 112 0x04
 134                               0 113 0x04
 135                               0 114 0x04
 136                               0 115 0x04
 137                               0 116 0x04
 138                               0 117 0x04
 139                               0 118 0x04
 140                               0 119 0x04
 141                               0 128 0x04
 142                               0 129 0x04
 143                               0 130 0x04
 144                               0 131 0x04
 145                               0 132 0x04
 146                               0 133 0x04
 147                               0 134 0x04
 148                               0 135 0x04
 149                               0 136 0x04
 150                               0 137 0x04
 151                               0 138 0x04
 152                               0 139 0x04
 153                               0 140 0x04
 154                               0 141 0x04
 155                               0 142 0x04
 156                               0 143 0x04>;
 157         };
 158
 159         ahb: ahb {
 160                 compatible = "nvidia,tegra30-ahb";
 161                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
 162         };
 163
 164         gpio: gpio {
 165                 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
 166                 reg = <0x6000d000 0x1000>;
 167                 interrupts = <0 32 0x04
 168                               0 33 0x04
 169                               0 34 0x04
 170                               0 35 0x04
 171                               0 55 0x04
 172                               0 87 0x04
 173                               0 89 0x04
 174                               0 125 0x04>;
 175                 #gpio-cells = <2>;
 176                 gpio-controller;
 177                 #interrupt-cells = <2>;
 178                 interrupt-controller;
 179         };
 180
 181         pinmux: pinmux {
 182                 compatible = "nvidia,tegra30-pinmux";
 183                 reg = <0x70000868 0xd0    /* Pad control registers */
 184                        0x70003000 0x3e0>; /* Mux registers */
 185         };
 186
 187         serial@70006000 {
 188                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 189                 reg = <0x70006000 0x40>;
 190                 reg-shift = <2>;
 191                 interrupts = <0 36 0x04>;
 192                 status = "disabled";
 193         };
 194
 195         serial@70006040 {
 196                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 197                 reg = <0x70006040 0x40>;
 198                 reg-shift = <2>;
 199                 interrupts = <0 37 0x04>;
 200                 status = "disabled";
 201         };
 202
 203         serial@70006200 {
 204                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 205                 reg = <0x70006200 0x100>;
 206                 reg-shift = <2>;
 207                 interrupts = <0 46 0x04>;
 208                 status = "disabled";
 209         };
 210
 211         serial@70006300 {
 212                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 213                 reg = <0x70006300 0x100>;
 214                 reg-shift = <2>;
 215                 interrupts = <0 90 0x04>;
 216                 status = "disabled";
 217         };
 218
 219         serial@70006400 {
 220                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 221                 reg = <0x70006400 0x100>;
 222                 reg-shift = <2>;
 223                 interrupts = <0 91 0x04>;
 224                 status = "disabled";
 225         };
 226
 227         pwm: pwm {
 228                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 229                 reg = <0x7000a000 0x100>;
 230                 #pwm-cells = <2>;
 231         };
 232
 233         i2c@7000c000 {
 234                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 235                 reg = <0x7000c000 0x100>;
 236                 interrupts = <0 38 0x04>;
 237                 #address-cells = <1>;
 238                 #size-cells = <0>;
 239                 status = "disabled";
 240         };
 241
 242         i2c@7000c400 {
 243                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 244                 reg = <0x7000c400 0x100>;
 245                 interrupts = <0 84 0x04>;
 246                 #address-cells = <1>;
 247                 #size-cells = <0>;
 248                 status = "disabled";
 249         };
 250
 251         i2c@7000c500 {
 252                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 253                 reg = <0x7000c500 0x100>;
 254                 interrupts = <0 92 0x04>;
 255                 #address-cells = <1>;
 256                 #size-cells = <0>;
 257                 status = "disabled";
 258         };
 259
 260         i2c@7000c700 {
 261                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 262                 reg = <0x7000c700 0x100>;
 263                 interrupts = <0 120 0x04>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 status = "disabled";
 267         };
 268
 269         i2c@7000d000 {
 270                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 271                 reg = <0x7000d000 0x100>;
 272                 interrupts = <0 53 0x04>;
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 status = "disabled";
 276         };
 277
 278         spi@7000d400 {
 279                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 280                 reg = <0x7000d400 0x200>;
 281                 interrupts = <0 59 0x04>;
 282                 nvidia,dma-request-selector = <&apbdma 15>;
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 status = "disabled";
 286         };
 287
 288         spi@7000d600 {
 289                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 290                 reg = <0x7000d600 0x200>;
 291                 interrupts = <0 82 0x04>;
 292                 nvidia,dma-request-selector = <&apbdma 16>;
 293                 #address-cells = <1>;
 294                 #size-cells = <0>;
 295                 status = "disabled";
 296         };
 297
 298         spi@7000d800 {
 299                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 300                 reg = <0x7000d480 0x200>;
 301                 interrupts = <0 83 0x04>;
 302                 nvidia,dma-request-selector = <&apbdma 17>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 status = "disabled";
 306         };
 307
 308         spi@7000da00 {
 309                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 310                 reg = <0x7000da00 0x200>;
 311                 interrupts = <0 93 0x04>;
 312                 nvidia,dma-request-selector = <&apbdma 18>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 status = "disabled";
 316         };
 317
 318         spi@7000dc00 {
 319                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 320                 reg = <0x7000dc00 0x200>;
 321                 interrupts = <0 94 0x04>;
 322                 nvidia,dma-request-selector = <&apbdma 27>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         spi@7000de00 {
 329                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 330                 reg = <0x7000de00 0x200>;
 331                 interrupts = <0 79 0x04>;
 332                 nvidia,dma-request-selector = <&apbdma 28>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 status = "disabled";
 336         };
 337
 338         pmc {
 339                 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
 340                 reg = <0x7000e400 0x400>;
 341         };
 342
 343         memory-controller {
 344                 compatible = "nvidia,tegra30-mc";
 345                 reg = <0x7000f000 0x010
 346                        0x7000f03c 0x1b4
 347                        0x7000f200 0x028
 348                        0x7000f284 0x17c>;
 349                 interrupts = <0 77 0x04>;
 350         };
 351
 352         smmu {
 353                 compatible = "nvidia,tegra30-smmu";
 354                 reg = <0x7000f010 0x02c
 355                        0x7000f1f0 0x010
 356                        0x7000f228 0x05c>;
 357                 nvidia,#asids = <4>;            /* # of ASIDs */
 358                 dma-window = <0 0x40000000>;    /* IOVA start & length */
 359                 nvidia,ahb = <&ahb>;
 360         };
 361
 362         ahub {
 363                 compatible = "nvidia,tegra30-ahub";
 364                 reg = <0x70080000 0x200
 365                        0x70080200 0x100>;
 366                 interrupts = <0 103 0x04>;
 367                 nvidia,dma-request-selector = <&apbdma 1>;
 368
 369                 ranges;
 370                 #address-cells = <1>;
 371                 #size-cells = <1>;
 372
 373                 tegra_i2s0: i2s@70080300 {
 374                         compatible = "nvidia,tegra30-i2s";
 375                         reg = <0x70080300 0x100>;
 376                         nvidia,ahub-cif-ids = <4 4>;
 377                         status = "disabled";
 378                 };
 379
 380                 tegra_i2s1: i2s@70080400 {
 381                         compatible = "nvidia,tegra30-i2s";
 382                         reg = <0x70080400 0x100>;
 383                         nvidia,ahub-cif-ids = <5 5>;
 384                         status = "disabled";
 385                 };
 386
 387                 tegra_i2s2: i2s@70080500 {
 388                         compatible = "nvidia,tegra30-i2s";
 389                         reg = <0x70080500 0x100>;
 390                         nvidia,ahub-cif-ids = <6 6>;
 391                         status = "disabled";
 392                 };
 393
 394                 tegra_i2s3: i2s@70080600 {
 395                         compatible = "nvidia,tegra30-i2s";
 396                         reg = <0x70080600 0x100>;
 397                         nvidia,ahub-cif-ids = <7 7>;
 398                         status = "disabled";
 399                 };
 400
 401                 tegra_i2s4: i2s@70080700 {
 402                         compatible = "nvidia,tegra30-i2s";
 403                         reg = <0x70080700 0x100>;
 404                         nvidia,ahub-cif-ids = <8 8>;
 405                         status = "disabled";
 406                 };
 407         };
 408
 409         sdhci@78000000 {
 410                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 411                 reg = <0x78000000 0x200>;
 412                 interrupts = <0 14 0x04>;
 413                 status = "disabled";
 414         };
 415
 416         sdhci@78000200 {
 417                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 418                 reg = <0x78000200 0x200>;
 419                 interrupts = <0 15 0x04>;
 420                 status = "disabled";
 421         };
 422
 423         sdhci@78000400 {
 424                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 425                 reg = <0x78000400 0x200>;
 426                 interrupts = <0 19 0x04>;
 427                 status = "disabled";
 428         };
 429
 430         sdhci@78000600 {
 431                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 432                 reg = <0x78000600 0x200>;
 433                 interrupts = <0 31 0x04>;
 434                 status = "disabled";
 435         };
 436
 437         pmu {
 438                 compatible = "arm,cortex-a9-pmu";
 439                 interrupts = <0 144 0x04
 440                               0 145 0x04
 441                               0 146 0x04
 442                               0 147 0x04>;
 443         };
 444 };