arch/arm/boot/dts/tegra30.dtsi

   1 #include <dt-bindings/clock/tegra30-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         compatible = "nvidia,tegra30";
   9         interrupt-parent = <&intc>;
  10
  11         aliases {
  12                 serial0 = &uarta;
  13                 serial1 = &uartb;
  14                 serial2 = &uartc;
  15                 serial3 = &uartd;
  16                 serial4 = &uarte;
  17         };
  18
  19         host1x {
  20                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  21                 reg = <0x50000000 0x00024000>;
  22                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  23                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  24                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
  25
  26                 #address-cells = <1>;
  27                 #size-cells = <1>;
  28
  29                 ranges = <0x54000000 0x54000000 0x04000000>;
  30
  31                 mpe {
  32                         compatible = "nvidia,tegra30-mpe";
  33                         reg = <0x54040000 0x00040000>;
  34                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  35                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
  36                 };
  37
  38                 vi {
  39                         compatible = "nvidia,tegra30-vi";
  40                         reg = <0x54080000 0x00040000>;
  41                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  42                         clocks = <&tegra_car TEGRA30_CLK_VI>;
  43                 };
  44
  45                 epp {
  46                         compatible = "nvidia,tegra30-epp";
  47                         reg = <0x540c0000 0x00040000>;
  48                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  49                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
  50                 };
  51
  52                 isp {
  53                         compatible = "nvidia,tegra30-isp";
  54                         reg = <0x54100000 0x00040000>;
  55                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  56                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
  57                 };
  58
  59                 gr2d {
  60                         compatible = "nvidia,tegra30-gr2d";
  61                         reg = <0x54140000 0x00040000>;
  62                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  63                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
  64                 };
  65
  66                 gr3d {
  67                         compatible = "nvidia,tegra30-gr3d";
  68                         reg = <0x54180000 0x00040000>;
  69                         clocks = <&tegra_car 24 &tegra_car 98>;
  70                         clock-names = "3d", "3d2";
  71                 };
  72
  73                 dc@54200000 {
  74                         compatible = "nvidia,tegra30-dc";
  75                         reg = <0x54200000 0x00040000>;
  76                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  77                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
  78                                  <&tegra_car TEGRA30_CLK_PLL_P>;
  79                         clock-names = "disp1", "parent";
  80
  81                         rgb {
  82                                 status = "disabled";
  83                         };
  84                 };
  85
  86                 dc@54240000 {
  87                         compatible = "nvidia,tegra30-dc";
  88                         reg = <0x54240000 0x00040000>;
  89                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  90                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
  91                                  <&tegra_car TEGRA30_CLK_PLL_P>;
  92                         clock-names = "disp2", "parent";
  93
  94                         rgb {
  95                                 status = "disabled";
  96                         };
  97                 };
  98
  99                 hdmi {
 100                         compatible = "nvidia,tegra30-hdmi";
 101                         reg = <0x54280000 0x00040000>;
 102                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 103                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 104                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 105                         clock-names = "hdmi", "parent";
 106                         status = "disabled";
 107                 };
 108
 109                 tvo {
 110                         compatible = "nvidia,tegra30-tvo";
 111                         reg = <0x542c0000 0x00040000>;
 112                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 113                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 114                         status = "disabled";
 115                 };
 116
 117                 dsi {
 118                         compatible = "nvidia,tegra30-dsi";
 119                         reg = <0x54300000 0x00040000>;
 120                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 121                         status = "disabled";
 122                 };
 123         };
 124
 125         timer@50004600 {
 126                 compatible = "arm,cortex-a9-twd-timer";
 127                 reg = <0x50040600 0x20>;
 128                 interrupts = <GIC_PPI 13
 129                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 130                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 131         };
 132
 133         intc: interrupt-controller {
 134                 compatible = "arm,cortex-a9-gic";
 135                 reg = <0x50041000 0x1000
 136                        0x50040100 0x0100>;
 137                 interrupt-controller;
 138                 #interrupt-cells = <3>;
 139         };
 140
 141         cache-controller {
 142                 compatible = "arm,pl310-cache";
 143                 reg = <0x50043000 0x1000>;
 144                 arm,data-latency = <6 6 2>;
 145                 arm,tag-latency = <5 5 2>;
 146                 cache-unified;
 147                 cache-level = <2>;
 148         };
 149
 150         timer@60005000 {
 151                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 152                 reg = <0x60005000 0x400>;
 153                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 157                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 158                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 160         };
 161
 162         tegra_car: clock {
 163                 compatible = "nvidia,tegra30-car";
 164                 reg = <0x60006000 0x1000>;
 165                 #clock-cells = <1>;
 166         };
 167
 168         apbdma: dma {
 169                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 170                 reg = <0x6000a000 0x1400>;
 171                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 181                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 202                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 204         };
 205
 206         ahb: ahb {
 207                 compatible = "nvidia,tegra30-ahb";
 208                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
 209         };
 210
 211         gpio: gpio {
 212                 compatible = "nvidia,tegra30-gpio";
 213                 reg = <0x6000d000 0x1000>;
 214                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 222                 #gpio-cells = <2>;
 223                 gpio-controller;
 224                 #interrupt-cells = <2>;
 225                 interrupt-controller;
 226         };
 227
 228         pinmux: pinmux {
 229                 compatible = "nvidia,tegra30-pinmux";
 230                 reg = <0x70000868 0xd4    /* Pad control registers */
 231                        0x70003000 0x3e4>; /* Mux registers */
 232         };
 233
 234         /*
 235          * There are two serial driver i.e. 8250 based simple serial
 236          * driver and APB DMA based serial driver for higher baudrate
 237          * and performace. To enable the 8250 based driver, the compatible
 238          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 239          * the APB DMA based serial driver, the comptible is
 240          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 241          */
 242         uarta: serial@70006000 {
 243                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 244                 reg = <0x70006000 0x40>;
 245                 reg-shift = <2>;
 246                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 247                 nvidia,dma-request-selector = <&apbdma 8>;
 248                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 249                 status = "disabled";
 250         };
 251
 252         uartb: serial@70006040 {
 253                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 254                 reg = <0x70006040 0x40>;
 255                 reg-shift = <2>;
 256                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 257                 nvidia,dma-request-selector = <&apbdma 9>;
 258                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 259                 status = "disabled";
 260         };
 261
 262         uartc: serial@70006200 {
 263                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 264                 reg = <0x70006200 0x100>;
 265                 reg-shift = <2>;
 266                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 267                 nvidia,dma-request-selector = <&apbdma 10>;
 268                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 269                 status = "disabled";
 270         };
 271
 272         uartd: serial@70006300 {
 273                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 274                 reg = <0x70006300 0x100>;
 275                 reg-shift = <2>;
 276                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 277                 nvidia,dma-request-selector = <&apbdma 19>;
 278                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 279                 status = "disabled";
 280         };
 281
 282         uarte: serial@70006400 {
 283                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 284                 reg = <0x70006400 0x100>;
 285                 reg-shift = <2>;
 286                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 287                 nvidia,dma-request-selector = <&apbdma 20>;
 288                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 289                 status = "disabled";
 290         };
 291
 292         pwm: pwm {
 293                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 294                 reg = <0x7000a000 0x100>;
 295                 #pwm-cells = <2>;
 296                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 297                 status = "disabled";
 298         };
 299
 300         rtc {
 301                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 302                 reg = <0x7000e000 0x100>;
 303                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 305         };
 306
 307         i2c@7000c000 {
 308                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 309                 reg = <0x7000c000 0x100>;
 310                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 311                 #address-cells = <1>;
 312                 #size-cells = <0>;
 313                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 314                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 315                 clock-names = "div-clk", "fast-clk";
 316                 status = "disabled";
 317         };
 318
 319         i2c@7000c400 {
 320                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 321                 reg = <0x7000c400 0x100>;
 322                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 326                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 327                 clock-names = "div-clk", "fast-clk";
 328                 status = "disabled";
 329         };
 330
 331         i2c@7000c500 {
 332                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 333                 reg = <0x7000c500 0x100>;
 334                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 338                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 339                 clock-names = "div-clk", "fast-clk";
 340                 status = "disabled";
 341         };
 342
 343         i2c@7000c700 {
 344                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 345                 reg = <0x7000c700 0x100>;
 346                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 350                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 351                 clock-names = "div-clk", "fast-clk";
 352                 status = "disabled";
 353         };
 354
 355         i2c@7000d000 {
 356                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 357                 reg = <0x7000d000 0x100>;
 358                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 362                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 363                 clock-names = "div-clk", "fast-clk";
 364                 status = "disabled";
 365         };
 366
 367         spi@7000d400 {
 368                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 369                 reg = <0x7000d400 0x200>;
 370                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 371                 nvidia,dma-request-selector = <&apbdma 15>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 375                 status = "disabled";
 376         };
 377
 378         spi@7000d600 {
 379                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 380                 reg = <0x7000d600 0x200>;
 381                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 382                 nvidia,dma-request-selector = <&apbdma 16>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 386                 status = "disabled";
 387         };
 388
 389         spi@7000d800 {
 390                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 391                 reg = <0x7000d800 0x200>;
 392                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 393                 nvidia,dma-request-selector = <&apbdma 17>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 397                 status = "disabled";
 398         };
 399
 400         spi@7000da00 {
 401                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 402                 reg = <0x7000da00 0x200>;
 403                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 404                 nvidia,dma-request-selector = <&apbdma 18>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 408                 status = "disabled";
 409         };
 410
 411         spi@7000dc00 {
 412                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 413                 reg = <0x7000dc00 0x200>;
 414                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 415                 nvidia,dma-request-selector = <&apbdma 27>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 419                 status = "disabled";
 420         };
 421
 422         spi@7000de00 {
 423                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 424                 reg = <0x7000de00 0x200>;
 425                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 426                 nvidia,dma-request-selector = <&apbdma 28>;
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 430                 status = "disabled";
 431         };
 432
 433         kbc {
 434                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 435                 reg = <0x7000e200 0x100>;
 436                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 437                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 438                 status = "disabled";
 439         };
 440
 441         pmc {
 442                 compatible = "nvidia,tegra30-pmc";
 443                 reg = <0x7000e400 0x400>;
 444                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 445                 clock-names = "pclk", "clk32k_in";
 446         };
 447
 448         memory-controller {
 449                 compatible = "nvidia,tegra30-mc";
 450                 reg = <0x7000f000 0x010
 451                        0x7000f03c 0x1b4
 452                        0x7000f200 0x028
 453                        0x7000f284 0x17c>;
 454                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 455         };
 456
 457         iommu {
 458                 compatible = "nvidia,tegra30-smmu";
 459                 reg = <0x7000f010 0x02c
 460                        0x7000f1f0 0x010
 461                        0x7000f228 0x05c>;
 462                 nvidia,#asids = <4>;            /* # of ASIDs */
 463                 dma-window = <0 0x40000000>;    /* IOVA start & length */
 464                 nvidia,ahb = <&ahb>;
 465         };
 466
 467         ahub {
 468                 compatible = "nvidia,tegra30-ahub";
 469                 reg = <0x70080000 0x200
 470                        0x70080200 0x100>;
 471                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 472                 nvidia,dma-request-selector = <&apbdma 1>;
 473                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 474                          <&tegra_car TEGRA30_CLK_APBIF>,
 475                          <&tegra_car TEGRA30_CLK_I2S0>,
 476                          <&tegra_car TEGRA30_CLK_I2S1>,
 477                          <&tegra_car TEGRA30_CLK_I2S2>,
 478                          <&tegra_car TEGRA30_CLK_I2S3>,
 479                          <&tegra_car TEGRA30_CLK_I2S4>,
 480                          <&tegra_car TEGRA30_CLK_DAM0>,
 481                          <&tegra_car TEGRA30_CLK_DAM1>,
 482                          <&tegra_car TEGRA30_CLK_DAM2>,
 483                          <&tegra_car TEGRA30_CLK_SPDIF_IN>;
 484                 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 485                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 486                               "spdif_in";
 487                 ranges;
 488                 #address-cells = <1>;
 489                 #size-cells = <1>;
 490
 491                 tegra_i2s0: i2s@70080300 {
 492                         compatible = "nvidia,tegra30-i2s";
 493                         reg = <0x70080300 0x100>;
 494                         nvidia,ahub-cif-ids = <4 4>;
 495                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 496                         status = "disabled";
 497                 };
 498
 499                 tegra_i2s1: i2s@70080400 {
 500                         compatible = "nvidia,tegra30-i2s";
 501                         reg = <0x70080400 0x100>;
 502                         nvidia,ahub-cif-ids = <5 5>;
 503                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 504                         status = "disabled";
 505                 };
 506
 507                 tegra_i2s2: i2s@70080500 {
 508                         compatible = "nvidia,tegra30-i2s";
 509                         reg = <0x70080500 0x100>;
 510                         nvidia,ahub-cif-ids = <6 6>;
 511                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 512                         status = "disabled";
 513                 };
 514
 515                 tegra_i2s3: i2s@70080600 {
 516                         compatible = "nvidia,tegra30-i2s";
 517                         reg = <0x70080600 0x100>;
 518                         nvidia,ahub-cif-ids = <7 7>;
 519                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 520                         status = "disabled";
 521                 };
 522
 523                 tegra_i2s4: i2s@70080700 {
 524                         compatible = "nvidia,tegra30-i2s";
 525                         reg = <0x70080700 0x100>;
 526                         nvidia,ahub-cif-ids = <8 8>;
 527                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 528                         status = "disabled";
 529                 };
 530         };
 531
 532         sdhci@78000000 {
 533                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 534                 reg = <0x78000000 0x200>;
 535                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 536                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 537                 status = "disabled";
 538         };
 539
 540         sdhci@78000200 {
 541                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 542                 reg = <0x78000200 0x200>;
 543                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 544                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 545                 status = "disabled";
 546         };
 547
 548         sdhci@78000400 {
 549                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 550                 reg = <0x78000400 0x200>;
 551                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 552                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 553                 status = "disabled";
 554         };
 555
 556         sdhci@78000600 {
 557                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 558                 reg = <0x78000600 0x200>;
 559                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 560                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 561                 status = "disabled";
 562         };
 563
 564         cpus {
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567
 568                 cpu@0 {
 569                         device_type = "cpu";
 570                         compatible = "arm,cortex-a9";
 571                         reg = <0>;
 572                 };
 573
 574                 cpu@1 {
 575                         device_type = "cpu";
 576                         compatible = "arm,cortex-a9";
 577                         reg = <1>;
 578                 };
 579
 580                 cpu@2 {
 581                         device_type = "cpu";
 582                         compatible = "arm,cortex-a9";
 583                         reg = <2>;
 584                 };
 585
 586                 cpu@3 {
 587                         device_type = "cpu";
 588                         compatible = "arm,cortex-a9";
 589                         reg = <3>;
 590                 };
 591         };
 592
 593         pmu {
 594                 compatible = "arm,cortex-a9-pmu";
 595                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 596                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 597                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 598                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 599         };
 600 };