2 /include/ "skeleton.dtsi"
5 model = "ARM Versatile AB";
6 compatible = "arm,versatile-ab";
9 interrupt-parent = <&vic>;
23 reg = <0x0 0x08000000>;
26 xtal24mhz: xtal24mhz@24M {
28 compatible = "fixed-clock";
29 clock-frequency = <24000000>;
32 core-module@10000000 {
33 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
34 reg = <0x10000000 0x200>;
37 compatible = "register-bit-led";
40 label = "versatile:0";
41 linux,default-trigger = "heartbeat";
45 compatible = "register-bit-led";
48 label = "versatile:1";
49 linux,default-trigger = "mmc0";
50 default-state = "off";
53 compatible = "register-bit-led";
56 label = "versatile:2";
57 linux,default-trigger = "cpu0";
58 default-state = "off";
61 compatible = "register-bit-led";
64 label = "versatile:3";
65 default-state = "off";
68 compatible = "register-bit-led";
71 label = "versatile:4";
72 default-state = "off";
75 compatible = "register-bit-led";
78 label = "versatile:5";
79 default-state = "off";
82 compatible = "register-bit-led";
85 label = "versatile:6";
86 default-state = "off";
89 compatible = "register-bit-led";
92 label = "versatile:7";
93 default-state = "off";
96 /* OSC1 on AB, OSC4 on PB */
97 osc1: cm_aux_osc@24M {
99 compatible = "arm,versatile-cm-auxosc";
100 clocks = <&xtal24mhz>;
103 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
106 compatible = "fixed-factor-clock";
109 clocks = <&xtal24mhz>;
114 compatible = "fixed-factor-clock";
117 clocks = <&xtal24mhz>;
122 /* 64 MiB NOR flash in non-interleaved chips */
123 compatible = "arm,versatile-flash", "cfi-flash";
124 reg = <0x34000000 0x04000000>;
129 #address-cells = <1>;
131 compatible = "arm,versatile-i2c";
132 reg = <0x10002000 0x1000>;
135 compatible = "dallas,ds1338";
141 compatible = "smsc,lan91c111";
142 reg = <0x10010000 0x10000>;
147 compatible = "arm,versatile-lcd";
148 reg = <0x10008000 0x1000>;
152 compatible = "simple-bus";
153 #address-cells = <1>;
158 compatible = "arm,versatile-vic";
159 interrupt-controller;
160 #interrupt-cells = <1>;
161 reg = <0x10140000 0x1000>;
162 clear-mask = <0xffffffff>;
163 valid-mask = <0xffffffff>;
167 compatible = "arm,versatile-sic";
168 interrupt-controller;
169 #interrupt-cells = <1>;
170 reg = <0x10003000 0x1000>;
171 interrupt-parent = <&vic>;
172 interrupts = <31>; /* Cascaded to vic */
173 clear-mask = <0xffffffff>;
175 * Valid interrupt lines mask according to
176 * table 4-36 page 4-50 of ARM DUI 0225D
178 valid-mask = <0x0760031b>;
182 compatible = "arm,pl081", "arm,primecell";
183 reg = <0x10130000 0x1000>;
186 clock-names = "apb_pclk";
189 uart0: uart@101f1000 {
190 compatible = "arm,pl011", "arm,primecell";
191 reg = <0x101f1000 0x1000>;
193 clocks = <&xtal24mhz>, <&pclk>;
194 clock-names = "uartclk", "apb_pclk";
197 uart1: uart@101f2000 {
198 compatible = "arm,pl011", "arm,primecell";
199 reg = <0x101f2000 0x1000>;
201 clocks = <&xtal24mhz>, <&pclk>;
202 clock-names = "uartclk", "apb_pclk";
205 uart2: uart@101f3000 {
206 compatible = "arm,pl011", "arm,primecell";
207 reg = <0x101f3000 0x1000>;
209 clocks = <&xtal24mhz>, <&pclk>;
210 clock-names = "uartclk", "apb_pclk";
214 compatible = "arm,primecell";
215 reg = <0x10100000 0x1000>;
217 clock-names = "apb_pclk";
221 compatible = "arm,primecell";
222 reg = <0x10110000 0x1000>;
224 clock-names = "apb_pclk";
228 compatible = "arm,pl110", "arm,primecell";
229 reg = <0x10120000 0x1000>;
231 clocks = <&osc1>, <&pclk>;
232 clock-names = "clcd", "apb_pclk";
236 compatible = "arm,primecell";
237 reg = <0x101e0000 0x1000>;
239 clock-names = "apb_pclk";
243 compatible = "arm,primecell";
244 reg = <0x101e1000 0x1000>;
247 clock-names = "apb_pclk";
251 compatible = "arm,sp804", "arm,primecell";
252 reg = <0x101e2000 0x1000>;
254 clocks = <&timclk>, <&timclk>, <&pclk>;
255 clock-names = "timer0", "timer1", "apb_pclk";
259 compatible = "arm,sp804", "arm,primecell";
260 reg = <0x101e3000 0x1000>;
262 clocks = <&timclk>, <&timclk>, <&pclk>;
263 clock-names = "timer0", "timer1", "apb_pclk";
266 gpio0: gpio@101e4000 {
267 compatible = "arm,pl061", "arm,primecell";
268 reg = <0x101e4000 0x1000>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
275 clock-names = "apb_pclk";
278 gpio1: gpio@101e5000 {
279 compatible = "arm,pl061", "arm,primecell";
280 reg = <0x101e5000 0x1000>;
284 interrupt-controller;
285 #interrupt-cells = <2>;
287 clock-names = "apb_pclk";
291 compatible = "arm,pl030", "arm,primecell";
292 reg = <0x101e8000 0x1000>;
295 clock-names = "apb_pclk";
299 compatible = "arm,primecell";
300 reg = <0x101f0000 0x1000>;
303 clock-names = "apb_pclk";
307 compatible = "arm,pl022", "arm,primecell";
308 reg = <0x101f4000 0x1000>;
310 clocks = <&xtal24mhz>, <&pclk>;
311 clock-names = "SSPCLK", "apb_pclk";
315 compatible = "arm,versatile-fpga", "simple-bus";
316 #address-cells = <1>;
318 ranges = <0 0x10000000 0x10000>;
321 compatible = "arm,versatile-sysreg", "syscon";
322 reg = <0x00000 0x1000>;
326 compatible = "arm,primecell";
327 reg = <0x4000 0x1000>;
330 clock-names = "apb_pclk";
333 compatible = "arm,pl180", "arm,primecell";
334 reg = <0x5000 0x1000>;
335 interrupts-extended = <&vic 22 &sic 1>;
336 clocks = <&xtal24mhz>, <&pclk>;
337 clock-names = "mclk", "apb_pclk";
340 compatible = "arm,pl050", "arm,primecell";
341 reg = <0x6000 0x1000>;
342 interrupt-parent = <&sic>;
344 clocks = <&xtal24mhz>, <&pclk>;
345 clock-names = "KMIREFCLK", "apb_pclk";
348 compatible = "arm,pl050", "arm,primecell";
349 reg = <0x7000 0x1000>;
350 interrupt-parent = <&sic>;
352 clocks = <&xtal24mhz>, <&pclk>;
353 clock-names = "KMIREFCLK", "apb_pclk";