arch/arm/boot/dts/versatile-ab.dts

   1 /dts-v1/;
   2 /include/ "skeleton.dtsi"
   3
   4 / {
   5         model = "ARM Versatile AB";
   6         compatible = "arm,versatile-ab";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 serial0 = &uart0;
  13                 serial1 = &uart1;
  14                 serial2 = &uart2;
  15                 i2c0 = &i2c0;
  16         };
  17
  18         chosen {
  19                 stdout-path = &uart0;
  20         };
  21
  22         memory {
  23                 reg = <0x0 0x08000000>;
  24         };
  25
  26         xtal24mhz: xtal24mhz@24M {
  27                 #clock-cells = <0>;
  28                 compatible = "fixed-clock";
  29                 clock-frequency = <24000000>;
  30         };
  31
  32         core-module@10000000 {
  33                 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
  34                 reg = <0x10000000 0x200>;
  35
  36                 led@08.0 {
  37                         compatible = "register-bit-led";
  38                         offset = <0x08>;
  39                         mask = <0x01>;
  40                         label = "versatile:0";
  41                         linux,default-trigger = "heartbeat";
  42                         default-state = "on";
  43                 };
  44                 led@08.1 {
  45                         compatible = "register-bit-led";
  46                         offset = <0x08>;
  47                         mask = <0x02>;
  48                         label = "versatile:1";
  49                         linux,default-trigger = "mmc0";
  50                         default-state = "off";
  51                 };
  52                 led@08.2 {
  53                         compatible = "register-bit-led";
  54                         offset = <0x08>;
  55                         mask = <0x04>;
  56                         label = "versatile:2";
  57                         linux,default-trigger = "cpu0";
  58                         default-state = "off";
  59                 };
  60                 led@08.3 {
  61                         compatible = "register-bit-led";
  62                         offset = <0x08>;
  63                         mask = <0x08>;
  64                         label = "versatile:3";
  65                         default-state = "off";
  66                 };
  67                 led@08.4 {
  68                         compatible = "register-bit-led";
  69                         offset = <0x08>;
  70                         mask = <0x10>;
  71                         label = "versatile:4";
  72                         default-state = "off";
  73                 };
  74                 led@08.5 {
  75                         compatible = "register-bit-led";
  76                         offset = <0x08>;
  77                         mask = <0x20>;
  78                         label = "versatile:5";
  79                         default-state = "off";
  80                 };
  81                 led@08.6 {
  82                         compatible = "register-bit-led";
  83                         offset = <0x08>;
  84                         mask = <0x40>;
  85                         label = "versatile:6";
  86                         default-state = "off";
  87                 };
  88                 led@08.7 {
  89                         compatible = "register-bit-led";
  90                         offset = <0x08>;
  91                         mask = <0x80>;
  92                         label = "versatile:7";
  93                         default-state = "off";
  94                 };
  95
  96                 /* OSC1 on AB, OSC4 on PB */
  97                 osc1: cm_aux_osc@24M {
  98                         #clock-cells = <0>;
  99                         compatible = "arm,versatile-cm-auxosc";
 100                         clocks = <&xtal24mhz>;
 101                 };
 102
 103                 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
 104                 timclk: timclk@1M {
 105                         #clock-cells = <0>;
 106                         compatible = "fixed-factor-clock";
 107                         clock-div = <24>;
 108                         clock-mult = <1>;
 109                         clocks = <&xtal24mhz>;
 110                 };
 111
 112                 pclk: pclk@24M {
 113                         #clock-cells = <0>;
 114                         compatible = "fixed-factor-clock";
 115                         clock-div = <1>;
 116                         clock-mult = <1>;
 117                         clocks = <&xtal24mhz>;
 118                 };
 119         };
 120
 121         flash@34000000 {
 122                 /* 64 MiB NOR flash in non-interleaved chips */
 123                 compatible = "arm,versatile-flash", "cfi-flash";
 124                 reg = <0x34000000 0x04000000>;
 125                 bank-width = <4>;
 126         };
 127
 128         i2c0: i2c@10002000 {
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131                 compatible = "arm,versatile-i2c";
 132                 reg = <0x10002000 0x1000>;
 133
 134                 rtc@68 {
 135                         compatible = "dallas,ds1338";
 136                         reg = <0x68>;
 137                 };
 138         };
 139
 140         net@10010000 {
 141                 compatible = "smsc,lan91c111";
 142                 reg = <0x10010000 0x10000>;
 143                 interrupts = <25>;
 144         };
 145
 146         lcd@10008000 {
 147                 compatible = "arm,versatile-lcd";
 148                 reg = <0x10008000 0x1000>;
 149         };
 150
 151         amba {
 152                 compatible = "simple-bus";
 153                 #address-cells = <1>;
 154                 #size-cells = <1>;
 155                 ranges;
 156
 157                 vic: intc@10140000 {
 158                         compatible = "arm,versatile-vic";
 159                         interrupt-controller;
 160                         #interrupt-cells = <1>;
 161                         reg = <0x10140000 0x1000>;
 162                         clear-mask = <0xffffffff>;
 163                         valid-mask = <0xffffffff>;
 164                 };
 165
 166                 sic: intc@10003000 {
 167                         compatible = "arm,versatile-sic";
 168                         interrupt-controller;
 169                         #interrupt-cells = <1>;
 170                         reg = <0x10003000 0x1000>;
 171                         interrupt-parent = <&vic>;
 172                         interrupts = <31>; /* Cascaded to vic */
 173                         clear-mask = <0xffffffff>;
 174                         /*
 175                          * Valid interrupt lines mask according to
 176                          * table 4-36 page 4-50 of ARM DUI 0225D
 177                          */
 178                         valid-mask = <0x0760031b>;
 179                 };
 180
 181                 dma@10130000 {
 182                         compatible = "arm,pl081", "arm,primecell";
 183                         reg = <0x10130000 0x1000>;
 184                         interrupts = <17>;
 185                         clocks = <&pclk>;
 186                         clock-names = "apb_pclk";
 187                 };
 188
 189                 uart0: uart@101f1000 {
 190                         compatible = "arm,pl011", "arm,primecell";
 191                         reg = <0x101f1000 0x1000>;
 192                         interrupts = <12>;
 193                         clocks = <&xtal24mhz>, <&pclk>;
 194                         clock-names = "uartclk", "apb_pclk";
 195                 };
 196
 197                 uart1: uart@101f2000 {
 198                         compatible = "arm,pl011", "arm,primecell";
 199                         reg = <0x101f2000 0x1000>;
 200                         interrupts = <13>;
 201                         clocks = <&xtal24mhz>, <&pclk>;
 202                         clock-names = "uartclk", "apb_pclk";
 203                 };
 204
 205                 uart2: uart@101f3000 {
 206                         compatible = "arm,pl011", "arm,primecell";
 207                         reg = <0x101f3000 0x1000>;
 208                         interrupts = <14>;
 209                         clocks = <&xtal24mhz>, <&pclk>;
 210                         clock-names = "uartclk", "apb_pclk";
 211                 };
 212
 213                 smc@10100000 {
 214                         compatible = "arm,primecell";
 215                         reg = <0x10100000 0x1000>;
 216                         clocks = <&pclk>;
 217                         clock-names = "apb_pclk";
 218                 };
 219
 220                 mpmc@10110000 {
 221                         compatible = "arm,primecell";
 222                         reg = <0x10110000 0x1000>;
 223                         clocks = <&pclk>;
 224                         clock-names = "apb_pclk";
 225                 };
 226
 227                 display@10120000 {
 228                         compatible = "arm,pl110", "arm,primecell";
 229                         reg = <0x10120000 0x1000>;
 230                         interrupts = <16>;
 231                         clocks = <&osc1>, <&pclk>;
 232                         clock-names = "clcd", "apb_pclk";
 233                 };
 234
 235                 sctl@101e0000 {
 236                         compatible = "arm,primecell";
 237                         reg = <0x101e0000 0x1000>;
 238                         clocks = <&pclk>;
 239                         clock-names = "apb_pclk";
 240                 };
 241
 242                 watchdog@101e1000 {
 243                         compatible = "arm,primecell";
 244                         reg = <0x101e1000 0x1000>;
 245                         interrupts = <0>;
 246                         clocks = <&pclk>;
 247                         clock-names = "apb_pclk";
 248                 };
 249
 250                 timer@101e2000 {
 251                         compatible = "arm,sp804", "arm,primecell";
 252                         reg = <0x101e2000 0x1000>;
 253                         interrupts = <4>;
 254                         clocks = <&timclk>, <&timclk>, <&pclk>;
 255                         clock-names = "timer0", "timer1", "apb_pclk";
 256                 };
 257
 258                 timer@101e3000 {
 259                         compatible = "arm,sp804", "arm,primecell";
 260                         reg = <0x101e3000 0x1000>;
 261                         interrupts = <5>;
 262                         clocks = <&timclk>, <&timclk>, <&pclk>;
 263                         clock-names = "timer0", "timer1", "apb_pclk";
 264                 };
 265
 266                 gpio0: gpio@101e4000 {
 267                         compatible = "arm,pl061", "arm,primecell";
 268                         reg = <0x101e4000 0x1000>;
 269                         gpio-controller;
 270                         interrupts = <6>;
 271                         #gpio-cells = <2>;
 272                         interrupt-controller;
 273                         #interrupt-cells = <2>;
 274                         clocks = <&pclk>;
 275                         clock-names = "apb_pclk";
 276                 };
 277
 278                 gpio1: gpio@101e5000 {
 279                         compatible = "arm,pl061", "arm,primecell";
 280                         reg = <0x101e5000 0x1000>;
 281                         interrupts = <7>;
 282                         gpio-controller;
 283                         #gpio-cells = <2>;
 284                         interrupt-controller;
 285                         #interrupt-cells = <2>;
 286                         clocks = <&pclk>;
 287                         clock-names = "apb_pclk";
 288                 };
 289
 290                 rtc@101e8000 {
 291                         compatible = "arm,pl030", "arm,primecell";
 292                         reg = <0x101e8000 0x1000>;
 293                         interrupts = <10>;
 294                         clocks = <&pclk>;
 295                         clock-names = "apb_pclk";
 296                 };
 297
 298                 sci@101f0000 {
 299                         compatible = "arm,primecell";
 300                         reg = <0x101f0000 0x1000>;
 301                         interrupts = <15>;
 302                         clocks = <&pclk>;
 303                         clock-names = "apb_pclk";
 304                 };
 305
 306                 ssp@101f4000 {
 307                         compatible = "arm,pl022", "arm,primecell";
 308                         reg = <0x101f4000 0x1000>;
 309                         interrupts = <11>;
 310                         clocks = <&xtal24mhz>, <&pclk>;
 311                         clock-names = "SSPCLK", "apb_pclk";
 312                 };
 313
 314                 fpga {
 315                         compatible = "arm,versatile-fpga", "simple-bus";
 316                         #address-cells = <1>;
 317                         #size-cells = <1>;
 318                         ranges = <0 0x10000000 0x10000>;
 319
 320                         sysreg@0 {
 321                                 compatible = "arm,versatile-sysreg", "syscon";
 322                                 reg = <0x00000 0x1000>;
 323                         };
 324
 325                         aaci@4000 {
 326                                 compatible = "arm,primecell";
 327                                 reg = <0x4000 0x1000>;
 328                                 interrupts = <24>;
 329                                 clocks = <&pclk>;
 330                                 clock-names = "apb_pclk";
 331                         };
 332                         mmc@5000 {
 333                                 compatible = "arm,pl180", "arm,primecell";
 334                                 reg = <0x5000 0x1000>;
 335                                 interrupts-extended = <&vic 22 &sic 1>;
 336                                 clocks = <&xtal24mhz>, <&pclk>;
 337                                 clock-names = "mclk", "apb_pclk";
 338                         };
 339                         kmi@6000 {
 340                                 compatible = "arm,pl050", "arm,primecell";
 341                                 reg = <0x6000 0x1000>;
 342                                 interrupt-parent = <&sic>;
 343                                 interrupts = <3>;
 344                                 clocks = <&xtal24mhz>, <&pclk>;
 345                                 clock-names = "KMIREFCLK", "apb_pclk";
 346                         };
 347                         kmi@7000 {
 348                                 compatible = "arm,pl050", "arm,primecell";
 349                                 reg = <0x7000 0x1000>;
 350                                 interrupt-parent = <&sic>;
 351                                 interrupts = <4>;
 352                                 clocks = <&xtal24mhz>, <&pclk>;
 353                                 clock-names = "KMIREFCLK", "apb_pclk";
 354                         };
 355                 };
 356         };
 357 };