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ARM: edma: Get IP configuration from HW (number of channels, tc, etc)
[deliverable/linux.git] / arch / arm / common / edma.c
1 /*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/slab.h>
28 #include <linux/edma.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34
35 #include <linux/platform_data/edma.h>
36
37 /* Offsets matching "struct edmacc_param" */
38 #define PARM_OPT 0x00
39 #define PARM_SRC 0x04
40 #define PARM_A_B_CNT 0x08
41 #define PARM_DST 0x0c
42 #define PARM_SRC_DST_BIDX 0x10
43 #define PARM_LINK_BCNTRLD 0x14
44 #define PARM_SRC_DST_CIDX 0x18
45 #define PARM_CCNT 0x1c
46
47 #define PARM_SIZE 0x20
48
49 /* Offsets for EDMA CC global channel registers and their shadows */
50 #define SH_ER 0x00 /* 64 bits */
51 #define SH_ECR 0x08 /* 64 bits */
52 #define SH_ESR 0x10 /* 64 bits */
53 #define SH_CER 0x18 /* 64 bits */
54 #define SH_EER 0x20 /* 64 bits */
55 #define SH_EECR 0x28 /* 64 bits */
56 #define SH_EESR 0x30 /* 64 bits */
57 #define SH_SER 0x38 /* 64 bits */
58 #define SH_SECR 0x40 /* 64 bits */
59 #define SH_IER 0x50 /* 64 bits */
60 #define SH_IECR 0x58 /* 64 bits */
61 #define SH_IESR 0x60 /* 64 bits */
62 #define SH_IPR 0x68 /* 64 bits */
63 #define SH_ICR 0x70 /* 64 bits */
64 #define SH_IEVAL 0x78
65 #define SH_QER 0x80
66 #define SH_QEER 0x84
67 #define SH_QEECR 0x88
68 #define SH_QEESR 0x8c
69 #define SH_QSER 0x90
70 #define SH_QSECR 0x94
71 #define SH_SIZE 0x200
72
73 /* Offsets for EDMA CC global registers */
74 #define EDMA_REV 0x0000
75 #define EDMA_CCCFG 0x0004
76 #define EDMA_QCHMAP 0x0200 /* 8 registers */
77 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
78 #define EDMA_QDMAQNUM 0x0260
79 #define EDMA_QUETCMAP 0x0280
80 #define EDMA_QUEPRI 0x0284
81 #define EDMA_EMR 0x0300 /* 64 bits */
82 #define EDMA_EMCR 0x0308 /* 64 bits */
83 #define EDMA_QEMR 0x0310
84 #define EDMA_QEMCR 0x0314
85 #define EDMA_CCERR 0x0318
86 #define EDMA_CCERRCLR 0x031c
87 #define EDMA_EEVAL 0x0320
88 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
89 #define EDMA_QRAE 0x0380 /* 4 registers */
90 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
91 #define EDMA_QSTAT 0x0600 /* 2 registers */
92 #define EDMA_QWMTHRA 0x0620
93 #define EDMA_QWMTHRB 0x0624
94 #define EDMA_CCSTAT 0x0640
95
96 #define EDMA_M 0x1000 /* global channel registers */
97 #define EDMA_ECR 0x1008
98 #define EDMA_ECRH 0x100C
99 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
100 #define EDMA_PARM 0x4000 /* 128 param entries */
101
102 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
103
104 #define EDMA_DCHMAP 0x0100 /* 64 registers */
105
106 /* CCCFG register */
107 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
108 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
109 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
110 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
111 #define CHMAP_EXIST BIT(24)
112
113 #define EDMA_MAX_DMACH 64
114 #define EDMA_MAX_PARAMENTRY 512
115
116 /*****************************************************************************/
117
118 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
119
120 static inline unsigned int edma_read(unsigned ctlr, int offset)
121 {
122 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
123 }
124
125 static inline void edma_write(unsigned ctlr, int offset, int val)
126 {
127 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
128 }
129 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
130 unsigned or)
131 {
132 unsigned val = edma_read(ctlr, offset);
133 val &= and;
134 val |= or;
135 edma_write(ctlr, offset, val);
136 }
137 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
138 {
139 unsigned val = edma_read(ctlr, offset);
140 val &= and;
141 edma_write(ctlr, offset, val);
142 }
143 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
144 {
145 unsigned val = edma_read(ctlr, offset);
146 val |= or;
147 edma_write(ctlr, offset, val);
148 }
149 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
150 {
151 return edma_read(ctlr, offset + (i << 2));
152 }
153 static inline void edma_write_array(unsigned ctlr, int offset, int i,
154 unsigned val)
155 {
156 edma_write(ctlr, offset + (i << 2), val);
157 }
158 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
159 unsigned and, unsigned or)
160 {
161 edma_modify(ctlr, offset + (i << 2), and, or);
162 }
163 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
164 {
165 edma_or(ctlr, offset + (i << 2), or);
166 }
167 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
168 unsigned or)
169 {
170 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
171 }
172 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
173 unsigned val)
174 {
175 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
176 }
177 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
178 {
179 return edma_read(ctlr, EDMA_SHADOW0 + offset);
180 }
181 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
182 int i)
183 {
184 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
185 }
186 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
187 {
188 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
189 }
190 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
191 unsigned val)
192 {
193 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
194 }
195 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
196 int param_no)
197 {
198 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
199 }
200 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
201 unsigned val)
202 {
203 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
204 }
205 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
206 unsigned and, unsigned or)
207 {
208 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
209 }
210 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
211 unsigned and)
212 {
213 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
214 }
215 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
216 unsigned or)
217 {
218 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
219 }
220
221 static inline void set_bits(int offset, int len, unsigned long *p)
222 {
223 for (; len > 0; len--)
224 set_bit(offset + (len - 1), p);
225 }
226
227 static inline void clear_bits(int offset, int len, unsigned long *p)
228 {
229 for (; len > 0; len--)
230 clear_bit(offset + (len - 1), p);
231 }
232
233 /*****************************************************************************/
234
235 /* actual number of DMA channels and slots on this silicon */
236 struct edma {
237 /* how many dma resources of each type */
238 unsigned num_channels;
239 unsigned num_region;
240 unsigned num_slots;
241 unsigned num_tc;
242 enum dma_event_q default_queue;
243
244 /* list of channels with no even trigger; terminated by "-1" */
245 const s8 *noevent;
246
247 /* The edma_inuse bit for each PaRAM slot is clear unless the
248 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
249 */
250 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
251
252 /* The edma_unused bit for each channel is clear unless
253 * it is not being used on this platform. It uses a bit
254 * of SOC-specific initialization code.
255 */
256 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
257
258 unsigned irq_res_start;
259 unsigned irq_res_end;
260
261 struct dma_interrupt_data {
262 void (*callback)(unsigned channel, unsigned short ch_status,
263 void *data);
264 void *data;
265 } intr_data[EDMA_MAX_DMACH];
266 };
267
268 static struct edma *edma_cc[EDMA_MAX_CC];
269 static int arch_num_cc;
270
271 /* dummy param set used to (re)initialize parameter RAM slots */
272 static const struct edmacc_param dummy_paramset = {
273 .link_bcntrld = 0xffff,
274 .ccnt = 1,
275 };
276
277 static const struct of_device_id edma_of_ids[] = {
278 { .compatible = "ti,edma3", },
279 {}
280 };
281
282 /*****************************************************************************/
283
284 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
285 enum dma_event_q queue_no)
286 {
287 int bit = (ch_no & 0x7) * 4;
288
289 /* default to low priority queue */
290 if (queue_no == EVENTQ_DEFAULT)
291 queue_no = edma_cc[ctlr]->default_queue;
292
293 queue_no &= 7;
294 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
295 ~(0x7 << bit), queue_no << bit);
296 }
297
298 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
299 int priority)
300 {
301 int bit = queue_no * 4;
302 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
303 ((priority & 0x7) << bit));
304 }
305
306 /**
307 * map_dmach_param - Maps channel number to param entry number
308 *
309 * This maps the dma channel number to param entry numberter. In
310 * other words using the DMA channel mapping registers a param entry
311 * can be mapped to any channel
312 *
313 * Callers are responsible for ensuring the channel mapping logic is
314 * included in that particular EDMA variant (Eg : dm646x)
315 *
316 */
317 static void __init map_dmach_param(unsigned ctlr)
318 {
319 int i;
320 for (i = 0; i < EDMA_MAX_DMACH; i++)
321 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
322 }
323
324 static inline void
325 setup_dma_interrupt(unsigned lch,
326 void (*callback)(unsigned channel, u16 ch_status, void *data),
327 void *data)
328 {
329 unsigned ctlr;
330
331 ctlr = EDMA_CTLR(lch);
332 lch = EDMA_CHAN_SLOT(lch);
333
334 if (!callback)
335 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
336 BIT(lch & 0x1f));
337
338 edma_cc[ctlr]->intr_data[lch].callback = callback;
339 edma_cc[ctlr]->intr_data[lch].data = data;
340
341 if (callback) {
342 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
343 BIT(lch & 0x1f));
344 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
345 BIT(lch & 0x1f));
346 }
347 }
348
349 static int irq2ctlr(int irq)
350 {
351 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
352 return 0;
353 else if (irq >= edma_cc[1]->irq_res_start &&
354 irq <= edma_cc[1]->irq_res_end)
355 return 1;
356
357 return -1;
358 }
359
360 /******************************************************************************
361 *
362 * DMA interrupt handler
363 *
364 *****************************************************************************/
365 static irqreturn_t dma_irq_handler(int irq, void *data)
366 {
367 int ctlr;
368 u32 sh_ier;
369 u32 sh_ipr;
370 u32 bank;
371
372 ctlr = irq2ctlr(irq);
373 if (ctlr < 0)
374 return IRQ_NONE;
375
376 dev_dbg(data, "dma_irq_handler\n");
377
378 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
379 if (!sh_ipr) {
380 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
381 if (!sh_ipr)
382 return IRQ_NONE;
383 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
384 bank = 1;
385 } else {
386 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
387 bank = 0;
388 }
389
390 do {
391 u32 slot;
392 u32 channel;
393
394 dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
395
396 slot = __ffs(sh_ipr);
397 sh_ipr &= ~(BIT(slot));
398
399 if (sh_ier & BIT(slot)) {
400 channel = (bank << 5) | slot;
401 /* Clear the corresponding IPR bits */
402 edma_shadow0_write_array(ctlr, SH_ICR, bank,
403 BIT(slot));
404 if (edma_cc[ctlr]->intr_data[channel].callback)
405 edma_cc[ctlr]->intr_data[channel].callback(
406 channel, EDMA_DMA_COMPLETE,
407 edma_cc[ctlr]->intr_data[channel].data);
408 }
409 } while (sh_ipr);
410
411 edma_shadow0_write(ctlr, SH_IEVAL, 1);
412 return IRQ_HANDLED;
413 }
414
415 /******************************************************************************
416 *
417 * DMA error interrupt handler
418 *
419 *****************************************************************************/
420 static irqreturn_t dma_ccerr_handler(int irq, void *data)
421 {
422 int i;
423 int ctlr;
424 unsigned int cnt = 0;
425
426 ctlr = irq2ctlr(irq);
427 if (ctlr < 0)
428 return IRQ_NONE;
429
430 dev_dbg(data, "dma_ccerr_handler\n");
431
432 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
433 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
434 (edma_read(ctlr, EDMA_QEMR) == 0) &&
435 (edma_read(ctlr, EDMA_CCERR) == 0))
436 return IRQ_NONE;
437
438 while (1) {
439 int j = -1;
440 if (edma_read_array(ctlr, EDMA_EMR, 0))
441 j = 0;
442 else if (edma_read_array(ctlr, EDMA_EMR, 1))
443 j = 1;
444 if (j >= 0) {
445 dev_dbg(data, "EMR%d %08x\n", j,
446 edma_read_array(ctlr, EDMA_EMR, j));
447 for (i = 0; i < 32; i++) {
448 int k = (j << 5) + i;
449 if (edma_read_array(ctlr, EDMA_EMR, j) &
450 BIT(i)) {
451 /* Clear the corresponding EMR bits */
452 edma_write_array(ctlr, EDMA_EMCR, j,
453 BIT(i));
454 /* Clear any SER */
455 edma_shadow0_write_array(ctlr, SH_SECR,
456 j, BIT(i));
457 if (edma_cc[ctlr]->intr_data[k].
458 callback) {
459 edma_cc[ctlr]->intr_data[k].
460 callback(k,
461 EDMA_DMA_CC_ERROR,
462 edma_cc[ctlr]->intr_data
463 [k].data);
464 }
465 }
466 }
467 } else if (edma_read(ctlr, EDMA_QEMR)) {
468 dev_dbg(data, "QEMR %02x\n",
469 edma_read(ctlr, EDMA_QEMR));
470 for (i = 0; i < 8; i++) {
471 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
472 /* Clear the corresponding IPR bits */
473 edma_write(ctlr, EDMA_QEMCR, BIT(i));
474 edma_shadow0_write(ctlr, SH_QSECR,
475 BIT(i));
476
477 /* NOTE: not reported!! */
478 }
479 }
480 } else if (edma_read(ctlr, EDMA_CCERR)) {
481 dev_dbg(data, "CCERR %08x\n",
482 edma_read(ctlr, EDMA_CCERR));
483 /* FIXME: CCERR.BIT(16) ignored! much better
484 * to just write CCERRCLR with CCERR value...
485 */
486 for (i = 0; i < 8; i++) {
487 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
488 /* Clear the corresponding IPR bits */
489 edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
490
491 /* NOTE: not reported!! */
492 }
493 }
494 }
495 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
496 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
497 (edma_read(ctlr, EDMA_QEMR) == 0) &&
498 (edma_read(ctlr, EDMA_CCERR) == 0))
499 break;
500 cnt++;
501 if (cnt > 10)
502 break;
503 }
504 edma_write(ctlr, EDMA_EEVAL, 1);
505 return IRQ_HANDLED;
506 }
507
508 static int reserve_contiguous_slots(int ctlr, unsigned int id,
509 unsigned int num_slots,
510 unsigned int start_slot)
511 {
512 int i, j;
513 unsigned int count = num_slots;
514 int stop_slot = start_slot;
515 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
516
517 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
518 j = EDMA_CHAN_SLOT(i);
519 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
520 /* Record our current beginning slot */
521 if (count == num_slots)
522 stop_slot = i;
523
524 count--;
525 set_bit(j, tmp_inuse);
526
527 if (count == 0)
528 break;
529 } else {
530 clear_bit(j, tmp_inuse);
531
532 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
533 stop_slot = i;
534 break;
535 } else {
536 count = num_slots;
537 }
538 }
539 }
540
541 /*
542 * We have to clear any bits that we set
543 * if we run out parameter RAM slots, i.e we do find a set
544 * of contiguous parameter RAM slots but do not find the exact number
545 * requested as we may reach the total number of parameter RAM slots
546 */
547 if (i == edma_cc[ctlr]->num_slots)
548 stop_slot = i;
549
550 j = start_slot;
551 for_each_set_bit_from(j, tmp_inuse, stop_slot)
552 clear_bit(j, edma_cc[ctlr]->edma_inuse);
553
554 if (count)
555 return -EBUSY;
556
557 for (j = i - num_slots + 1; j <= i; ++j)
558 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
559 &dummy_paramset, PARM_SIZE);
560
561 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
562 }
563
564 static int prepare_unused_channel_list(struct device *dev, void *data)
565 {
566 struct platform_device *pdev = to_platform_device(dev);
567 int i, count, ctlr;
568 struct of_phandle_args dma_spec;
569
570 if (dev->of_node) {
571 count = of_property_count_strings(dev->of_node, "dma-names");
572 if (count < 0)
573 return 0;
574 for (i = 0; i < count; i++) {
575 if (of_parse_phandle_with_args(dev->of_node, "dmas",
576 "#dma-cells", i,
577 &dma_spec))
578 continue;
579
580 if (!of_match_node(edma_of_ids, dma_spec.np)) {
581 of_node_put(dma_spec.np);
582 continue;
583 }
584
585 clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
586 edma_cc[0]->edma_unused);
587 of_node_put(dma_spec.np);
588 }
589 return 0;
590 }
591
592 /* For non-OF case */
593 for (i = 0; i < pdev->num_resources; i++) {
594 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
595 (int)pdev->resource[i].start >= 0) {
596 ctlr = EDMA_CTLR(pdev->resource[i].start);
597 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
598 edma_cc[ctlr]->edma_unused);
599 }
600 }
601
602 return 0;
603 }
604
605 /*-----------------------------------------------------------------------*/
606
607 static bool unused_chan_list_done;
608
609 /* Resource alloc/free: dma channels, parameter RAM slots */
610
611 /**
612 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
613 * @channel: specific channel to allocate; negative for "any unmapped channel"
614 * @callback: optional; to be issued on DMA completion or errors
615 * @data: passed to callback
616 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
617 * Controller (TC) executes requests using this channel. Use
618 * EVENTQ_DEFAULT unless you really need a high priority queue.
619 *
620 * This allocates a DMA channel and its associated parameter RAM slot.
621 * The parameter RAM is initialized to hold a dummy transfer.
622 *
623 * Normal use is to pass a specific channel number as @channel, to make
624 * use of hardware events mapped to that channel. When the channel will
625 * be used only for software triggering or event chaining, channels not
626 * mapped to hardware events (or mapped to unused events) are preferable.
627 *
628 * DMA transfers start from a channel using edma_start(), or by
629 * chaining. When the transfer described in that channel's parameter RAM
630 * slot completes, that slot's data may be reloaded through a link.
631 *
632 * DMA errors are only reported to the @callback associated with the
633 * channel driving that transfer, but transfer completion callbacks can
634 * be sent to another channel under control of the TCC field in
635 * the option word of the transfer's parameter RAM set. Drivers must not
636 * use DMA transfer completion callbacks for channels they did not allocate.
637 * (The same applies to TCC codes used in transfer chaining.)
638 *
639 * Returns the number of the channel, else negative errno.
640 */
641 int edma_alloc_channel(int channel,
642 void (*callback)(unsigned channel, u16 ch_status, void *data),
643 void *data,
644 enum dma_event_q eventq_no)
645 {
646 unsigned i, done = 0, ctlr = 0;
647 int ret = 0;
648
649 if (!unused_chan_list_done) {
650 /*
651 * Scan all the platform devices to find out the EDMA channels
652 * used and clear them in the unused list, making the rest
653 * available for ARM usage.
654 */
655 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
656 prepare_unused_channel_list);
657 if (ret < 0)
658 return ret;
659
660 unused_chan_list_done = true;
661 }
662
663 if (channel >= 0) {
664 ctlr = EDMA_CTLR(channel);
665 channel = EDMA_CHAN_SLOT(channel);
666 }
667
668 if (channel < 0) {
669 for (i = 0; i < arch_num_cc; i++) {
670 channel = 0;
671 for (;;) {
672 channel = find_next_bit(edma_cc[i]->edma_unused,
673 edma_cc[i]->num_channels,
674 channel);
675 if (channel == edma_cc[i]->num_channels)
676 break;
677 if (!test_and_set_bit(channel,
678 edma_cc[i]->edma_inuse)) {
679 done = 1;
680 ctlr = i;
681 break;
682 }
683 channel++;
684 }
685 if (done)
686 break;
687 }
688 if (!done)
689 return -ENOMEM;
690 } else if (channel >= edma_cc[ctlr]->num_channels) {
691 return -EINVAL;
692 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
693 return -EBUSY;
694 }
695
696 /* ensure access through shadow region 0 */
697 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
698
699 /* ensure no events are pending */
700 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
701 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
702 &dummy_paramset, PARM_SIZE);
703
704 if (callback)
705 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
706 callback, data);
707
708 map_dmach_queue(ctlr, channel, eventq_no);
709
710 return EDMA_CTLR_CHAN(ctlr, channel);
711 }
712 EXPORT_SYMBOL(edma_alloc_channel);
713
714
715 /**
716 * edma_free_channel - deallocate DMA channel
717 * @channel: dma channel returned from edma_alloc_channel()
718 *
719 * This deallocates the DMA channel and associated parameter RAM slot
720 * allocated by edma_alloc_channel().
721 *
722 * Callers are responsible for ensuring the channel is inactive, and
723 * will not be reactivated by linking, chaining, or software calls to
724 * edma_start().
725 */
726 void edma_free_channel(unsigned channel)
727 {
728 unsigned ctlr;
729
730 ctlr = EDMA_CTLR(channel);
731 channel = EDMA_CHAN_SLOT(channel);
732
733 if (channel >= edma_cc[ctlr]->num_channels)
734 return;
735
736 setup_dma_interrupt(channel, NULL, NULL);
737 /* REVISIT should probably take out of shadow region 0 */
738
739 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
740 &dummy_paramset, PARM_SIZE);
741 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
742 }
743 EXPORT_SYMBOL(edma_free_channel);
744
745 /**
746 * edma_alloc_slot - allocate DMA parameter RAM
747 * @slot: specific slot to allocate; negative for "any unused slot"
748 *
749 * This allocates a parameter RAM slot, initializing it to hold a
750 * dummy transfer. Slots allocated using this routine have not been
751 * mapped to a hardware DMA channel, and will normally be used by
752 * linking to them from a slot associated with a DMA channel.
753 *
754 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
755 * slots may be allocated on behalf of DSP firmware.
756 *
757 * Returns the number of the slot, else negative errno.
758 */
759 int edma_alloc_slot(unsigned ctlr, int slot)
760 {
761 if (!edma_cc[ctlr])
762 return -EINVAL;
763
764 if (slot >= 0)
765 slot = EDMA_CHAN_SLOT(slot);
766
767 if (slot < 0) {
768 slot = edma_cc[ctlr]->num_channels;
769 for (;;) {
770 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
771 edma_cc[ctlr]->num_slots, slot);
772 if (slot == edma_cc[ctlr]->num_slots)
773 return -ENOMEM;
774 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
775 break;
776 }
777 } else if (slot < edma_cc[ctlr]->num_channels ||
778 slot >= edma_cc[ctlr]->num_slots) {
779 return -EINVAL;
780 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
781 return -EBUSY;
782 }
783
784 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
785 &dummy_paramset, PARM_SIZE);
786
787 return EDMA_CTLR_CHAN(ctlr, slot);
788 }
789 EXPORT_SYMBOL(edma_alloc_slot);
790
791 /**
792 * edma_free_slot - deallocate DMA parameter RAM
793 * @slot: parameter RAM slot returned from edma_alloc_slot()
794 *
795 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
796 * Callers are responsible for ensuring the slot is inactive, and will
797 * not be activated.
798 */
799 void edma_free_slot(unsigned slot)
800 {
801 unsigned ctlr;
802
803 ctlr = EDMA_CTLR(slot);
804 slot = EDMA_CHAN_SLOT(slot);
805
806 if (slot < edma_cc[ctlr]->num_channels ||
807 slot >= edma_cc[ctlr]->num_slots)
808 return;
809
810 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
811 &dummy_paramset, PARM_SIZE);
812 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
813 }
814 EXPORT_SYMBOL(edma_free_slot);
815
816
817 /**
818 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
819 * The API will return the starting point of a set of
820 * contiguous parameter RAM slots that have been requested
821 *
822 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
823 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
824 * @count: number of contiguous Paramter RAM slots
825 * @slot - the start value of Parameter RAM slot that should be passed if id
826 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
827 *
828 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
829 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
830 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
831 *
832 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
833 * set of contiguous parameter RAM slots from the "slot" that is passed as an
834 * argument to the API.
835 *
836 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
837 * starts looking for a set of contiguous parameter RAMs from the "slot"
838 * that is passed as an argument to the API. On failure the API will try to
839 * find a set of contiguous Parameter RAM slots from the remaining Parameter
840 * RAM slots
841 */
842 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
843 {
844 /*
845 * The start slot requested should be greater than
846 * the number of channels and lesser than the total number
847 * of slots
848 */
849 if ((id != EDMA_CONT_PARAMS_ANY) &&
850 (slot < edma_cc[ctlr]->num_channels ||
851 slot >= edma_cc[ctlr]->num_slots))
852 return -EINVAL;
853
854 /*
855 * The number of parameter RAM slots requested cannot be less than 1
856 * and cannot be more than the number of slots minus the number of
857 * channels
858 */
859 if (count < 1 || count >
860 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
861 return -EINVAL;
862
863 switch (id) {
864 case EDMA_CONT_PARAMS_ANY:
865 return reserve_contiguous_slots(ctlr, id, count,
866 edma_cc[ctlr]->num_channels);
867 case EDMA_CONT_PARAMS_FIXED_EXACT:
868 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
869 return reserve_contiguous_slots(ctlr, id, count, slot);
870 default:
871 return -EINVAL;
872 }
873
874 }
875 EXPORT_SYMBOL(edma_alloc_cont_slots);
876
877 /**
878 * edma_free_cont_slots - deallocate DMA parameter RAM slots
879 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
880 * @count: the number of contiguous parameter RAM slots to be freed
881 *
882 * This deallocates the parameter RAM slots allocated by
883 * edma_alloc_cont_slots.
884 * Callers/applications need to keep track of sets of contiguous
885 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
886 * API.
887 * Callers are responsible for ensuring the slots are inactive, and will
888 * not be activated.
889 */
890 int edma_free_cont_slots(unsigned slot, int count)
891 {
892 unsigned ctlr, slot_to_free;
893 int i;
894
895 ctlr = EDMA_CTLR(slot);
896 slot = EDMA_CHAN_SLOT(slot);
897
898 if (slot < edma_cc[ctlr]->num_channels ||
899 slot >= edma_cc[ctlr]->num_slots ||
900 count < 1)
901 return -EINVAL;
902
903 for (i = slot; i < slot + count; ++i) {
904 ctlr = EDMA_CTLR(i);
905 slot_to_free = EDMA_CHAN_SLOT(i);
906
907 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
908 &dummy_paramset, PARM_SIZE);
909 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
910 }
911
912 return 0;
913 }
914 EXPORT_SYMBOL(edma_free_cont_slots);
915
916 /*-----------------------------------------------------------------------*/
917
918 /* Parameter RAM operations (i) -- read/write partial slots */
919
920 /**
921 * edma_set_src - set initial DMA source address in parameter RAM slot
922 * @slot: parameter RAM slot being configured
923 * @src_port: physical address of source (memory, controller FIFO, etc)
924 * @addressMode: INCR, except in very rare cases
925 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
926 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
927 *
928 * Note that the source address is modified during the DMA transfer
929 * according to edma_set_src_index().
930 */
931 void edma_set_src(unsigned slot, dma_addr_t src_port,
932 enum address_mode mode, enum fifo_width width)
933 {
934 unsigned ctlr;
935
936 ctlr = EDMA_CTLR(slot);
937 slot = EDMA_CHAN_SLOT(slot);
938
939 if (slot < edma_cc[ctlr]->num_slots) {
940 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
941
942 if (mode) {
943 /* set SAM and program FWID */
944 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
945 } else {
946 /* clear SAM */
947 i &= ~SAM;
948 }
949 edma_parm_write(ctlr, PARM_OPT, slot, i);
950
951 /* set the source port address
952 in source register of param structure */
953 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
954 }
955 }
956 EXPORT_SYMBOL(edma_set_src);
957
958 /**
959 * edma_set_dest - set initial DMA destination address in parameter RAM slot
960 * @slot: parameter RAM slot being configured
961 * @dest_port: physical address of destination (memory, controller FIFO, etc)
962 * @addressMode: INCR, except in very rare cases
963 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
964 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
965 *
966 * Note that the destination address is modified during the DMA transfer
967 * according to edma_set_dest_index().
968 */
969 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
970 enum address_mode mode, enum fifo_width width)
971 {
972 unsigned ctlr;
973
974 ctlr = EDMA_CTLR(slot);
975 slot = EDMA_CHAN_SLOT(slot);
976
977 if (slot < edma_cc[ctlr]->num_slots) {
978 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
979
980 if (mode) {
981 /* set DAM and program FWID */
982 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
983 } else {
984 /* clear DAM */
985 i &= ~DAM;
986 }
987 edma_parm_write(ctlr, PARM_OPT, slot, i);
988 /* set the destination port address
989 in dest register of param structure */
990 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
991 }
992 }
993 EXPORT_SYMBOL(edma_set_dest);
994
995 /**
996 * edma_get_position - returns the current transfer point
997 * @slot: parameter RAM slot being examined
998 * @dst: true selects the dest position, false the source
999 *
1000 * Returns the position of the current active slot
1001 */
1002 dma_addr_t edma_get_position(unsigned slot, bool dst)
1003 {
1004 u32 offs, ctlr = EDMA_CTLR(slot);
1005
1006 slot = EDMA_CHAN_SLOT(slot);
1007
1008 offs = PARM_OFFSET(slot);
1009 offs += dst ? PARM_DST : PARM_SRC;
1010
1011 return edma_read(ctlr, offs);
1012 }
1013
1014 /**
1015 * edma_set_src_index - configure DMA source address indexing
1016 * @slot: parameter RAM slot being configured
1017 * @src_bidx: byte offset between source arrays in a frame
1018 * @src_cidx: byte offset between source frames in a block
1019 *
1020 * Offsets are specified to support either contiguous or discontiguous
1021 * memory transfers, or repeated access to a hardware register, as needed.
1022 * When accessing hardware registers, both offsets are normally zero.
1023 */
1024 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1025 {
1026 unsigned ctlr;
1027
1028 ctlr = EDMA_CTLR(slot);
1029 slot = EDMA_CHAN_SLOT(slot);
1030
1031 if (slot < edma_cc[ctlr]->num_slots) {
1032 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1033 0xffff0000, src_bidx);
1034 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1035 0xffff0000, src_cidx);
1036 }
1037 }
1038 EXPORT_SYMBOL(edma_set_src_index);
1039
1040 /**
1041 * edma_set_dest_index - configure DMA destination address indexing
1042 * @slot: parameter RAM slot being configured
1043 * @dest_bidx: byte offset between destination arrays in a frame
1044 * @dest_cidx: byte offset between destination frames in a block
1045 *
1046 * Offsets are specified to support either contiguous or discontiguous
1047 * memory transfers, or repeated access to a hardware register, as needed.
1048 * When accessing hardware registers, both offsets are normally zero.
1049 */
1050 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1051 {
1052 unsigned ctlr;
1053
1054 ctlr = EDMA_CTLR(slot);
1055 slot = EDMA_CHAN_SLOT(slot);
1056
1057 if (slot < edma_cc[ctlr]->num_slots) {
1058 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1059 0x0000ffff, dest_bidx << 16);
1060 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1061 0x0000ffff, dest_cidx << 16);
1062 }
1063 }
1064 EXPORT_SYMBOL(edma_set_dest_index);
1065
1066 /**
1067 * edma_set_transfer_params - configure DMA transfer parameters
1068 * @slot: parameter RAM slot being configured
1069 * @acnt: how many bytes per array (at least one)
1070 * @bcnt: how many arrays per frame (at least one)
1071 * @ccnt: how many frames per block (at least one)
1072 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1073 * the value to reload into bcnt when it decrements to zero
1074 * @sync_mode: ASYNC or ABSYNC
1075 *
1076 * See the EDMA3 documentation to understand how to configure and link
1077 * transfers using the fields in PaRAM slots. If you are not doing it
1078 * all at once with edma_write_slot(), you will use this routine
1079 * plus two calls each for source and destination, setting the initial
1080 * address and saying how to index that address.
1081 *
1082 * An example of an A-Synchronized transfer is a serial link using a
1083 * single word shift register. In that case, @acnt would be equal to
1084 * that word size; the serial controller issues a DMA synchronization
1085 * event to transfer each word, and memory access by the DMA transfer
1086 * controller will be word-at-a-time.
1087 *
1088 * An example of an AB-Synchronized transfer is a device using a FIFO.
1089 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1090 * The controller with the FIFO issues DMA synchronization events when
1091 * the FIFO threshold is reached, and the DMA transfer controller will
1092 * transfer one frame to (or from) the FIFO. It will probably use
1093 * efficient burst modes to access memory.
1094 */
1095 void edma_set_transfer_params(unsigned slot,
1096 u16 acnt, u16 bcnt, u16 ccnt,
1097 u16 bcnt_rld, enum sync_dimension sync_mode)
1098 {
1099 unsigned ctlr;
1100
1101 ctlr = EDMA_CTLR(slot);
1102 slot = EDMA_CHAN_SLOT(slot);
1103
1104 if (slot < edma_cc[ctlr]->num_slots) {
1105 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1106 0x0000ffff, bcnt_rld << 16);
1107 if (sync_mode == ASYNC)
1108 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1109 else
1110 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1111 /* Set the acount, bcount, ccount registers */
1112 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1113 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1114 }
1115 }
1116 EXPORT_SYMBOL(edma_set_transfer_params);
1117
1118 /**
1119 * edma_link - link one parameter RAM slot to another
1120 * @from: parameter RAM slot originating the link
1121 * @to: parameter RAM slot which is the link target
1122 *
1123 * The originating slot should not be part of any active DMA transfer.
1124 */
1125 void edma_link(unsigned from, unsigned to)
1126 {
1127 unsigned ctlr_from, ctlr_to;
1128
1129 ctlr_from = EDMA_CTLR(from);
1130 from = EDMA_CHAN_SLOT(from);
1131 ctlr_to = EDMA_CTLR(to);
1132 to = EDMA_CHAN_SLOT(to);
1133
1134 if (from >= edma_cc[ctlr_from]->num_slots)
1135 return;
1136 if (to >= edma_cc[ctlr_to]->num_slots)
1137 return;
1138 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1139 PARM_OFFSET(to));
1140 }
1141 EXPORT_SYMBOL(edma_link);
1142
1143 /**
1144 * edma_unlink - cut link from one parameter RAM slot
1145 * @from: parameter RAM slot originating the link
1146 *
1147 * The originating slot should not be part of any active DMA transfer.
1148 * Its link is set to 0xffff.
1149 */
1150 void edma_unlink(unsigned from)
1151 {
1152 unsigned ctlr;
1153
1154 ctlr = EDMA_CTLR(from);
1155 from = EDMA_CHAN_SLOT(from);
1156
1157 if (from >= edma_cc[ctlr]->num_slots)
1158 return;
1159 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1160 }
1161 EXPORT_SYMBOL(edma_unlink);
1162
1163 /*-----------------------------------------------------------------------*/
1164
1165 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1166
1167 /**
1168 * edma_write_slot - write parameter RAM data for slot
1169 * @slot: number of parameter RAM slot being modified
1170 * @param: data to be written into parameter RAM slot
1171 *
1172 * Use this to assign all parameters of a transfer at once. This
1173 * allows more efficient setup of transfers than issuing multiple
1174 * calls to set up those parameters in small pieces, and provides
1175 * complete control over all transfer options.
1176 */
1177 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1178 {
1179 unsigned ctlr;
1180
1181 ctlr = EDMA_CTLR(slot);
1182 slot = EDMA_CHAN_SLOT(slot);
1183
1184 if (slot >= edma_cc[ctlr]->num_slots)
1185 return;
1186 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1187 PARM_SIZE);
1188 }
1189 EXPORT_SYMBOL(edma_write_slot);
1190
1191 /**
1192 * edma_read_slot - read parameter RAM data from slot
1193 * @slot: number of parameter RAM slot being copied
1194 * @param: where to store copy of parameter RAM data
1195 *
1196 * Use this to read data from a parameter RAM slot, perhaps to
1197 * save them as a template for later reuse.
1198 */
1199 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1200 {
1201 unsigned ctlr;
1202
1203 ctlr = EDMA_CTLR(slot);
1204 slot = EDMA_CHAN_SLOT(slot);
1205
1206 if (slot >= edma_cc[ctlr]->num_slots)
1207 return;
1208 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1209 PARM_SIZE);
1210 }
1211 EXPORT_SYMBOL(edma_read_slot);
1212
1213 /*-----------------------------------------------------------------------*/
1214
1215 /* Various EDMA channel control operations */
1216
1217 /**
1218 * edma_pause - pause dma on a channel
1219 * @channel: on which edma_start() has been called
1220 *
1221 * This temporarily disables EDMA hardware events on the specified channel,
1222 * preventing them from triggering new transfers on its behalf
1223 */
1224 void edma_pause(unsigned channel)
1225 {
1226 unsigned ctlr;
1227
1228 ctlr = EDMA_CTLR(channel);
1229 channel = EDMA_CHAN_SLOT(channel);
1230
1231 if (channel < edma_cc[ctlr]->num_channels) {
1232 unsigned int mask = BIT(channel & 0x1f);
1233
1234 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1235 }
1236 }
1237 EXPORT_SYMBOL(edma_pause);
1238
1239 /**
1240 * edma_resume - resumes dma on a paused channel
1241 * @channel: on which edma_pause() has been called
1242 *
1243 * This re-enables EDMA hardware events on the specified channel.
1244 */
1245 void edma_resume(unsigned channel)
1246 {
1247 unsigned ctlr;
1248
1249 ctlr = EDMA_CTLR(channel);
1250 channel = EDMA_CHAN_SLOT(channel);
1251
1252 if (channel < edma_cc[ctlr]->num_channels) {
1253 unsigned int mask = BIT(channel & 0x1f);
1254
1255 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1256 }
1257 }
1258 EXPORT_SYMBOL(edma_resume);
1259
1260 int edma_trigger_channel(unsigned channel)
1261 {
1262 unsigned ctlr;
1263 unsigned int mask;
1264
1265 ctlr = EDMA_CTLR(channel);
1266 channel = EDMA_CHAN_SLOT(channel);
1267 mask = BIT(channel & 0x1f);
1268
1269 edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
1270
1271 pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
1272 edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
1273 return 0;
1274 }
1275 EXPORT_SYMBOL(edma_trigger_channel);
1276
1277 /**
1278 * edma_start - start dma on a channel
1279 * @channel: channel being activated
1280 *
1281 * Channels with event associations will be triggered by their hardware
1282 * events, and channels without such associations will be triggered by
1283 * software. (At this writing there is no interface for using software
1284 * triggers except with channels that don't support hardware triggers.)
1285 *
1286 * Returns zero on success, else negative errno.
1287 */
1288 int edma_start(unsigned channel)
1289 {
1290 unsigned ctlr;
1291
1292 ctlr = EDMA_CTLR(channel);
1293 channel = EDMA_CHAN_SLOT(channel);
1294
1295 if (channel < edma_cc[ctlr]->num_channels) {
1296 int j = channel >> 5;
1297 unsigned int mask = BIT(channel & 0x1f);
1298
1299 /* EDMA channels without event association */
1300 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1301 pr_debug("EDMA: ESR%d %08x\n", j,
1302 edma_shadow0_read_array(ctlr, SH_ESR, j));
1303 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1304 return 0;
1305 }
1306
1307 /* EDMA channel with event association */
1308 pr_debug("EDMA: ER%d %08x\n", j,
1309 edma_shadow0_read_array(ctlr, SH_ER, j));
1310 /* Clear any pending event or error */
1311 edma_write_array(ctlr, EDMA_ECR, j, mask);
1312 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1313 /* Clear any SER */
1314 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1315 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1316 pr_debug("EDMA: EER%d %08x\n", j,
1317 edma_shadow0_read_array(ctlr, SH_EER, j));
1318 return 0;
1319 }
1320
1321 return -EINVAL;
1322 }
1323 EXPORT_SYMBOL(edma_start);
1324
1325 /**
1326 * edma_stop - stops dma on the channel passed
1327 * @channel: channel being deactivated
1328 *
1329 * When @lch is a channel, any active transfer is paused and
1330 * all pending hardware events are cleared. The current transfer
1331 * may not be resumed, and the channel's Parameter RAM should be
1332 * reinitialized before being reused.
1333 */
1334 void edma_stop(unsigned channel)
1335 {
1336 unsigned ctlr;
1337
1338 ctlr = EDMA_CTLR(channel);
1339 channel = EDMA_CHAN_SLOT(channel);
1340
1341 if (channel < edma_cc[ctlr]->num_channels) {
1342 int j = channel >> 5;
1343 unsigned int mask = BIT(channel & 0x1f);
1344
1345 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1346 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1347 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1348 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1349
1350 pr_debug("EDMA: EER%d %08x\n", j,
1351 edma_shadow0_read_array(ctlr, SH_EER, j));
1352
1353 /* REVISIT: consider guarding against inappropriate event
1354 * chaining by overwriting with dummy_paramset.
1355 */
1356 }
1357 }
1358 EXPORT_SYMBOL(edma_stop);
1359
1360 /******************************************************************************
1361 *
1362 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1363 * been removed before EDMA has finished.It is usedful for removable media.
1364 * Arguments:
1365 * ch_no - channel no
1366 *
1367 * Return: zero on success, or corresponding error no on failure
1368 *
1369 * FIXME this should not be needed ... edma_stop() should suffice.
1370 *
1371 *****************************************************************************/
1372
1373 void edma_clean_channel(unsigned channel)
1374 {
1375 unsigned ctlr;
1376
1377 ctlr = EDMA_CTLR(channel);
1378 channel = EDMA_CHAN_SLOT(channel);
1379
1380 if (channel < edma_cc[ctlr]->num_channels) {
1381 int j = (channel >> 5);
1382 unsigned int mask = BIT(channel & 0x1f);
1383
1384 pr_debug("EDMA: EMR%d %08x\n", j,
1385 edma_read_array(ctlr, EDMA_EMR, j));
1386 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1387 /* Clear the corresponding EMR bits */
1388 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1389 /* Clear any SER */
1390 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1391 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1392 }
1393 }
1394 EXPORT_SYMBOL(edma_clean_channel);
1395
1396 /*
1397 * edma_clear_event - clear an outstanding event on the DMA channel
1398 * Arguments:
1399 * channel - channel number
1400 */
1401 void edma_clear_event(unsigned channel)
1402 {
1403 unsigned ctlr;
1404
1405 ctlr = EDMA_CTLR(channel);
1406 channel = EDMA_CHAN_SLOT(channel);
1407
1408 if (channel >= edma_cc[ctlr]->num_channels)
1409 return;
1410 if (channel < 32)
1411 edma_write(ctlr, EDMA_ECR, BIT(channel));
1412 else
1413 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
1414 }
1415 EXPORT_SYMBOL(edma_clear_event);
1416
1417 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1418 struct edma *edma_cc)
1419 {
1420 int i;
1421 u32 value, cccfg;
1422 s8 (*queue_priority_map)[2];
1423
1424 /* Decode the eDMA3 configuration from CCCFG register */
1425 cccfg = edma_read(0, EDMA_CCCFG);
1426
1427 value = GET_NUM_REGN(cccfg);
1428 edma_cc->num_region = BIT(value);
1429
1430 value = GET_NUM_DMACH(cccfg);
1431 edma_cc->num_channels = BIT(value + 1);
1432
1433 value = GET_NUM_PAENTRY(cccfg);
1434 edma_cc->num_slots = BIT(value + 4);
1435
1436 value = GET_NUM_EVQUE(cccfg);
1437 edma_cc->num_tc = value + 1;
1438
1439 dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
1440 dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
1441 dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
1442 dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
1443 dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
1444
1445 /* Nothing need to be done if queue priority is provided */
1446 if (pdata->queue_priority_mapping)
1447 return 0;
1448
1449 /*
1450 * Configure TC/queue priority as follows:
1451 * Q0 - priority 0
1452 * Q1 - priority 1
1453 * Q2 - priority 2
1454 * ...
1455 * The meaning of priority numbers: 0 highest priority, 7 lowest
1456 * priority. So Q0 is the highest priority queue and the last queue has
1457 * the lowest priority.
1458 */
1459 queue_priority_map = devm_kzalloc(dev,
1460 (edma_cc->num_tc + 1) * sizeof(s8),
1461 GFP_KERNEL);
1462 if (!queue_priority_map)
1463 return -ENOMEM;
1464
1465 for (i = 0; i < edma_cc->num_tc; i++) {
1466 queue_priority_map[i][0] = i;
1467 queue_priority_map[i][1] = i;
1468 }
1469 queue_priority_map[i][0] = -1;
1470 queue_priority_map[i][1] = -1;
1471
1472 pdata->queue_priority_mapping = queue_priority_map;
1473 pdata->default_queue = 0;
1474
1475 return 0;
1476 }
1477
1478 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1479
1480 static int edma_of_read_u32_to_s16_array(const struct device_node *np,
1481 const char *propname, s16 *out_values,
1482 size_t sz)
1483 {
1484 int ret;
1485
1486 ret = of_property_read_u16_array(np, propname, out_values, sz);
1487 if (ret)
1488 return ret;
1489
1490 /* Terminate it */
1491 *out_values++ = -1;
1492 *out_values++ = -1;
1493
1494 return 0;
1495 }
1496
1497 static int edma_xbar_event_map(struct device *dev,
1498 struct device_node *node,
1499 struct edma_soc_info *pdata, int len)
1500 {
1501 int ret, i;
1502 struct resource res;
1503 void __iomem *xbar;
1504 const s16 (*xbar_chans)[2];
1505 u32 shift, offset, mux;
1506
1507 xbar_chans = devm_kzalloc(dev,
1508 len/sizeof(s16) + 2*sizeof(s16),
1509 GFP_KERNEL);
1510 if (!xbar_chans)
1511 return -ENOMEM;
1512
1513 ret = of_address_to_resource(node, 1, &res);
1514 if (ret)
1515 return -EIO;
1516
1517 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1518 if (!xbar)
1519 return -ENOMEM;
1520
1521 ret = edma_of_read_u32_to_s16_array(node,
1522 "ti,edma-xbar-event-map",
1523 (s16 *)xbar_chans,
1524 len/sizeof(u32));
1525 if (ret)
1526 return -EIO;
1527
1528 for (i = 0; xbar_chans[i][0] != -1; i++) {
1529 shift = (xbar_chans[i][1] & 0x03) << 3;
1530 offset = xbar_chans[i][1] & 0xfffffffc;
1531 mux = readl(xbar + offset);
1532 mux &= ~(0xff << shift);
1533 mux |= xbar_chans[i][0] << shift;
1534 writel(mux, (xbar + offset));
1535 }
1536
1537 pdata->xbar_chans = xbar_chans;
1538
1539 return 0;
1540 }
1541
1542 static int edma_of_parse_dt(struct device *dev,
1543 struct device_node *node,
1544 struct edma_soc_info *pdata)
1545 {
1546 int ret = 0;
1547 struct property *prop;
1548 size_t sz;
1549 struct edma_rsv_info *rsv_info;
1550
1551 rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
1552 if (!rsv_info)
1553 return -ENOMEM;
1554 pdata->rsv = rsv_info;
1555
1556 prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
1557 if (prop)
1558 ret = edma_xbar_event_map(dev, node, pdata, sz);
1559
1560 return ret;
1561 }
1562
1563 static struct of_dma_filter_info edma_filter_info = {
1564 .filter_fn = edma_filter_fn,
1565 };
1566
1567 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1568 struct device_node *node)
1569 {
1570 struct edma_soc_info *info;
1571 int ret;
1572
1573 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1574 if (!info)
1575 return ERR_PTR(-ENOMEM);
1576
1577 ret = edma_of_parse_dt(dev, node, info);
1578 if (ret)
1579 return ERR_PTR(ret);
1580
1581 dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
1582 dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
1583 of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
1584 &edma_filter_info);
1585
1586 return info;
1587 }
1588 #else
1589 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1590 struct device_node *node)
1591 {
1592 return ERR_PTR(-ENOSYS);
1593 }
1594 #endif
1595
1596 static int edma_probe(struct platform_device *pdev)
1597 {
1598 struct edma_soc_info **info = pdev->dev.platform_data;
1599 struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
1600 s8 (*queue_priority_mapping)[2];
1601 int i, j, off, ln, found = 0;
1602 int status = -1;
1603 const s16 (*rsv_chans)[2];
1604 const s16 (*rsv_slots)[2];
1605 const s16 (*xbar_chans)[2];
1606 int irq[EDMA_MAX_CC] = {0, 0};
1607 int err_irq[EDMA_MAX_CC] = {0, 0};
1608 struct resource *r[EDMA_MAX_CC] = {NULL};
1609 struct resource res[EDMA_MAX_CC];
1610 char res_name[10];
1611 struct device_node *node = pdev->dev.of_node;
1612 struct device *dev = &pdev->dev;
1613 int ret;
1614
1615 if (node) {
1616 /* Check if this is a second instance registered */
1617 if (arch_num_cc) {
1618 dev_err(dev, "only one EDMA instance is supported via DT\n");
1619 return -ENODEV;
1620 }
1621
1622 ninfo[0] = edma_setup_info_from_dt(dev, node);
1623 if (IS_ERR(ninfo[0])) {
1624 dev_err(dev, "failed to get DT data\n");
1625 return PTR_ERR(ninfo[0]);
1626 }
1627
1628 info = ninfo;
1629 }
1630
1631 if (!info)
1632 return -ENODEV;
1633
1634 pm_runtime_enable(dev);
1635 ret = pm_runtime_get_sync(dev);
1636 if (ret < 0) {
1637 dev_err(dev, "pm_runtime_get_sync() failed\n");
1638 return ret;
1639 }
1640
1641 for (j = 0; j < EDMA_MAX_CC; j++) {
1642 if (!info[j]) {
1643 if (!found)
1644 return -ENODEV;
1645 break;
1646 }
1647 if (node) {
1648 ret = of_address_to_resource(node, j, &res[j]);
1649 if (!ret)
1650 r[j] = &res[j];
1651 } else {
1652 sprintf(res_name, "edma_cc%d", j);
1653 r[j] = platform_get_resource_byname(pdev,
1654 IORESOURCE_MEM,
1655 res_name);
1656 }
1657 if (!r[j]) {
1658 if (found)
1659 break;
1660 else
1661 return -ENODEV;
1662 } else {
1663 found = 1;
1664 }
1665
1666 edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
1667 if (IS_ERR(edmacc_regs_base[j]))
1668 return PTR_ERR(edmacc_regs_base[j]);
1669
1670 edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
1671 GFP_KERNEL);
1672 if (!edma_cc[j])
1673 return -ENOMEM;
1674
1675 /* Get eDMA3 configuration from IP */
1676 ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
1677 if (ret)
1678 return ret;
1679
1680 edma_cc[j]->default_queue = info[j]->default_queue;
1681
1682 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1683 edmacc_regs_base[j]);
1684
1685 for (i = 0; i < edma_cc[j]->num_slots; i++)
1686 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1687 &dummy_paramset, PARM_SIZE);
1688
1689 /* Mark all channels as unused */
1690 memset(edma_cc[j]->edma_unused, 0xff,
1691 sizeof(edma_cc[j]->edma_unused));
1692
1693 if (info[j]->rsv) {
1694
1695 /* Clear the reserved channels in unused list */
1696 rsv_chans = info[j]->rsv->rsv_chans;
1697 if (rsv_chans) {
1698 for (i = 0; rsv_chans[i][0] != -1; i++) {
1699 off = rsv_chans[i][0];
1700 ln = rsv_chans[i][1];
1701 clear_bits(off, ln,
1702 edma_cc[j]->edma_unused);
1703 }
1704 }
1705
1706 /* Set the reserved slots in inuse list */
1707 rsv_slots = info[j]->rsv->rsv_slots;
1708 if (rsv_slots) {
1709 for (i = 0; rsv_slots[i][0] != -1; i++) {
1710 off = rsv_slots[i][0];
1711 ln = rsv_slots[i][1];
1712 set_bits(off, ln,
1713 edma_cc[j]->edma_inuse);
1714 }
1715 }
1716 }
1717
1718 /* Clear the xbar mapped channels in unused list */
1719 xbar_chans = info[j]->xbar_chans;
1720 if (xbar_chans) {
1721 for (i = 0; xbar_chans[i][1] != -1; i++) {
1722 off = xbar_chans[i][1];
1723 clear_bits(off, 1,
1724 edma_cc[j]->edma_unused);
1725 }
1726 }
1727
1728 if (node) {
1729 irq[j] = irq_of_parse_and_map(node, 0);
1730 err_irq[j] = irq_of_parse_and_map(node, 2);
1731 } else {
1732 char irq_name[10];
1733
1734 sprintf(irq_name, "edma%d", j);
1735 irq[j] = platform_get_irq_byname(pdev, irq_name);
1736
1737 sprintf(irq_name, "edma%d_err", j);
1738 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1739 }
1740 edma_cc[j]->irq_res_start = irq[j];
1741 edma_cc[j]->irq_res_end = err_irq[j];
1742
1743 status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
1744 "edma", dev);
1745 if (status < 0) {
1746 dev_dbg(&pdev->dev,
1747 "devm_request_irq %d failed --> %d\n",
1748 irq[j], status);
1749 return status;
1750 }
1751
1752 status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
1753 "edma_error", dev);
1754 if (status < 0) {
1755 dev_dbg(&pdev->dev,
1756 "devm_request_irq %d failed --> %d\n",
1757 err_irq[j], status);
1758 return status;
1759 }
1760
1761 for (i = 0; i < edma_cc[j]->num_channels; i++)
1762 map_dmach_queue(j, i, info[j]->default_queue);
1763
1764 queue_priority_mapping = info[j]->queue_priority_mapping;
1765
1766 /* Event queue priority mapping */
1767 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1768 assign_priority_to_queue(j,
1769 queue_priority_mapping[i][0],
1770 queue_priority_mapping[i][1]);
1771
1772 /* Map the channel to param entry if channel mapping logic
1773 * exist
1774 */
1775 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1776 map_dmach_param(j);
1777
1778 for (i = 0; i < edma_cc[j]->num_region; i++) {
1779 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1780 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1781 edma_write_array(j, EDMA_QRAE, i, 0x0);
1782 }
1783 arch_num_cc++;
1784 }
1785
1786 return 0;
1787 }
1788
1789 static struct platform_driver edma_driver = {
1790 .driver = {
1791 .name = "edma",
1792 .of_match_table = edma_of_ids,
1793 },
1794 .probe = edma_probe,
1795 };
1796
1797 static int __init edma_init(void)
1798 {
1799 return platform_driver_probe(&edma_driver, edma_probe);
1800 }
1801 arch_initcall(edma_init);
1802
Linux kernel - Deliverables
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