2 * linux/arch/arm/common/gic.c
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Interrupt architecture for the GIC:
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/export.h>
28 #include <linux/list.h>
29 #include <linux/smp.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
33 #include <linux/irqdomain.h>
34 #include <linux/interrupt.h>
35 #include <linux/percpu.h>
36 #include <linux/slab.h>
39 #include <asm/mach/irq.h>
40 #include <asm/hardware/gic.h>
42 static DEFINE_SPINLOCK(irq_controller_lock
);
44 /* Address of GIC 0 CPU interface */
45 void __iomem
*gic_cpu_base_addr __read_mostly
;
48 * Supported arch specific GIC irq extension.
49 * Default make them NULL.
51 struct irq_chip gic_arch_extn
= {
55 .irq_retrigger
= NULL
,
64 static struct gic_chip_data gic_data
[MAX_GIC_NR
] __read_mostly
;
66 static inline void __iomem
*gic_dist_base(struct irq_data
*d
)
68 struct gic_chip_data
*gic_data
= irq_data_get_irq_chip_data(d
);
69 return gic_data
->dist_base
;
72 static inline void __iomem
*gic_cpu_base(struct irq_data
*d
)
74 struct gic_chip_data
*gic_data
= irq_data_get_irq_chip_data(d
);
75 return gic_data
->cpu_base
;
78 static inline unsigned int gic_irq(struct irq_data
*d
)
84 * Routines to acknowledge, disable and enable interrupts
86 static void gic_mask_irq(struct irq_data
*d
)
88 u32 mask
= 1 << (gic_irq(d
) % 32);
90 spin_lock(&irq_controller_lock
);
91 writel_relaxed(mask
, gic_dist_base(d
) + GIC_DIST_ENABLE_CLEAR
+ (gic_irq(d
) / 32) * 4);
92 if (gic_arch_extn
.irq_mask
)
93 gic_arch_extn
.irq_mask(d
);
94 spin_unlock(&irq_controller_lock
);
97 static void gic_unmask_irq(struct irq_data
*d
)
99 u32 mask
= 1 << (gic_irq(d
) % 32);
101 spin_lock(&irq_controller_lock
);
102 if (gic_arch_extn
.irq_unmask
)
103 gic_arch_extn
.irq_unmask(d
);
104 writel_relaxed(mask
, gic_dist_base(d
) + GIC_DIST_ENABLE_SET
+ (gic_irq(d
) / 32) * 4);
105 spin_unlock(&irq_controller_lock
);
108 static void gic_eoi_irq(struct irq_data
*d
)
110 if (gic_arch_extn
.irq_eoi
) {
111 spin_lock(&irq_controller_lock
);
112 gic_arch_extn
.irq_eoi(d
);
113 spin_unlock(&irq_controller_lock
);
116 writel_relaxed(gic_irq(d
), gic_cpu_base(d
) + GIC_CPU_EOI
);
119 static int gic_set_type(struct irq_data
*d
, unsigned int type
)
121 void __iomem
*base
= gic_dist_base(d
);
122 unsigned int gicirq
= gic_irq(d
);
123 u32 enablemask
= 1 << (gicirq
% 32);
124 u32 enableoff
= (gicirq
/ 32) * 4;
125 u32 confmask
= 0x2 << ((gicirq
% 16) * 2);
126 u32 confoff
= (gicirq
/ 16) * 4;
127 bool enabled
= false;
130 /* Interrupt configuration for SGIs can't be changed */
134 if (type
!= IRQ_TYPE_LEVEL_HIGH
&& type
!= IRQ_TYPE_EDGE_RISING
)
137 spin_lock(&irq_controller_lock
);
139 if (gic_arch_extn
.irq_set_type
)
140 gic_arch_extn
.irq_set_type(d
, type
);
142 val
= readl_relaxed(base
+ GIC_DIST_CONFIG
+ confoff
);
143 if (type
== IRQ_TYPE_LEVEL_HIGH
)
145 else if (type
== IRQ_TYPE_EDGE_RISING
)
149 * As recommended by the spec, disable the interrupt before changing
152 if (readl_relaxed(base
+ GIC_DIST_ENABLE_SET
+ enableoff
) & enablemask
) {
153 writel_relaxed(enablemask
, base
+ GIC_DIST_ENABLE_CLEAR
+ enableoff
);
157 writel_relaxed(val
, base
+ GIC_DIST_CONFIG
+ confoff
);
160 writel_relaxed(enablemask
, base
+ GIC_DIST_ENABLE_SET
+ enableoff
);
162 spin_unlock(&irq_controller_lock
);
167 static int gic_retrigger(struct irq_data
*d
)
169 if (gic_arch_extn
.irq_retrigger
)
170 return gic_arch_extn
.irq_retrigger(d
);
176 static int gic_set_affinity(struct irq_data
*d
, const struct cpumask
*mask_val
,
179 void __iomem
*reg
= gic_dist_base(d
) + GIC_DIST_TARGET
+ (gic_irq(d
) & ~3);
180 unsigned int shift
= (gic_irq(d
) % 4) * 8;
181 unsigned int cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
184 if (cpu
>= 8 || cpu
>= nr_cpu_ids
)
187 mask
= 0xff << shift
;
188 bit
= 1 << (cpu_logical_map(cpu
) + shift
);
190 spin_lock(&irq_controller_lock
);
191 val
= readl_relaxed(reg
) & ~mask
;
192 writel_relaxed(val
| bit
, reg
);
193 spin_unlock(&irq_controller_lock
);
195 return IRQ_SET_MASK_OK
;
200 static int gic_set_wake(struct irq_data
*d
, unsigned int on
)
204 if (gic_arch_extn
.irq_set_wake
)
205 ret
= gic_arch_extn
.irq_set_wake(d
, on
);
211 #define gic_set_wake NULL
214 static void gic_handle_cascade_irq(unsigned int irq
, struct irq_desc
*desc
)
216 struct gic_chip_data
*chip_data
= irq_get_handler_data(irq
);
217 struct irq_chip
*chip
= irq_get_chip(irq
);
218 unsigned int cascade_irq
, gic_irq
;
219 unsigned long status
;
221 chained_irq_enter(chip
, desc
);
223 spin_lock(&irq_controller_lock
);
224 status
= readl_relaxed(chip_data
->cpu_base
+ GIC_CPU_INTACK
);
225 spin_unlock(&irq_controller_lock
);
227 gic_irq
= (status
& 0x3ff);
231 cascade_irq
= irq_domain_to_irq(&chip_data
->domain
, gic_irq
);
232 if (unlikely(gic_irq
< 32 || gic_irq
> 1020 || cascade_irq
>= NR_IRQS
))
233 do_bad_IRQ(cascade_irq
, desc
);
235 generic_handle_irq(cascade_irq
);
238 chained_irq_exit(chip
, desc
);
241 static struct irq_chip gic_chip
= {
243 .irq_mask
= gic_mask_irq
,
244 .irq_unmask
= gic_unmask_irq
,
245 .irq_eoi
= gic_eoi_irq
,
246 .irq_set_type
= gic_set_type
,
247 .irq_retrigger
= gic_retrigger
,
249 .irq_set_affinity
= gic_set_affinity
,
251 .irq_set_wake
= gic_set_wake
,
254 void __init
gic_cascade_irq(unsigned int gic_nr
, unsigned int irq
)
256 if (gic_nr
>= MAX_GIC_NR
)
258 if (irq_set_handler_data(irq
, &gic_data
[gic_nr
]) != 0)
260 irq_set_chained_handler(irq
, gic_handle_cascade_irq
);
263 static void __init
gic_dist_init(struct gic_chip_data
*gic
)
267 unsigned int gic_irqs
= gic
->gic_irqs
;
268 struct irq_domain
*domain
= &gic
->domain
;
269 void __iomem
*base
= gic
->dist_base
;
273 cpu
= cpu_logical_map(smp_processor_id());
277 cpumask
|= cpumask
<< 8;
278 cpumask
|= cpumask
<< 16;
280 writel_relaxed(0, base
+ GIC_DIST_CTRL
);
283 * Set all global interrupts to be level triggered, active low.
285 for (i
= 32; i
< gic_irqs
; i
+= 16)
286 writel_relaxed(0, base
+ GIC_DIST_CONFIG
+ i
* 4 / 16);
289 * Set all global interrupts to this CPU only.
291 for (i
= 32; i
< gic_irqs
; i
+= 4)
292 writel_relaxed(cpumask
, base
+ GIC_DIST_TARGET
+ i
* 4 / 4);
295 * Set priority on all global interrupts.
297 for (i
= 32; i
< gic_irqs
; i
+= 4)
298 writel_relaxed(0xa0a0a0a0, base
+ GIC_DIST_PRI
+ i
* 4 / 4);
301 * Disable all interrupts. Leave the PPI and SGIs alone
302 * as these enables are banked registers.
304 for (i
= 32; i
< gic_irqs
; i
+= 32)
305 writel_relaxed(0xffffffff, base
+ GIC_DIST_ENABLE_CLEAR
+ i
* 4 / 32);
308 * Setup the Linux IRQ subsystem.
310 irq_domain_for_each_irq(domain
, i
, irq
) {
312 irq_set_percpu_devid(irq
);
313 irq_set_chip_and_handler(irq
, &gic_chip
,
314 handle_percpu_devid_irq
);
315 set_irq_flags(irq
, IRQF_VALID
| IRQF_NOAUTOEN
);
317 irq_set_chip_and_handler(irq
, &gic_chip
,
319 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
321 irq_set_chip_data(irq
, gic
);
324 writel_relaxed(1, base
+ GIC_DIST_CTRL
);
327 static void __cpuinit
gic_cpu_init(struct gic_chip_data
*gic
)
329 void __iomem
*dist_base
= gic
->dist_base
;
330 void __iomem
*base
= gic
->cpu_base
;
334 * Deal with the banked PPI and SGI interrupts - disable all
335 * PPI interrupts, ensure all SGI interrupts are enabled.
337 writel_relaxed(0xffff0000, dist_base
+ GIC_DIST_ENABLE_CLEAR
);
338 writel_relaxed(0x0000ffff, dist_base
+ GIC_DIST_ENABLE_SET
);
341 * Set priority on PPI and SGI interrupts
343 for (i
= 0; i
< 32; i
+= 4)
344 writel_relaxed(0xa0a0a0a0, dist_base
+ GIC_DIST_PRI
+ i
* 4 / 4);
346 writel_relaxed(0xf0, base
+ GIC_CPU_PRIMASK
);
347 writel_relaxed(1, base
+ GIC_CPU_CTRL
);
352 * Saves the GIC distributor registers during suspend or idle. Must be called
353 * with interrupts disabled but before powering down the GIC. After calling
354 * this function, no interrupts will be delivered by the GIC, and another
355 * platform-specific wakeup source must be enabled.
357 static void gic_dist_save(unsigned int gic_nr
)
359 unsigned int gic_irqs
;
360 void __iomem
*dist_base
;
363 if (gic_nr
>= MAX_GIC_NR
)
366 gic_irqs
= gic_data
[gic_nr
].gic_irqs
;
367 dist_base
= gic_data
[gic_nr
].dist_base
;
372 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 16); i
++)
373 gic_data
[gic_nr
].saved_spi_conf
[i
] =
374 readl_relaxed(dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
376 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++)
377 gic_data
[gic_nr
].saved_spi_target
[i
] =
378 readl_relaxed(dist_base
+ GIC_DIST_TARGET
+ i
* 4);
380 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 32); i
++)
381 gic_data
[gic_nr
].saved_spi_enable
[i
] =
382 readl_relaxed(dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
386 * Restores the GIC distributor registers during resume or when coming out of
387 * idle. Must be called before enabling interrupts. If a level interrupt
388 * that occured while the GIC was suspended is still present, it will be
389 * handled normally, but any edge interrupts that occured will not be seen by
390 * the GIC and need to be handled by the platform-specific wakeup source.
392 static void gic_dist_restore(unsigned int gic_nr
)
394 unsigned int gic_irqs
;
396 void __iomem
*dist_base
;
398 if (gic_nr
>= MAX_GIC_NR
)
401 gic_irqs
= gic_data
[gic_nr
].gic_irqs
;
402 dist_base
= gic_data
[gic_nr
].dist_base
;
407 writel_relaxed(0, dist_base
+ GIC_DIST_CTRL
);
409 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 16); i
++)
410 writel_relaxed(gic_data
[gic_nr
].saved_spi_conf
[i
],
411 dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
413 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++)
414 writel_relaxed(0xa0a0a0a0,
415 dist_base
+ GIC_DIST_PRI
+ i
* 4);
417 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++)
418 writel_relaxed(gic_data
[gic_nr
].saved_spi_target
[i
],
419 dist_base
+ GIC_DIST_TARGET
+ i
* 4);
421 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 32); i
++)
422 writel_relaxed(gic_data
[gic_nr
].saved_spi_enable
[i
],
423 dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
425 writel_relaxed(1, dist_base
+ GIC_DIST_CTRL
);
428 static void gic_cpu_save(unsigned int gic_nr
)
432 void __iomem
*dist_base
;
433 void __iomem
*cpu_base
;
435 if (gic_nr
>= MAX_GIC_NR
)
438 dist_base
= gic_data
[gic_nr
].dist_base
;
439 cpu_base
= gic_data
[gic_nr
].cpu_base
;
441 if (!dist_base
|| !cpu_base
)
444 ptr
= __this_cpu_ptr(gic_data
[gic_nr
].saved_ppi_enable
);
445 for (i
= 0; i
< DIV_ROUND_UP(32, 32); i
++)
446 ptr
[i
] = readl_relaxed(dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
448 ptr
= __this_cpu_ptr(gic_data
[gic_nr
].saved_ppi_conf
);
449 for (i
= 0; i
< DIV_ROUND_UP(32, 16); i
++)
450 ptr
[i
] = readl_relaxed(dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
454 static void gic_cpu_restore(unsigned int gic_nr
)
458 void __iomem
*dist_base
;
459 void __iomem
*cpu_base
;
461 if (gic_nr
>= MAX_GIC_NR
)
464 dist_base
= gic_data
[gic_nr
].dist_base
;
465 cpu_base
= gic_data
[gic_nr
].cpu_base
;
467 if (!dist_base
|| !cpu_base
)
470 ptr
= __this_cpu_ptr(gic_data
[gic_nr
].saved_ppi_enable
);
471 for (i
= 0; i
< DIV_ROUND_UP(32, 32); i
++)
472 writel_relaxed(ptr
[i
], dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
474 ptr
= __this_cpu_ptr(gic_data
[gic_nr
].saved_ppi_conf
);
475 for (i
= 0; i
< DIV_ROUND_UP(32, 16); i
++)
476 writel_relaxed(ptr
[i
], dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
478 for (i
= 0; i
< DIV_ROUND_UP(32, 4); i
++)
479 writel_relaxed(0xa0a0a0a0, dist_base
+ GIC_DIST_PRI
+ i
* 4);
481 writel_relaxed(0xf0, cpu_base
+ GIC_CPU_PRIMASK
);
482 writel_relaxed(1, cpu_base
+ GIC_CPU_CTRL
);
485 static int gic_notifier(struct notifier_block
*self
, unsigned long cmd
, void *v
)
489 for (i
= 0; i
< MAX_GIC_NR
; i
++) {
494 case CPU_PM_ENTER_FAILED
:
498 case CPU_CLUSTER_PM_ENTER
:
501 case CPU_CLUSTER_PM_ENTER_FAILED
:
502 case CPU_CLUSTER_PM_EXIT
:
511 static struct notifier_block gic_notifier_block
= {
512 .notifier_call
= gic_notifier
,
515 static void __init
gic_pm_init(struct gic_chip_data
*gic
)
517 gic
->saved_ppi_enable
= __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
519 BUG_ON(!gic
->saved_ppi_enable
);
521 gic
->saved_ppi_conf
= __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
523 BUG_ON(!gic
->saved_ppi_conf
);
525 cpu_pm_register_notifier(&gic_notifier_block
);
528 static void __init
gic_pm_init(struct gic_chip_data
*gic
)
533 const struct irq_domain_ops gic_irq_domain_ops
= {
536 void __init
gic_init(unsigned int gic_nr
, unsigned int irq_start
,
537 void __iomem
*dist_base
, void __iomem
*cpu_base
)
539 struct gic_chip_data
*gic
;
540 struct irq_domain
*domain
;
543 BUG_ON(gic_nr
>= MAX_GIC_NR
);
545 gic
= &gic_data
[gic_nr
];
546 domain
= &gic
->domain
;
547 gic
->dist_base
= dist_base
;
548 gic
->cpu_base
= cpu_base
;
551 * For primary GICs, skip over SGIs.
552 * For secondary GICs, skip over PPIs, too.
555 gic_cpu_base_addr
= cpu_base
;
556 domain
->hwirq_base
= 16;
557 irq_start
= (irq_start
& ~31) + 16;
559 domain
->hwirq_base
= 32;
562 * Find out how many interrupts are supported.
563 * The GIC only supports up to 1020 interrupt sources.
565 gic_irqs
= readl_relaxed(dist_base
+ GIC_DIST_CTR
) & 0x1f;
566 gic_irqs
= (gic_irqs
+ 1) * 32;
569 gic
->gic_irqs
= gic_irqs
;
571 domain
->nr_irq
= gic_irqs
- domain
->hwirq_base
;
572 domain
->irq_base
= irq_alloc_descs(-1, irq_start
, domain
->nr_irq
,
575 domain
->ops
= &gic_irq_domain_ops
;
576 irq_domain_add(domain
);
578 gic_chip
.flags
|= gic_arch_extn
.flags
;
584 void __cpuinit
gic_secondary_init(unsigned int gic_nr
)
586 BUG_ON(gic_nr
>= MAX_GIC_NR
);
588 gic_cpu_init(&gic_data
[gic_nr
]);
592 void gic_raise_softirq(const struct cpumask
*mask
, unsigned int irq
)
595 unsigned long map
= 0;
597 /* Convert our logical CPU mask into a physical one. */
598 for_each_cpu(cpu
, mask
)
599 map
|= 1 << cpu_logical_map(cpu
);
602 * Ensure that stores to Normal memory are visible to the
603 * other CPUs before issuing the IPI.
607 /* this always happens on GIC0 */
608 writel_relaxed(map
<< 16 | irq
, gic_data
[0].dist_base
+ GIC_DIST_SOFTINT
);