2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
17 #error "Only include this from assembly code"
20 #include <asm/ptrace.h>
23 * Endian independent macros for shifting bytes within registers.
28 #define get_byte_0 lsl #0
29 #define get_byte_1 lsr #8
30 #define get_byte_2 lsr #16
31 #define get_byte_3 lsr #24
32 #define put_byte_0 lsl #0
33 #define put_byte_1 lsl #8
34 #define put_byte_2 lsl #16
35 #define put_byte_3 lsl #24
39 #define get_byte_0 lsr #24
40 #define get_byte_1 lsr #16
41 #define get_byte_2 lsr #8
42 #define get_byte_3 lsl #0
43 #define put_byte_0 lsl #24
44 #define put_byte_1 lsl #16
45 #define put_byte_2 lsl #8
46 #define put_byte_3 lsl #0
50 * Data preload for architectures that support it
52 #if __LINUX_ARM_ARCH__ >= 5
53 #define PLD(code...) code
59 * This can be used to enable code to cacheline align the destination
60 * pointer when bulk writing to memory. Experiments on StrongARM and
61 * XScale didn't show this a worthwhile thing to do when the cache is not
62 * set to write-allocate (this would need further testing on XScale when WA
65 * On Feroceon there is much to gain however, regardless of cache mode.
67 #ifdef CONFIG_CPU_FEROCEON
68 #define CALGN(code...) code
70 #define CALGN(code...)
74 * Enable and disable interrupts
76 #if __LINUX_ARM_ARCH__ >= 6
86 msr cpsr_c
, #PSR_I_BIT | SVC_MODE
95 * Save the current IRQ state and disable IRQs. Note that this macro
96 * assumes FIQs are enabled, and that the processor is in SVC mode.
98 .macro save_and_disable_irqs
, oldcpsr
104 * Restore interrupt state previously stored in a register. We don't
105 * guarantee that this will preserve the flags.
107 .macro restore_irqs
, oldcpsr
113 .section __ex_table,"a"; \
119 * SMP data memory barrier
123 #if __LINUX_ARM_ARCH__ >= 7
125 #elif __LINUX_ARM_ARCH__ == 6
126 mcr p15
, 0, r0
, c7
, c10
, 5 @ dmb
131 #ifdef CONFIG_THUMB2_KERNEL
132 .macro setmode
, mode
, reg
137 .macro setmode
, mode
, reg
143 * STRT/LDRT access macros with ARM and Thumb-2 variants
145 #ifdef CONFIG_THUMB2_KERNEL
147 .macro usraccoff
, instr
, reg
, ptr
, inc
, off
, cond
, abort
150 \instr\cond\
()bt
\reg
, [\ptr
, #\off]
152 \instr\cond\
()t
\reg
, [\ptr
, #\off]
154 .error
"Unsupported inc macro argument"
157 .section __ex_table
,"a"
163 .macro usracc
, instr
, reg
, ptr
, inc
, cond
, rept
, abort
164 @
explicit IT instruction needed because of the label
165 @ introduced by the USER macro
172 .error
"Unsupported rept macro argument"
176 @ Slightly optimised to avoid incrementing the pointer twice
177 usraccoff \instr
, \reg
, \ptr
, \inc
, 0, \cond
, \abort
179 usraccoff \instr
, \reg
, \ptr
, \inc
, 4, \cond
, \abort
182 add\cond \ptr
, #\rept * \inc
185 #else /* !CONFIG_THUMB2_KERNEL */
187 .macro usracc
, instr
, reg
, ptr
, inc
, cond
, rept
, abort
191 \instr\cond\
()bt
\reg
, [\ptr
], #\inc
193 \instr\cond\
()t
\reg
, [\ptr
], #\inc
195 .error
"Unsupported inc macro argument"
198 .section __ex_table
,"a"
205 #endif /* CONFIG_THUMB2_KERNEL */
207 .macro strusr
, reg
, ptr
, inc
, cond
=al
, rept
=1, abort
=9001f
208 usracc str
, \reg
, \ptr
, \inc
, \cond
, \rept
, \abort
211 .macro ldrusr
, reg
, ptr
, inc
, cond
=al
, rept
=1, abort
=9001f
212 usracc ldr
, \reg
, \ptr
, \inc
, \cond
, \rept
, \abort