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arm: Provide atomic_{or,xor,and}
[deliverable/linux.git] / arch / arm / include / asm / atomic.h
1 /*
2 * arch/arm/include/asm/atomic.h
3 *
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #ifndef __ASM_ARM_ATOMIC_H
12 #define __ASM_ARM_ATOMIC_H
13
14 #include <linux/compiler.h>
15 #include <linux/prefetch.h>
16 #include <linux/types.h>
17 #include <linux/irqflags.h>
18 #include <asm/barrier.h>
19 #include <asm/cmpxchg.h>
20
21 #define ATOMIC_INIT(i) { (i) }
22
23 #ifdef __KERNEL__
24
25 /*
26 * On ARM, ordinary assignment (str instruction) doesn't clear the local
27 * strex/ldrex monitor on some implementations. The reason we can use it for
28 * atomic_set() is the clrex or dummy strex done on every exception return.
29 */
30 #define atomic_read(v) ACCESS_ONCE((v)->counter)
31 #define atomic_set(v,i) (((v)->counter) = (i))
32
33 #if __LINUX_ARM_ARCH__ >= 6
34
35 /*
36 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
37 * store exclusive to ensure that these are atomic. We may loop
38 * to ensure that the update happens.
39 */
40
41 #define ATOMIC_OP(op, c_op, asm_op) \
42 static inline void atomic_##op(int i, atomic_t *v) \
43 { \
44 unsigned long tmp; \
45 int result; \
46 \
47 prefetchw(&v->counter); \
48 __asm__ __volatile__("@ atomic_" #op "\n" \
49 "1: ldrex %0, [%3]\n" \
50 " " #asm_op " %0, %0, %4\n" \
51 " strex %1, %0, [%3]\n" \
52 " teq %1, #0\n" \
53 " bne 1b" \
54 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
55 : "r" (&v->counter), "Ir" (i) \
56 : "cc"); \
57 } \
58
59 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
60 static inline int atomic_##op##_return(int i, atomic_t *v) \
61 { \
62 unsigned long tmp; \
63 int result; \
64 \
65 smp_mb(); \
66 prefetchw(&v->counter); \
67 \
68 __asm__ __volatile__("@ atomic_" #op "_return\n" \
69 "1: ldrex %0, [%3]\n" \
70 " " #asm_op " %0, %0, %4\n" \
71 " strex %1, %0, [%3]\n" \
72 " teq %1, #0\n" \
73 " bne 1b" \
74 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
75 : "r" (&v->counter), "Ir" (i) \
76 : "cc"); \
77 \
78 smp_mb(); \
79 \
80 return result; \
81 }
82
83 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
84 {
85 int oldval;
86 unsigned long res;
87
88 smp_mb();
89 prefetchw(&ptr->counter);
90
91 do {
92 __asm__ __volatile__("@ atomic_cmpxchg\n"
93 "ldrex %1, [%3]\n"
94 "mov %0, #0\n"
95 "teq %1, %4\n"
96 "strexeq %0, %5, [%3]\n"
97 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
98 : "r" (&ptr->counter), "Ir" (old), "r" (new)
99 : "cc");
100 } while (res);
101
102 smp_mb();
103
104 return oldval;
105 }
106
107 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
108 {
109 int oldval, newval;
110 unsigned long tmp;
111
112 smp_mb();
113 prefetchw(&v->counter);
114
115 __asm__ __volatile__ ("@ atomic_add_unless\n"
116 "1: ldrex %0, [%4]\n"
117 " teq %0, %5\n"
118 " beq 2f\n"
119 " add %1, %0, %6\n"
120 " strex %2, %1, [%4]\n"
121 " teq %2, #0\n"
122 " bne 1b\n"
123 "2:"
124 : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
125 : "r" (&v->counter), "r" (u), "r" (a)
126 : "cc");
127
128 if (oldval != u)
129 smp_mb();
130
131 return oldval;
132 }
133
134 #else /* ARM_ARCH_6 */
135
136 #ifdef CONFIG_SMP
137 #error SMP not supported on pre-ARMv6 CPUs
138 #endif
139
140 #define ATOMIC_OP(op, c_op, asm_op) \
141 static inline void atomic_##op(int i, atomic_t *v) \
142 { \
143 unsigned long flags; \
144 \
145 raw_local_irq_save(flags); \
146 v->counter c_op i; \
147 raw_local_irq_restore(flags); \
148 } \
149
150 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
151 static inline int atomic_##op##_return(int i, atomic_t *v) \
152 { \
153 unsigned long flags; \
154 int val; \
155 \
156 raw_local_irq_save(flags); \
157 v->counter c_op i; \
158 val = v->counter; \
159 raw_local_irq_restore(flags); \
160 \
161 return val; \
162 }
163
164 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
165 {
166 int ret;
167 unsigned long flags;
168
169 raw_local_irq_save(flags);
170 ret = v->counter;
171 if (likely(ret == old))
172 v->counter = new;
173 raw_local_irq_restore(flags);
174
175 return ret;
176 }
177
178 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
179 {
180 int c, old;
181
182 c = atomic_read(v);
183 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
184 c = old;
185 return c;
186 }
187
188 #endif /* __LINUX_ARM_ARCH__ */
189
190 #define ATOMIC_OPS(op, c_op, asm_op) \
191 ATOMIC_OP(op, c_op, asm_op) \
192 ATOMIC_OP_RETURN(op, c_op, asm_op)
193
194 ATOMIC_OPS(add, +=, add)
195 ATOMIC_OPS(sub, -=, sub)
196
197 #define CONFIG_ARCH_HAS_ATOMIC_OR
198 #define atomic_andnot atomic_andnot
199
200 ATOMIC_OP(and, &=, and)
201 ATOMIC_OP(andnot, &= ~, bic)
202 ATOMIC_OP(or, |=, orr)
203 ATOMIC_OP(xor, ^=, eor)
204
205 #undef ATOMIC_OPS
206 #undef ATOMIC_OP_RETURN
207 #undef ATOMIC_OP
208
209 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
210
211 #define atomic_inc(v) atomic_add(1, v)
212 #define atomic_dec(v) atomic_sub(1, v)
213
214 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
215 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
216 #define atomic_inc_return(v) (atomic_add_return(1, v))
217 #define atomic_dec_return(v) (atomic_sub_return(1, v))
218 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
219
220 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
221
222 #ifndef CONFIG_GENERIC_ATOMIC64
223 typedef struct {
224 long long counter;
225 } atomic64_t;
226
227 #define ATOMIC64_INIT(i) { (i) }
228
229 #ifdef CONFIG_ARM_LPAE
230 static inline long long atomic64_read(const atomic64_t *v)
231 {
232 long long result;
233
234 __asm__ __volatile__("@ atomic64_read\n"
235 " ldrd %0, %H0, [%1]"
236 : "=&r" (result)
237 : "r" (&v->counter), "Qo" (v->counter)
238 );
239
240 return result;
241 }
242
243 static inline void atomic64_set(atomic64_t *v, long long i)
244 {
245 __asm__ __volatile__("@ atomic64_set\n"
246 " strd %2, %H2, [%1]"
247 : "=Qo" (v->counter)
248 : "r" (&v->counter), "r" (i)
249 );
250 }
251 #else
252 static inline long long atomic64_read(const atomic64_t *v)
253 {
254 long long result;
255
256 __asm__ __volatile__("@ atomic64_read\n"
257 " ldrexd %0, %H0, [%1]"
258 : "=&r" (result)
259 : "r" (&v->counter), "Qo" (v->counter)
260 );
261
262 return result;
263 }
264
265 static inline void atomic64_set(atomic64_t *v, long long i)
266 {
267 long long tmp;
268
269 prefetchw(&v->counter);
270 __asm__ __volatile__("@ atomic64_set\n"
271 "1: ldrexd %0, %H0, [%2]\n"
272 " strexd %0, %3, %H3, [%2]\n"
273 " teq %0, #0\n"
274 " bne 1b"
275 : "=&r" (tmp), "=Qo" (v->counter)
276 : "r" (&v->counter), "r" (i)
277 : "cc");
278 }
279 #endif
280
281 #define ATOMIC64_OP(op, op1, op2) \
282 static inline void atomic64_##op(long long i, atomic64_t *v) \
283 { \
284 long long result; \
285 unsigned long tmp; \
286 \
287 prefetchw(&v->counter); \
288 __asm__ __volatile__("@ atomic64_" #op "\n" \
289 "1: ldrexd %0, %H0, [%3]\n" \
290 " " #op1 " %Q0, %Q0, %Q4\n" \
291 " " #op2 " %R0, %R0, %R4\n" \
292 " strexd %1, %0, %H0, [%3]\n" \
293 " teq %1, #0\n" \
294 " bne 1b" \
295 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
296 : "r" (&v->counter), "r" (i) \
297 : "cc"); \
298 } \
299
300 #define ATOMIC64_OP_RETURN(op, op1, op2) \
301 static inline long long atomic64_##op##_return(long long i, atomic64_t *v) \
302 { \
303 long long result; \
304 unsigned long tmp; \
305 \
306 smp_mb(); \
307 prefetchw(&v->counter); \
308 \
309 __asm__ __volatile__("@ atomic64_" #op "_return\n" \
310 "1: ldrexd %0, %H0, [%3]\n" \
311 " " #op1 " %Q0, %Q0, %Q4\n" \
312 " " #op2 " %R0, %R0, %R4\n" \
313 " strexd %1, %0, %H0, [%3]\n" \
314 " teq %1, #0\n" \
315 " bne 1b" \
316 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
317 : "r" (&v->counter), "r" (i) \
318 : "cc"); \
319 \
320 smp_mb(); \
321 \
322 return result; \
323 }
324
325 #define ATOMIC64_OPS(op, op1, op2) \
326 ATOMIC64_OP(op, op1, op2) \
327 ATOMIC64_OP_RETURN(op, op1, op2)
328
329 ATOMIC64_OPS(add, adds, adc)
330 ATOMIC64_OPS(sub, subs, sbc)
331
332 #define atomic64_andnot atomic64_andnot
333
334 ATOMIC64_OP(and, and, and)
335 ATOMIC64_OP(andnot, bic, bic)
336 ATOMIC64_OP(or, orr, orr)
337 ATOMIC64_OP(xor, eor, eor)
338
339 #undef ATOMIC64_OPS
340 #undef ATOMIC64_OP_RETURN
341 #undef ATOMIC64_OP
342
343 static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old,
344 long long new)
345 {
346 long long oldval;
347 unsigned long res;
348
349 smp_mb();
350 prefetchw(&ptr->counter);
351
352 do {
353 __asm__ __volatile__("@ atomic64_cmpxchg\n"
354 "ldrexd %1, %H1, [%3]\n"
355 "mov %0, #0\n"
356 "teq %1, %4\n"
357 "teqeq %H1, %H4\n"
358 "strexdeq %0, %5, %H5, [%3]"
359 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
360 : "r" (&ptr->counter), "r" (old), "r" (new)
361 : "cc");
362 } while (res);
363
364 smp_mb();
365
366 return oldval;
367 }
368
369 static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
370 {
371 long long result;
372 unsigned long tmp;
373
374 smp_mb();
375 prefetchw(&ptr->counter);
376
377 __asm__ __volatile__("@ atomic64_xchg\n"
378 "1: ldrexd %0, %H0, [%3]\n"
379 " strexd %1, %4, %H4, [%3]\n"
380 " teq %1, #0\n"
381 " bne 1b"
382 : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
383 : "r" (&ptr->counter), "r" (new)
384 : "cc");
385
386 smp_mb();
387
388 return result;
389 }
390
391 static inline long long atomic64_dec_if_positive(atomic64_t *v)
392 {
393 long long result;
394 unsigned long tmp;
395
396 smp_mb();
397 prefetchw(&v->counter);
398
399 __asm__ __volatile__("@ atomic64_dec_if_positive\n"
400 "1: ldrexd %0, %H0, [%3]\n"
401 " subs %Q0, %Q0, #1\n"
402 " sbc %R0, %R0, #0\n"
403 " teq %R0, #0\n"
404 " bmi 2f\n"
405 " strexd %1, %0, %H0, [%3]\n"
406 " teq %1, #0\n"
407 " bne 1b\n"
408 "2:"
409 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
410 : "r" (&v->counter)
411 : "cc");
412
413 smp_mb();
414
415 return result;
416 }
417
418 static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
419 {
420 long long val;
421 unsigned long tmp;
422 int ret = 1;
423
424 smp_mb();
425 prefetchw(&v->counter);
426
427 __asm__ __volatile__("@ atomic64_add_unless\n"
428 "1: ldrexd %0, %H0, [%4]\n"
429 " teq %0, %5\n"
430 " teqeq %H0, %H5\n"
431 " moveq %1, #0\n"
432 " beq 2f\n"
433 " adds %Q0, %Q0, %Q6\n"
434 " adc %R0, %R0, %R6\n"
435 " strexd %2, %0, %H0, [%4]\n"
436 " teq %2, #0\n"
437 " bne 1b\n"
438 "2:"
439 : "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
440 : "r" (&v->counter), "r" (u), "r" (a)
441 : "cc");
442
443 if (ret)
444 smp_mb();
445
446 return ret;
447 }
448
449 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
450 #define atomic64_inc(v) atomic64_add(1LL, (v))
451 #define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
452 #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
453 #define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
454 #define atomic64_dec(v) atomic64_sub(1LL, (v))
455 #define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
456 #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
457 #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
458
459 #endif /* !CONFIG_GENERIC_ATOMIC64 */
460 #endif
461 #endif
Linux kernel - Deliverables
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