arch/arm/include/debug/msm.S

   1 /*
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
   5  * Author: Brian Swetland <swetland@google.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18         .macro  addruart, rp, rv, tmp
  19         ldr     \rp, =CONFIG_DEBUG_UART_PHYS
  20         ldr     \rv, =CONFIG_DEBUG_UART_VIRT
  21         .endm
  22
  23         .macro  senduart, rd, rx
  24 ARM_BE8(rev     \rd, \rd )
  25         @ Write the 1 character to UARTDM_TF
  26         str     \rd, [\rx, #0x70]
  27         .endm
  28
  29         .macro  waituart, rd, rx
  30         @ check for TX_EMT in UARTDM_SR
  31         ldr     \rd, [\rx, #0x08]
  32 ARM_BE8(rev     \rd, \rd )
  33         tst     \rd, #0x08
  34         bne     1002f
  35         @ wait for TXREADY in UARTDM_ISR
  36 1001:   ldr     \rd, [\rx, #0x14]
  37 ARM_BE8(rev     \rd, \rd )
  38         tst     \rd, #0x80
  39         beq     1001b
  40 1002:
  41         @ Clear TX_READY by writing to the UARTDM_CR register
  42         mov     \rd, #0x300
  43 ARM_BE8(rev     \rd, \rd )
  44         str     \rd, [\rx, #0x10]
  45         @ Write 0x1 to NCF register
  46         mov     \rd, #0x1
  47 ARM_BE8(rev     \rd, \rd )
  48         str     \rd, [\rx, #0x40]
  49         @ UARTDM reg. Read to induce delay
  50         ldr     \rd, [\rx, #0x08]
  51         .endm
  52
  53         .macro  busyuart, rd, rx
  54         .endm