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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable
[deliverable/linux.git] / arch / arm / kernel / entry-armv.S
1 /*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
17
18 #include <asm/memory.h>
19 #include <asm/glue.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
24
25 #include "entry-header.S"
26
27 /*
28 * Interrupt handling. Preserves r7, r8, r9
29 */
30 .macro irq_handler
31 get_irqnr_preamble r5, lr
32 1: get_irqnr_and_base r0, r6, r5, lr
33 movne r1, sp
34 @
35 @ routine called with r0 = irq number, r1 = struct pt_regs *
36 @
37 adrne lr, BSYM(1b)
38 bne asm_do_IRQ
39
40 #ifdef CONFIG_SMP
41 /*
42 * XXX
43 *
44 * this macro assumes that irqstat (r6) and base (r5) are
45 * preserved from get_irqnr_and_base above
46 */
47 test_for_ipi r0, r6, r5, lr
48 movne r0, sp
49 adrne lr, BSYM(1b)
50 bne do_IPI
51
52 #ifdef CONFIG_LOCAL_TIMERS
53 test_for_ltirq r0, r6, r5, lr
54 movne r0, sp
55 adrne lr, BSYM(1b)
56 bne do_local_timer
57 #endif
58 #endif
59
60 .endm
61
62 #ifdef CONFIG_KPROBES
63 .section .kprobes.text,"ax",%progbits
64 #else
65 .text
66 #endif
67
68 /*
69 * Invalid mode handlers
70 */
71 .macro inv_entry, reason
72 sub sp, sp, #S_FRAME_SIZE
73 ARM( stmib sp, {r1 - lr} )
74 THUMB( stmia sp, {r0 - r12} )
75 THUMB( str sp, [sp, #S_SP] )
76 THUMB( str lr, [sp, #S_LR] )
77 mov r1, #\reason
78 .endm
79
80 __pabt_invalid:
81 inv_entry BAD_PREFETCH
82 b common_invalid
83 ENDPROC(__pabt_invalid)
84
85 __dabt_invalid:
86 inv_entry BAD_DATA
87 b common_invalid
88 ENDPROC(__dabt_invalid)
89
90 __irq_invalid:
91 inv_entry BAD_IRQ
92 b common_invalid
93 ENDPROC(__irq_invalid)
94
95 __und_invalid:
96 inv_entry BAD_UNDEFINSTR
97
98 @
99 @ XXX fall through to common_invalid
100 @
101
102 @
103 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
104 @
105 common_invalid:
106 zero_fp
107
108 ldmia r0, {r4 - r6}
109 add r0, sp, #S_PC @ here for interlock avoidance
110 mov r7, #-1 @ "" "" "" ""
111 str r4, [sp] @ save preserved r0
112 stmia r0, {r5 - r7} @ lr_<exception>,
113 @ cpsr_<exception>, "old_r0"
114
115 mov r0, sp
116 b bad_mode
117 ENDPROC(__und_invalid)
118
119 /*
120 * SVC mode handlers
121 */
122
123 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
124 #define SPFIX(code...) code
125 #else
126 #define SPFIX(code...)
127 #endif
128
129 .macro svc_entry, stack_hole=0
130 UNWIND(.fnstart )
131 UNWIND(.save {r0 - pc} )
132 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
133 #ifdef CONFIG_THUMB2_KERNEL
134 SPFIX( str r0, [sp] ) @ temporarily saved
135 SPFIX( mov r0, sp )
136 SPFIX( tst r0, #4 ) @ test original stack alignment
137 SPFIX( ldr r0, [sp] ) @ restored
138 #else
139 SPFIX( tst sp, #4 )
140 #endif
141 SPFIX( subeq sp, sp, #4 )
142 stmia sp, {r1 - r12}
143
144 ldmia r0, {r1 - r3}
145 add r5, sp, #S_SP - 4 @ here for interlock avoidance
146 mov r4, #-1 @ "" "" "" ""
147 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
148 SPFIX( addeq r0, r0, #4 )
149 str r1, [sp, #-4]! @ save the "real" r0 copied
150 @ from the exception stack
151
152 mov r1, lr
153
154 @
155 @ We are now ready to fill in the remaining blanks on the stack:
156 @
157 @ r0 - sp_svc
158 @ r1 - lr_svc
159 @ r2 - lr_<exception>, already fixed up for correct return/restart
160 @ r3 - spsr_<exception>
161 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
162 @
163 stmia r5, {r0 - r4}
164 .endm
165
166 .align 5
167 __dabt_svc:
168 svc_entry
169
170 @
171 @ get ready to re-enable interrupts if appropriate
172 @
173 mrs r9, cpsr
174 tst r3, #PSR_I_BIT
175 biceq r9, r9, #PSR_I_BIT
176
177 @
178 @ Call the processor-specific abort handler:
179 @
180 @ r2 - aborted context pc
181 @ r3 - aborted context cpsr
182 @
183 @ The abort handler must return the aborted address in r0, and
184 @ the fault status register in r1. r9 must be preserved.
185 @
186 #ifdef MULTI_DABORT
187 ldr r4, .LCprocfns
188 mov lr, pc
189 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
190 #else
191 bl CPU_DABORT_HANDLER
192 #endif
193
194 @
195 @ set desired IRQ state, then call main handler
196 @
197 msr cpsr_c, r9
198 mov r2, sp
199 bl do_DataAbort
200
201 @
202 @ IRQs off again before pulling preserved data off the stack
203 @
204 disable_irq
205
206 @
207 @ restore SPSR and restart the instruction
208 @
209 ldr r2, [sp, #S_PSR]
210 svc_exit r2 @ return from exception
211 UNWIND(.fnend )
212 ENDPROC(__dabt_svc)
213
214 .align 5
215 __irq_svc:
216 svc_entry
217
218 #ifdef CONFIG_TRACE_IRQFLAGS
219 bl trace_hardirqs_off
220 #endif
221 #ifdef CONFIG_PREEMPT
222 get_thread_info tsk
223 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
224 add r7, r8, #1 @ increment it
225 str r7, [tsk, #TI_PREEMPT]
226 #endif
227
228 irq_handler
229 #ifdef CONFIG_PREEMPT
230 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
231 ldr r0, [tsk, #TI_FLAGS] @ get flags
232 teq r8, #0 @ if preempt count != 0
233 movne r0, #0 @ force flags to 0
234 tst r0, #_TIF_NEED_RESCHED
235 blne svc_preempt
236 #endif
237 ldr r4, [sp, #S_PSR] @ irqs are already disabled
238 #ifdef CONFIG_TRACE_IRQFLAGS
239 tst r4, #PSR_I_BIT
240 bleq trace_hardirqs_on
241 #endif
242 svc_exit r4 @ return from exception
243 UNWIND(.fnend )
244 ENDPROC(__irq_svc)
245
246 .ltorg
247
248 #ifdef CONFIG_PREEMPT
249 svc_preempt:
250 mov r8, lr
251 1: bl preempt_schedule_irq @ irq en/disable is done inside
252 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
253 tst r0, #_TIF_NEED_RESCHED
254 moveq pc, r8 @ go again
255 b 1b
256 #endif
257
258 .align 5
259 __und_svc:
260 #ifdef CONFIG_KPROBES
261 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
262 @ it obviously needs free stack space which then will belong to
263 @ the saved context.
264 svc_entry 64
265 #else
266 svc_entry
267 #endif
268
269 @
270 @ call emulation code, which returns using r9 if it has emulated
271 @ the instruction, or the more conventional lr if we are to treat
272 @ this as a real undefined instruction
273 @
274 @ r0 - instruction
275 @
276 ldr r0, [r2, #-4]
277 adr r9, BSYM(1f)
278 bl call_fpe
279
280 mov r0, sp @ struct pt_regs *regs
281 bl do_undefinstr
282
283 @
284 @ IRQs off again before pulling preserved data off the stack
285 @
286 1: disable_irq
287
288 @
289 @ restore SPSR and restart the instruction
290 @
291 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
292 svc_exit r2 @ return from exception
293 UNWIND(.fnend )
294 ENDPROC(__und_svc)
295
296 .align 5
297 __pabt_svc:
298 svc_entry
299
300 @
301 @ re-enable interrupts if appropriate
302 @
303 mrs r9, cpsr
304 tst r3, #PSR_I_BIT
305 biceq r9, r9, #PSR_I_BIT
306
307 @
308 @ set args, then call main handler
309 @
310 @ r0 - address of faulting instruction
311 @ r1 - pointer to registers on stack
312 @
313 #ifdef MULTI_PABORT
314 mov r0, r2 @ pass address of aborted instruction.
315 ldr r4, .LCprocfns
316 mov lr, pc
317 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
318 #else
319 CPU_PABORT_HANDLER(r0, r2)
320 #endif
321 msr cpsr_c, r9 @ Maybe enable interrupts
322 mov r1, sp @ regs
323 bl do_PrefetchAbort @ call abort handler
324
325 @
326 @ IRQs off again before pulling preserved data off the stack
327 @
328 disable_irq
329
330 @
331 @ restore SPSR and restart the instruction
332 @
333 ldr r2, [sp, #S_PSR]
334 svc_exit r2 @ return from exception
335 UNWIND(.fnend )
336 ENDPROC(__pabt_svc)
337
338 .align 5
339 .LCcralign:
340 .word cr_alignment
341 #ifdef MULTI_DABORT
342 .LCprocfns:
343 .word processor
344 #endif
345 .LCfp:
346 .word fp_enter
347
348 /*
349 * User mode handlers
350 *
351 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
352 */
353
354 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
355 #error "sizeof(struct pt_regs) must be a multiple of 8"
356 #endif
357
358 .macro usr_entry
359 UNWIND(.fnstart )
360 UNWIND(.cantunwind ) @ don't unwind the user space
361 sub sp, sp, #S_FRAME_SIZE
362 ARM( stmib sp, {r1 - r12} )
363 THUMB( stmia sp, {r0 - r12} )
364
365 ldmia r0, {r1 - r3}
366 add r0, sp, #S_PC @ here for interlock avoidance
367 mov r4, #-1 @ "" "" "" ""
368
369 str r1, [sp] @ save the "real" r0 copied
370 @ from the exception stack
371
372 @
373 @ We are now ready to fill in the remaining blanks on the stack:
374 @
375 @ r2 - lr_<exception>, already fixed up for correct return/restart
376 @ r3 - spsr_<exception>
377 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
378 @
379 @ Also, separately save sp_usr and lr_usr
380 @
381 stmia r0, {r2 - r4}
382 ARM( stmdb r0, {sp, lr}^ )
383 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
384
385 @
386 @ Enable the alignment trap while in kernel mode
387 @
388 alignment_trap r0
389
390 @
391 @ Clear FP to mark the first stack frame
392 @
393 zero_fp
394 .endm
395
396 .macro kuser_cmpxchg_check
397 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
398 #ifndef CONFIG_MMU
399 #warning "NPTL on non MMU needs fixing"
400 #else
401 @ Make sure our user space atomic helper is restarted
402 @ if it was interrupted in a critical region. Here we
403 @ perform a quick test inline since it should be false
404 @ 99.9999% of the time. The rest is done out of line.
405 cmp r2, #TASK_SIZE
406 blhs kuser_cmpxchg_fixup
407 #endif
408 #endif
409 .endm
410
411 .align 5
412 __dabt_usr:
413 usr_entry
414 kuser_cmpxchg_check
415
416 @
417 @ Call the processor-specific abort handler:
418 @
419 @ r2 - aborted context pc
420 @ r3 - aborted context cpsr
421 @
422 @ The abort handler must return the aborted address in r0, and
423 @ the fault status register in r1.
424 @
425 #ifdef MULTI_DABORT
426 ldr r4, .LCprocfns
427 mov lr, pc
428 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
429 #else
430 bl CPU_DABORT_HANDLER
431 #endif
432
433 @
434 @ IRQs on, then call the main handler
435 @
436 enable_irq
437 mov r2, sp
438 adr lr, BSYM(ret_from_exception)
439 b do_DataAbort
440 UNWIND(.fnend )
441 ENDPROC(__dabt_usr)
442
443 .align 5
444 __irq_usr:
445 usr_entry
446 kuser_cmpxchg_check
447
448 #ifdef CONFIG_TRACE_IRQFLAGS
449 bl trace_hardirqs_off
450 #endif
451 get_thread_info tsk
452 #ifdef CONFIG_PREEMPT
453 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
454 add r7, r8, #1 @ increment it
455 str r7, [tsk, #TI_PREEMPT]
456 #endif
457
458 irq_handler
459 #ifdef CONFIG_PREEMPT
460 ldr r0, [tsk, #TI_PREEMPT]
461 str r8, [tsk, #TI_PREEMPT]
462 teq r0, r7
463 ARM( strne r0, [r0, -r0] )
464 THUMB( movne r0, #0 )
465 THUMB( strne r0, [r0] )
466 #endif
467 #ifdef CONFIG_TRACE_IRQFLAGS
468 bl trace_hardirqs_on
469 #endif
470
471 mov why, #0
472 b ret_to_user
473 UNWIND(.fnend )
474 ENDPROC(__irq_usr)
475
476 .ltorg
477
478 .align 5
479 __und_usr:
480 usr_entry
481
482 @
483 @ fall through to the emulation code, which returns using r9 if
484 @ it has emulated the instruction, or the more conventional lr
485 @ if we are to treat this as a real undefined instruction
486 @
487 @ r0 - instruction
488 @
489 adr r9, BSYM(ret_from_exception)
490 adr lr, BSYM(__und_usr_unknown)
491 tst r3, #PSR_T_BIT @ Thumb mode?
492 itet eq @ explicit IT needed for the 1f label
493 subeq r4, r2, #4 @ ARM instr at LR - 4
494 subne r4, r2, #2 @ Thumb instr at LR - 2
495 1: ldreqt r0, [r4]
496 #ifdef CONFIG_CPU_ENDIAN_BE8
497 reveq r0, r0 @ little endian instruction
498 #endif
499 beq call_fpe
500 @ Thumb instruction
501 #if __LINUX_ARM_ARCH__ >= 7
502 2:
503 ARM( ldrht r5, [r4], #2 )
504 THUMB( ldrht r5, [r4] )
505 THUMB( add r4, r4, #2 )
506 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
507 cmp r0, #0xe800 @ 32bit instruction if xx != 0
508 blo __und_usr_unknown
509 3: ldrht r0, [r4]
510 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
511 orr r0, r0, r5, lsl #16
512 #else
513 b __und_usr_unknown
514 #endif
515 UNWIND(.fnend )
516 ENDPROC(__und_usr)
517
518 @
519 @ fallthrough to call_fpe
520 @
521
522 /*
523 * The out of line fixup for the ldrt above.
524 */
525 .section .fixup, "ax"
526 4: mov pc, r9
527 .previous
528 .section __ex_table,"a"
529 .long 1b, 4b
530 #if __LINUX_ARM_ARCH__ >= 7
531 .long 2b, 4b
532 .long 3b, 4b
533 #endif
534 .previous
535
536 /*
537 * Check whether the instruction is a co-processor instruction.
538 * If yes, we need to call the relevant co-processor handler.
539 *
540 * Note that we don't do a full check here for the co-processor
541 * instructions; all instructions with bit 27 set are well
542 * defined. The only instructions that should fault are the
543 * co-processor instructions. However, we have to watch out
544 * for the ARM6/ARM7 SWI bug.
545 *
546 * NEON is a special case that has to be handled here. Not all
547 * NEON instructions are co-processor instructions, so we have
548 * to make a special case of checking for them. Plus, there's
549 * five groups of them, so we have a table of mask/opcode pairs
550 * to check against, and if any match then we branch off into the
551 * NEON handler code.
552 *
553 * Emulators may wish to make use of the following registers:
554 * r0 = instruction opcode.
555 * r2 = PC+4
556 * r9 = normal "successful" return address
557 * r10 = this threads thread_info structure.
558 * lr = unrecognised instruction return address
559 */
560 @
561 @ Fall-through from Thumb-2 __und_usr
562 @
563 #ifdef CONFIG_NEON
564 adr r6, .LCneon_thumb_opcodes
565 b 2f
566 #endif
567 call_fpe:
568 #ifdef CONFIG_NEON
569 adr r6, .LCneon_arm_opcodes
570 2:
571 ldr r7, [r6], #4 @ mask value
572 cmp r7, #0 @ end mask?
573 beq 1f
574 and r8, r0, r7
575 ldr r7, [r6], #4 @ opcode bits matching in mask
576 cmp r8, r7 @ NEON instruction?
577 bne 2b
578 get_thread_info r10
579 mov r7, #1
580 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
581 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
582 b do_vfp @ let VFP handler handle this
583 1:
584 #endif
585 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
586 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
587 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
588 and r8, r0, #0x0f000000 @ mask out op-code bits
589 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
590 #endif
591 moveq pc, lr
592 get_thread_info r10 @ get current thread
593 and r8, r0, #0x00000f00 @ mask out CP number
594 THUMB( lsr r8, r8, #8 )
595 mov r7, #1
596 add r6, r10, #TI_USED_CP
597 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
598 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
599 #ifdef CONFIG_IWMMXT
600 @ Test if we need to give access to iWMMXt coprocessors
601 ldr r5, [r10, #TI_FLAGS]
602 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
603 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
604 bcs iwmmxt_task_enable
605 #endif
606 ARM( add pc, pc, r8, lsr #6 )
607 THUMB( lsl r8, r8, #2 )
608 THUMB( add pc, r8 )
609 nop
610
611 W(mov) pc, lr @ CP#0
612 W(b) do_fpe @ CP#1 (FPE)
613 W(b) do_fpe @ CP#2 (FPE)
614 W(mov) pc, lr @ CP#3
615 #ifdef CONFIG_CRUNCH
616 b crunch_task_enable @ CP#4 (MaverickCrunch)
617 b crunch_task_enable @ CP#5 (MaverickCrunch)
618 b crunch_task_enable @ CP#6 (MaverickCrunch)
619 #else
620 W(mov) pc, lr @ CP#4
621 W(mov) pc, lr @ CP#5
622 W(mov) pc, lr @ CP#6
623 #endif
624 W(mov) pc, lr @ CP#7
625 W(mov) pc, lr @ CP#8
626 W(mov) pc, lr @ CP#9
627 #ifdef CONFIG_VFP
628 W(b) do_vfp @ CP#10 (VFP)
629 W(b) do_vfp @ CP#11 (VFP)
630 #else
631 W(mov) pc, lr @ CP#10 (VFP)
632 W(mov) pc, lr @ CP#11 (VFP)
633 #endif
634 W(mov) pc, lr @ CP#12
635 W(mov) pc, lr @ CP#13
636 W(mov) pc, lr @ CP#14 (Debug)
637 W(mov) pc, lr @ CP#15 (Control)
638
639 #ifdef CONFIG_NEON
640 .align 6
641
642 .LCneon_arm_opcodes:
643 .word 0xfe000000 @ mask
644 .word 0xf2000000 @ opcode
645
646 .word 0xff100000 @ mask
647 .word 0xf4000000 @ opcode
648
649 .word 0x00000000 @ mask
650 .word 0x00000000 @ opcode
651
652 .LCneon_thumb_opcodes:
653 .word 0xef000000 @ mask
654 .word 0xef000000 @ opcode
655
656 .word 0xff100000 @ mask
657 .word 0xf9000000 @ opcode
658
659 .word 0x00000000 @ mask
660 .word 0x00000000 @ opcode
661 #endif
662
663 do_fpe:
664 enable_irq
665 ldr r4, .LCfp
666 add r10, r10, #TI_FPSTATE @ r10 = workspace
667 ldr pc, [r4] @ Call FP module USR entry point
668
669 /*
670 * The FP module is called with these registers set:
671 * r0 = instruction
672 * r2 = PC+4
673 * r9 = normal "successful" return address
674 * r10 = FP workspace
675 * lr = unrecognised FP instruction return address
676 */
677
678 .data
679 ENTRY(fp_enter)
680 .word no_fp
681 .previous
682
683 no_fp: mov pc, lr
684
685 __und_usr_unknown:
686 enable_irq
687 mov r0, sp
688 adr lr, BSYM(ret_from_exception)
689 b do_undefinstr
690 ENDPROC(__und_usr_unknown)
691
692 .align 5
693 __pabt_usr:
694 usr_entry
695
696 #ifdef MULTI_PABORT
697 mov r0, r2 @ pass address of aborted instruction.
698 ldr r4, .LCprocfns
699 mov lr, pc
700 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
701 #else
702 CPU_PABORT_HANDLER(r0, r2)
703 #endif
704 enable_irq @ Enable interrupts
705 mov r1, sp @ regs
706 bl do_PrefetchAbort @ call abort handler
707 UNWIND(.fnend )
708 /* fall through */
709 /*
710 * This is the return code to user mode for abort handlers
711 */
712 ENTRY(ret_from_exception)
713 UNWIND(.fnstart )
714 UNWIND(.cantunwind )
715 get_thread_info tsk
716 mov why, #0
717 b ret_to_user
718 UNWIND(.fnend )
719 ENDPROC(__pabt_usr)
720 ENDPROC(ret_from_exception)
721
722 /*
723 * Register switch for ARMv3 and ARMv4 processors
724 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
725 * previous and next are guaranteed not to be the same.
726 */
727 ENTRY(__switch_to)
728 UNWIND(.fnstart )
729 UNWIND(.cantunwind )
730 add ip, r1, #TI_CPU_SAVE
731 ldr r3, [r2, #TI_TP_VALUE]
732 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
733 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
734 THUMB( str sp, [ip], #4 )
735 THUMB( str lr, [ip], #4 )
736 #ifdef CONFIG_MMU
737 ldr r6, [r2, #TI_CPU_DOMAIN]
738 #endif
739 #if __LINUX_ARM_ARCH__ >= 6
740 #ifdef CONFIG_CPU_32v6K
741 clrex
742 #else
743 strex r5, r4, [ip] @ Clear exclusive monitor
744 #endif
745 #endif
746 #if defined(CONFIG_HAS_TLS_REG)
747 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
748 #elif !defined(CONFIG_TLS_REG_EMUL)
749 mov r4, #0xffff0fff
750 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
751 #endif
752 #ifdef CONFIG_MMU
753 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
754 #endif
755 mov r5, r0
756 add r4, r2, #TI_CPU_SAVE
757 ldr r0, =thread_notify_head
758 mov r1, #THREAD_NOTIFY_SWITCH
759 bl atomic_notifier_call_chain
760 THUMB( mov ip, r4 )
761 mov r0, r5
762 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
763 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
764 THUMB( ldr sp, [ip], #4 )
765 THUMB( ldr pc, [ip] )
766 UNWIND(.fnend )
767 ENDPROC(__switch_to)
768
769 __INIT
770
771 /*
772 * User helpers.
773 *
774 * These are segment of kernel provided user code reachable from user space
775 * at a fixed address in kernel memory. This is used to provide user space
776 * with some operations which require kernel help because of unimplemented
777 * native feature and/or instructions in many ARM CPUs. The idea is for
778 * this code to be executed directly in user mode for best efficiency but
779 * which is too intimate with the kernel counter part to be left to user
780 * libraries. In fact this code might even differ from one CPU to another
781 * depending on the available instruction set and restrictions like on
782 * SMP systems. In other words, the kernel reserves the right to change
783 * this code as needed without warning. Only the entry points and their
784 * results are guaranteed to be stable.
785 *
786 * Each segment is 32-byte aligned and will be moved to the top of the high
787 * vector page. New segments (if ever needed) must be added in front of
788 * existing ones. This mechanism should be used only for things that are
789 * really small and justified, and not be abused freely.
790 *
791 * User space is expected to implement those things inline when optimizing
792 * for a processor that has the necessary native support, but only if such
793 * resulting binaries are already to be incompatible with earlier ARM
794 * processors due to the use of unsupported instructions other than what
795 * is provided here. In other words don't make binaries unable to run on
796 * earlier processors just for the sake of not using these kernel helpers
797 * if your compiled code is not going to use the new instructions for other
798 * purpose.
799 */
800 THUMB( .arm )
801
802 .macro usr_ret, reg
803 #ifdef CONFIG_ARM_THUMB
804 bx \reg
805 #else
806 mov pc, \reg
807 #endif
808 .endm
809
810 .align 5
811 .globl __kuser_helper_start
812 __kuser_helper_start:
813
814 /*
815 * Reference prototype:
816 *
817 * void __kernel_memory_barrier(void)
818 *
819 * Input:
820 *
821 * lr = return address
822 *
823 * Output:
824 *
825 * none
826 *
827 * Clobbered:
828 *
829 * none
830 *
831 * Definition and user space usage example:
832 *
833 * typedef void (__kernel_dmb_t)(void);
834 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
835 *
836 * Apply any needed memory barrier to preserve consistency with data modified
837 * manually and __kuser_cmpxchg usage.
838 *
839 * This could be used as follows:
840 *
841 * #define __kernel_dmb() \
842 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
843 * : : : "r0", "lr","cc" )
844 */
845
846 __kuser_memory_barrier: @ 0xffff0fa0
847 smp_dmb
848 usr_ret lr
849
850 .align 5
851
852 /*
853 * Reference prototype:
854 *
855 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
856 *
857 * Input:
858 *
859 * r0 = oldval
860 * r1 = newval
861 * r2 = ptr
862 * lr = return address
863 *
864 * Output:
865 *
866 * r0 = returned value (zero or non-zero)
867 * C flag = set if r0 == 0, clear if r0 != 0
868 *
869 * Clobbered:
870 *
871 * r3, ip, flags
872 *
873 * Definition and user space usage example:
874 *
875 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
876 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
877 *
878 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
879 * Return zero if *ptr was changed or non-zero if no exchange happened.
880 * The C flag is also set if *ptr was changed to allow for assembly
881 * optimization in the calling code.
882 *
883 * Notes:
884 *
885 * - This routine already includes memory barriers as needed.
886 *
887 * For example, a user space atomic_add implementation could look like this:
888 *
889 * #define atomic_add(ptr, val) \
890 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
891 * register unsigned int __result asm("r1"); \
892 * asm volatile ( \
893 * "1: @ atomic_add\n\t" \
894 * "ldr r0, [r2]\n\t" \
895 * "mov r3, #0xffff0fff\n\t" \
896 * "add lr, pc, #4\n\t" \
897 * "add r1, r0, %2\n\t" \
898 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
899 * "bcc 1b" \
900 * : "=&r" (__result) \
901 * : "r" (__ptr), "rIL" (val) \
902 * : "r0","r3","ip","lr","cc","memory" ); \
903 * __result; })
904 */
905
906 __kuser_cmpxchg: @ 0xffff0fc0
907
908 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
909
910 /*
911 * Poor you. No fast solution possible...
912 * The kernel itself must perform the operation.
913 * A special ghost syscall is used for that (see traps.c).
914 */
915 stmfd sp!, {r7, lr}
916 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
917 orr r7, r7, #0xf0
918 swi #0x9ffff0
919 ldmfd sp!, {r7, pc}
920
921 #elif __LINUX_ARM_ARCH__ < 6
922
923 #ifdef CONFIG_MMU
924
925 /*
926 * The only thing that can break atomicity in this cmpxchg
927 * implementation is either an IRQ or a data abort exception
928 * causing another process/thread to be scheduled in the middle
929 * of the critical sequence. To prevent this, code is added to
930 * the IRQ and data abort exception handlers to set the pc back
931 * to the beginning of the critical section if it is found to be
932 * within that critical section (see kuser_cmpxchg_fixup).
933 */
934 1: ldr r3, [r2] @ load current val
935 subs r3, r3, r0 @ compare with oldval
936 2: streq r1, [r2] @ store newval if eq
937 rsbs r0, r3, #0 @ set return val and C flag
938 usr_ret lr
939
940 .text
941 kuser_cmpxchg_fixup:
942 @ Called from kuser_cmpxchg_check macro.
943 @ r2 = address of interrupted insn (must be preserved).
944 @ sp = saved regs. r7 and r8 are clobbered.
945 @ 1b = first critical insn, 2b = last critical insn.
946 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
947 mov r7, #0xffff0fff
948 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
949 subs r8, r2, r7
950 rsbcss r8, r8, #(2b - 1b)
951 strcs r7, [sp, #S_PC]
952 mov pc, lr
953 .previous
954
955 #else
956 #warning "NPTL on non MMU needs fixing"
957 mov r0, #-1
958 adds r0, r0, #0
959 usr_ret lr
960 #endif
961
962 #else
963
964 #ifdef CONFIG_SMP
965 mcr p15, 0, r0, c7, c10, 5 @ dmb
966 #endif
967 1: ldrex r3, [r2]
968 subs r3, r3, r0
969 strexeq r3, r1, [r2]
970 teqeq r3, #1
971 beq 1b
972 rsbs r0, r3, #0
973 /* beware -- each __kuser slot must be 8 instructions max */
974 #ifdef CONFIG_SMP
975 b __kuser_memory_barrier
976 #else
977 usr_ret lr
978 #endif
979
980 #endif
981
982 .align 5
983
984 /*
985 * Reference prototype:
986 *
987 * int __kernel_get_tls(void)
988 *
989 * Input:
990 *
991 * lr = return address
992 *
993 * Output:
994 *
995 * r0 = TLS value
996 *
997 * Clobbered:
998 *
999 * none
1000 *
1001 * Definition and user space usage example:
1002 *
1003 * typedef int (__kernel_get_tls_t)(void);
1004 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
1005 *
1006 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
1007 *
1008 * This could be used as follows:
1009 *
1010 * #define __kernel_get_tls() \
1011 * ({ register unsigned int __val asm("r0"); \
1012 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
1013 * : "=r" (__val) : : "lr","cc" ); \
1014 * __val; })
1015 */
1016
1017 __kuser_get_tls: @ 0xffff0fe0
1018
1019 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
1020 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
1021 #else
1022 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
1023 #endif
1024 usr_ret lr
1025
1026 .rep 5
1027 .word 0 @ pad up to __kuser_helper_version
1028 .endr
1029
1030 /*
1031 * Reference declaration:
1032 *
1033 * extern unsigned int __kernel_helper_version;
1034 *
1035 * Definition and user space usage example:
1036 *
1037 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1038 *
1039 * User space may read this to determine the curent number of helpers
1040 * available.
1041 */
1042
1043 __kuser_helper_version: @ 0xffff0ffc
1044 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1045
1046 .globl __kuser_helper_end
1047 __kuser_helper_end:
1048
1049 THUMB( .thumb )
1050
1051 /*
1052 * Vector stubs.
1053 *
1054 * This code is copied to 0xffff0200 so we can use branches in the
1055 * vectors, rather than ldr's. Note that this code must not
1056 * exceed 0x300 bytes.
1057 *
1058 * Common stub entry macro:
1059 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1060 *
1061 * SP points to a minimal amount of processor-private memory, the address
1062 * of which is copied into r0 for the mode specific abort handler.
1063 */
1064 .macro vector_stub, name, mode, correction=0
1065 .align 5
1066
1067 vector_\name:
1068 .if \correction
1069 sub lr, lr, #\correction
1070 .endif
1071
1072 @
1073 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1074 @ (parent CPSR)
1075 @
1076 stmia sp, {r0, lr} @ save r0, lr
1077 mrs lr, spsr
1078 str lr, [sp, #8] @ save spsr
1079
1080 @
1081 @ Prepare for SVC32 mode. IRQs remain disabled.
1082 @
1083 mrs r0, cpsr
1084 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1085 msr spsr_cxsf, r0
1086
1087 @
1088 @ the branch table must immediately follow this code
1089 @
1090 and lr, lr, #0x0f
1091 THUMB( adr r0, 1f )
1092 THUMB( ldr lr, [r0, lr, lsl #2] )
1093 mov r0, sp
1094 ARM( ldr lr, [pc, lr, lsl #2] )
1095 movs pc, lr @ branch to handler in SVC mode
1096 ENDPROC(vector_\name)
1097
1098 .align 2
1099 @ handler addresses follow this label
1100 1:
1101 .endm
1102
1103 .globl __stubs_start
1104 __stubs_start:
1105 /*
1106 * Interrupt dispatcher
1107 */
1108 vector_stub irq, IRQ_MODE, 4
1109
1110 .long __irq_usr @ 0 (USR_26 / USR_32)
1111 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1112 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1113 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1114 .long __irq_invalid @ 4
1115 .long __irq_invalid @ 5
1116 .long __irq_invalid @ 6
1117 .long __irq_invalid @ 7
1118 .long __irq_invalid @ 8
1119 .long __irq_invalid @ 9
1120 .long __irq_invalid @ a
1121 .long __irq_invalid @ b
1122 .long __irq_invalid @ c
1123 .long __irq_invalid @ d
1124 .long __irq_invalid @ e
1125 .long __irq_invalid @ f
1126
1127 /*
1128 * Data abort dispatcher
1129 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1130 */
1131 vector_stub dabt, ABT_MODE, 8
1132
1133 .long __dabt_usr @ 0 (USR_26 / USR_32)
1134 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1135 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1136 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1137 .long __dabt_invalid @ 4
1138 .long __dabt_invalid @ 5
1139 .long __dabt_invalid @ 6
1140 .long __dabt_invalid @ 7
1141 .long __dabt_invalid @ 8
1142 .long __dabt_invalid @ 9
1143 .long __dabt_invalid @ a
1144 .long __dabt_invalid @ b
1145 .long __dabt_invalid @ c
1146 .long __dabt_invalid @ d
1147 .long __dabt_invalid @ e
1148 .long __dabt_invalid @ f
1149
1150 /*
1151 * Prefetch abort dispatcher
1152 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1153 */
1154 vector_stub pabt, ABT_MODE, 4
1155
1156 .long __pabt_usr @ 0 (USR_26 / USR_32)
1157 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1158 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1159 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1160 .long __pabt_invalid @ 4
1161 .long __pabt_invalid @ 5
1162 .long __pabt_invalid @ 6
1163 .long __pabt_invalid @ 7
1164 .long __pabt_invalid @ 8
1165 .long __pabt_invalid @ 9
1166 .long __pabt_invalid @ a
1167 .long __pabt_invalid @ b
1168 .long __pabt_invalid @ c
1169 .long __pabt_invalid @ d
1170 .long __pabt_invalid @ e
1171 .long __pabt_invalid @ f
1172
1173 /*
1174 * Undef instr entry dispatcher
1175 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1176 */
1177 vector_stub und, UND_MODE
1178
1179 .long __und_usr @ 0 (USR_26 / USR_32)
1180 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1181 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1182 .long __und_svc @ 3 (SVC_26 / SVC_32)
1183 .long __und_invalid @ 4
1184 .long __und_invalid @ 5
1185 .long __und_invalid @ 6
1186 .long __und_invalid @ 7
1187 .long __und_invalid @ 8
1188 .long __und_invalid @ 9
1189 .long __und_invalid @ a
1190 .long __und_invalid @ b
1191 .long __und_invalid @ c
1192 .long __und_invalid @ d
1193 .long __und_invalid @ e
1194 .long __und_invalid @ f
1195
1196 .align 5
1197
1198 /*=============================================================================
1199 * Undefined FIQs
1200 *-----------------------------------------------------------------------------
1201 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1202 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1203 * Basically to switch modes, we *HAVE* to clobber one register... brain
1204 * damage alert! I don't think that we can execute any code in here in any
1205 * other mode than FIQ... Ok you can switch to another mode, but you can't
1206 * get out of that mode without clobbering one register.
1207 */
1208 vector_fiq:
1209 disable_fiq
1210 subs pc, lr, #4
1211
1212 /*=============================================================================
1213 * Address exception handler
1214 *-----------------------------------------------------------------------------
1215 * These aren't too critical.
1216 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1217 */
1218
1219 vector_addrexcptn:
1220 b vector_addrexcptn
1221
1222 /*
1223 * We group all the following data together to optimise
1224 * for CPUs with separate I & D caches.
1225 */
1226 .align 5
1227
1228 .LCvswi:
1229 .word vector_swi
1230
1231 .globl __stubs_end
1232 __stubs_end:
1233
1234 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1235
1236 .globl __vectors_start
1237 __vectors_start:
1238 ARM( swi SYS_ERROR0 )
1239 THUMB( svc #0 )
1240 THUMB( nop )
1241 W(b) vector_und + stubs_offset
1242 W(ldr) pc, .LCvswi + stubs_offset
1243 W(b) vector_pabt + stubs_offset
1244 W(b) vector_dabt + stubs_offset
1245 W(b) vector_addrexcptn + stubs_offset
1246 W(b) vector_irq + stubs_offset
1247 W(b) vector_fiq + stubs_offset
1248
1249 .globl __vectors_end
1250 __vectors_end:
1251
1252 .data
1253
1254 .globl cr_alignment
1255 .globl cr_no_alignment
1256 cr_alignment:
1257 .space 4
1258 cr_no_alignment:
1259 .space 4
Linux kernel - Deliverables
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