arch/arm/kernel/head.S

   1 /*
   2  *  linux/arch/arm/kernel/head.S
   3  *
   4  *  Copyright (C) 1994-2002 Russell King
   5  *  Copyright (c) 2003 ARM Limited
   6  *  All Rights Reserved
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  *  Kernel startup code for all 32-bit CPUs
  13  */
  14 #include <linux/linkage.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/assembler.h>
  18 #include <asm/domain.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/asm-offsets.h>
  21 #include <asm/memory.h>
  22 #include <asm/thread_info.h>
  23 #include <asm/system.h>
  24
  25 #define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET)
  26
  27 /*
  28  * swapper_pg_dir is the virtual address of the initial page table.
  29  * We place the page tables 16K below KERNEL_RAM_ADDR.  Therefore, we must
  30  * make sure that KERNEL_RAM_ADDR is correctly set.  Currently, we expect
  31  * the least significant 16 bits to be 0x8000, but we could probably
  32  * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000.
  33  */
  34 #if (KERNEL_RAM_ADDR & 0xffff) != 0x8000
  35 #error KERNEL_RAM_ADDR must start at 0xXXXX8000
  36 #endif
  37
  38         .globl  swapper_pg_dir
  39         .equ    swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000
  40
  41         .macro  pgtbl, rd
  42         ldr     \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000))
  43         .endm
  44
  45 #ifdef CONFIG_XIP_KERNEL
  46 #define TEXTADDR  XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
  47 #else
  48 #define TEXTADDR  KERNEL_RAM_ADDR
  49 #endif
  50
  51 /*
  52  * Kernel startup entry point.
  53  * ---------------------------
  54  *
  55  * This is normally called from the decompressor code.  The requirements
  56  * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
  57  * r1 = machine nr.
  58  *
  59  * This code is mostly position independent, so if you link the kernel at
  60  * 0xc0008000, you call this at __pa(0xc0008000).
  61  *
  62  * See linux/arch/arm/tools/mach-types for the complete list of machine
  63  * numbers for r1.
  64  *
  65  * We're trying to keep crap to a minimum; DO NOT add any machine specific
  66  * crap here - that's what the boot loader (or in extreme, well justified
  67  * circumstances, zImage) is for.
  68  */
  69         __INIT
  70         .type   stext, %function
  71 ENTRY(stext)
  72         msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
  73                                                 @ and irqs disabled
  74         mrc     p15, 0, r9, c0, c0              @ get processor id
  75         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
  76         movs    r10, r5                         @ invalid processor (r5=0)?
  77         beq     __error_p                       @ yes, error 'p'
  78         bl      __lookup_machine_type           @ r5=machinfo
  79         movs    r8, r5                          @ invalid machine (r5=0)?
  80         beq     __error_a                       @ yes, error 'a'
  81         bl      __create_page_tables
  82
  83         /*
  84          * The following calls CPU specific code in a position independent
  85          * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
  86          * xxx_proc_info structure selected by __lookup_machine_type
  87          * above.  On return, the CPU will be ready for the MMU to be
  88          * turned on, and r0 will hold the CPU control register value.
  89          */
  90         ldr     r13, __switch_data              @ address to jump to after
  91                                                 @ mmu has been enabled
  92         adr     lr, __enable_mmu                @ return (PIC) address
  93         add     pc, r10, #PROCINFO_INITFUNC
  94
  95 #if defined(CONFIG_SMP)
  96         .type   secondary_startup, #function
  97 ENTRY(secondary_startup)
  98         /*
  99          * Common entry point for secondary CPUs.
 100          *
 101          * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
 102          * the processor type - there is no need to check the machine type
 103          * as it has already been validated by the primary processor.
 104          */
 105         msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
 106         mrc     p15, 0, r9, c0, c0              @ get processor id
 107         bl      __lookup_processor_type
 108         movs    r10, r5                         @ invalid processor?
 109         moveq   r0, #'p'                        @ yes, error 'p'
 110         beq     __error
 111
 112         /*
 113          * Use the page tables supplied from  __cpu_up.
 114          */
 115         adr     r4, __secondary_data
 116         ldmia   r4, {r5, r7, r13}               @ address to jump to after
 117         sub     r4, r4, r5                      @ mmu has been enabled
 118         ldr     r4, [r7, r4]                    @ get secondary_data.pgdir
 119         adr     lr, __enable_mmu                @ return address
 120         add     pc, r10, #PROCINFO_INITFUNC     @ initialise processor
 121                                                 @ (return control reg)
 122
 123         /*
 124          * r6  = &secondary_data
 125          */
 126 ENTRY(__secondary_switched)
 127         ldr     sp, [r7, #4]                    @ get secondary_data.stack
 128         mov     fp, #0
 129         b       secondary_start_kernel
 130
 131         .type   __secondary_data, %object
 132 __secondary_data:
 133         .long   .
 134         .long   secondary_data
 135         .long   __secondary_switched
 136 #endif /* defined(CONFIG_SMP) */
 137
 138
 139
 140 /*
 141  * Setup common bits before finally enabling the MMU.  Essentially
 142  * this is just loading the page table pointer and domain access
 143  * registers.
 144  */
 145         .type   __enable_mmu, %function
 146 __enable_mmu:
 147 #ifdef CONFIG_ALIGNMENT_TRAP
 148         orr     r0, r0, #CR_A
 149 #else
 150         bic     r0, r0, #CR_A
 151 #endif
 152 #ifdef CONFIG_CPU_DCACHE_DISABLE
 153         bic     r0, r0, #CR_C
 154 #endif
 155 #ifdef CONFIG_CPU_BPREDICT_DISABLE
 156         bic     r0, r0, #CR_Z
 157 #endif
 158 #ifdef CONFIG_CPU_ICACHE_DISABLE
 159         bic     r0, r0, #CR_I
 160 #endif
 161         mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
 162                       domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
 163                       domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
 164                       domain_val(DOMAIN_IO, DOMAIN_CLIENT))
 165         mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
 166         mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
 167         b       __turn_mmu_on
 168
 169 /*
 170  * Enable the MMU.  This completely changes the structure of the visible
 171  * memory space.  You will not be able to trace execution through this.
 172  * If you have an enquiry about this, *please* check the linux-arm-kernel
 173  * mailing list archives BEFORE sending another post to the list.
 174  *
 175  *  r0  = cp#15 control register
 176  *  r13 = *virtual* address to jump to upon completion
 177  *
 178  * other registers depend on the function called upon completion
 179  */
 180         .align  5
 181         .type   __turn_mmu_on, %function
 182 __turn_mmu_on:
 183         mov     r0, r0
 184         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 185         mrc     p15, 0, r3, c0, c0, 0           @ read id reg
 186         mov     r3, r3
 187         mov     r3, r3
 188         mov     pc, r13
 189
 190
 191
 192 /*
 193  * Setup the initial page tables.  We only setup the barest
 194  * amount which are required to get the kernel running, which
 195  * generally means mapping in the kernel code.
 196  *
 197  * r8  = machinfo
 198  * r9  = cpuid
 199  * r10 = procinfo
 200  *
 201  * Returns:
 202  *  r0, r3, r6, r7 corrupted
 203  *  r4 = physical page table address
 204  */
 205         .type   __create_page_tables, %function
 206 __create_page_tables:
 207         pgtbl   r4                              @ page table address
 208
 209         /*
 210          * Clear the 16K level 1 swapper page table
 211          */
 212         mov     r0, r4
 213         mov     r3, #0
 214         add     r6, r0, #0x4000
 215 1:      str     r3, [r0], #4
 216         str     r3, [r0], #4
 217         str     r3, [r0], #4
 218         str     r3, [r0], #4
 219         teq     r0, r6
 220         bne     1b
 221
 222         ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
 223
 224         /*
 225          * Create identity mapping for first MB of kernel to
 226          * cater for the MMU enable.  This identity mapping
 227          * will be removed by paging_init().  We use our current program
 228          * counter to determine corresponding section base address.
 229          */
 230         mov     r6, pc, lsr #20                 @ start of kernel section
 231         orr     r3, r7, r6, lsl #20             @ flags + kernel base
 232         str     r3, [r4, r6, lsl #2]            @ identity mapping
 233
 234         /*
 235          * Now setup the pagetables for our kernel direct
 236          * mapped region.
 237          */
 238         add     r0, r4,  #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
 239         str     r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
 240
 241         ldr     r6, =(_end - PAGE_OFFSET - 1)   @ r6 = number of sections
 242         mov     r6, r6, lsr #20                 @ needed for kernel minus 1
 243
 244 1:      add     r3, r3, #1 << 20
 245         str     r3, [r0, #4]!
 246         subs    r6, r6, #1
 247         bgt     1b
 248
 249         /*
 250          * Then map first 1MB of ram in case it contains our boot params.
 251          */
 252         add     r0, r4, #PAGE_OFFSET >> 18
 253         orr     r6, r7, #PHYS_OFFSET
 254         str     r6, [r0]
 255
 256 #ifdef CONFIG_XIP_KERNEL
 257         /*
 258          * Map some ram to cover our .data and .bss areas.
 259          * Mapping 3MB should be plenty.
 260          */
 261         sub     r3, r4, #PHYS_OFFSET
 262         mov     r3, r3, lsr #20
 263         add     r0, r0, r3, lsl #2
 264         add     r6, r6, r3, lsl #20
 265         str     r6, [r0], #4
 266         add     r6, r6, #(1 << 20)
 267         str     r6, [r0], #4
 268         add     r6, r6, #(1 << 20)
 269         str     r6, [r0]
 270 #endif
 271
 272 #ifdef CONFIG_DEBUG_LL
 273         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 274         /*
 275          * Map in IO space for serial debugging.
 276          * This allows debug messages to be output
 277          * via a serial console before paging_init.
 278          */
 279         ldr     r3, [r8, #MACHINFO_PGOFFIO]
 280         add     r0, r4, r3
 281         rsb     r3, r3, #0x4000                 @ PTRS_PER_PGD*sizeof(long)
 282         cmp     r3, #0x0800                     @ limit to 512MB
 283         movhi   r3, #0x0800
 284         add     r6, r0, r3
 285         ldr     r3, [r8, #MACHINFO_PHYSIO]
 286         orr     r3, r3, r7
 287 1:      str     r3, [r0], #4
 288         add     r3, r3, #1 << 20
 289         teq     r0, r6
 290         bne     1b
 291 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
 292         /*
 293          * If we're using the NetWinder or CATS, we also need to map
 294          * in the 16550-type serial port for the debug messages
 295          */
 296         add     r0, r4, #0xff000000 >> 18
 297         orr     r3, r7, #0x7c000000
 298         str     r3, [r0]
 299 #endif
 300 #ifdef CONFIG_ARCH_RPC
 301         /*
 302          * Map in screen at 0x02000000 & SCREEN2_BASE
 303          * Similar reasons here - for debug.  This is
 304          * only for Acorn RiscPC architectures.
 305          */
 306         add     r0, r4, #0x02000000 >> 18
 307         orr     r3, r7, #0x02000000
 308         str     r3, [r0]
 309         add     r0, r4, #0xd8000000 >> 18
 310         str     r3, [r0]
 311 #endif
 312 #endif
 313         mov     pc, lr
 314         .ltorg
 315
 316 #include "head-common.S"