arch/arm/kernel/head.S

   1 /*
   2  *  linux/arch/arm/kernel/head.S
   3  *
   4  *  Copyright (C) 1994-2002 Russell King
   5  *  Copyright (c) 2003 ARM Limited
   6  *  All Rights Reserved
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  *  Kernel startup code for all 32-bit CPUs
  13  */
  14 #include <linux/linkage.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/assembler.h>
  18 #include <asm/cp15.h>
  19 #include <asm/domain.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/asm-offsets.h>
  22 #include <asm/memory.h>
  23 #include <asm/thread_info.h>
  24 #include <asm/pgtable.h>
  25
  26 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
  27 #include CONFIG_DEBUG_LL_INCLUDE
  28 #endif
  29
  30 /*
  31  * swapper_pg_dir is the virtual address of the initial page table.
  32  * We place the page tables 16K below KERNEL_RAM_VADDR.  Therefore, we must
  33  * make sure that KERNEL_RAM_VADDR is correctly set.  Currently, we expect
  34  * the least significant 16 bits to be 0x8000, but we could probably
  35  * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
  36  */
  37 #define KERNEL_RAM_VADDR        (PAGE_OFFSET + TEXT_OFFSET)
  38 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
  39 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
  40 #endif
  41
  42 #ifdef CONFIG_ARM_LPAE
  43         /* LPAE requires an additional page for the PGD */
  44 #define PG_DIR_SIZE     0x5000
  45 #define PMD_ORDER       3
  46 #else
  47 #define PG_DIR_SIZE     0x4000
  48 #define PMD_ORDER       2
  49 #endif
  50
  51         .globl  swapper_pg_dir
  52         .equ    swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
  53
  54         .macro  pgtbl, rd, phys
  55         add     \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
  56         .endm
  57
  58 /*
  59  * Kernel startup entry point.
  60  * ---------------------------
  61  *
  62  * This is normally called from the decompressor code.  The requirements
  63  * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
  64  * r1 = machine nr, r2 = atags or dtb pointer.
  65  *
  66  * This code is mostly position independent, so if you link the kernel at
  67  * 0xc0008000, you call this at __pa(0xc0008000).
  68  *
  69  * See linux/arch/arm/tools/mach-types for the complete list of machine
  70  * numbers for r1.
  71  *
  72  * We're trying to keep crap to a minimum; DO NOT add any machine specific
  73  * crap here - that's what the boot loader (or in extreme, well justified
  74  * circumstances, zImage) is for.
  75  */
  76         .arm
  77
  78         __HEAD
  79 ENTRY(stext)
  80  ARM_BE8(setend be )                    @ ensure we are in BE8 mode
  81
  82  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
  83  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
  84  THUMB( .thumb                  )       @ switch to Thumb now.
  85  THUMB(1:                       )
  86
  87 #ifdef CONFIG_ARM_VIRT_EXT
  88         bl      __hyp_stub_install
  89 #endif
  90         @ ensure svc mode and all interrupts masked
  91         safe_svcmode_maskall r9
  92
  93         mrc     p15, 0, r9, c0, c0              @ get processor id
  94         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
  95         movs    r10, r5                         @ invalid processor (r5=0)?
  96  THUMB( it      eq )            @ force fixup-able long branch encoding
  97         beq     __error_p                       @ yes, error 'p'
  98
  99 #ifdef CONFIG_ARM_LPAE
 100         mrc     p15, 0, r3, c0, c1, 4           @ read ID_MMFR0
 101         and     r3, r3, #0xf                    @ extract VMSA support
 102         cmp     r3, #5                          @ long-descriptor translation table format?
 103  THUMB( it      lo )                            @ force fixup-able long branch encoding
 104         blo     __error_p                       @ only classic page table format
 105 #endif
 106
 107 #ifndef CONFIG_XIP_KERNEL
 108         adr     r3, 2f
 109         ldmia   r3, {r4, r8}
 110         sub     r4, r3, r4                      @ (PHYS_OFFSET - PAGE_OFFSET)
 111         add     r8, r8, r4                      @ PHYS_OFFSET
 112 #else
 113         ldr     r8, =PHYS_OFFSET                @ always constant in this case
 114 #endif
 115
 116         /*
 117          * r1 = machine no, r2 = atags or dtb,
 118          * r8 = phys_offset, r9 = cpuid, r10 = procinfo
 119          */
 120         bl      __vet_atags
 121 #ifdef CONFIG_SMP_ON_UP
 122         bl      __fixup_smp
 123 #endif
 124 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
 125         bl      __fixup_pv_table
 126 #endif
 127         bl      __create_page_tables
 128
 129         /*
 130          * The following calls CPU specific code in a position independent
 131          * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
 132          * xxx_proc_info structure selected by __lookup_processor_type
 133          * above.  On return, the CPU will be ready for the MMU to be
 134          * turned on, and r0 will hold the CPU control register value.
 135          */
 136         ldr     r13, =__mmap_switched           @ address to jump to after
 137                                                 @ mmu has been enabled
 138         adr     lr, BSYM(1f)                    @ return (PIC) address
 139         mov     r8, r4                          @ set TTBR1 to swapper_pg_dir
 140  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
 141  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
 142  THUMB( mov     pc, r12                         )
 143 1:      b       __enable_mmu
 144 ENDPROC(stext)
 145         .ltorg
 146 #ifndef CONFIG_XIP_KERNEL
 147 2:      .long   .
 148         .long   PAGE_OFFSET
 149 #endif
 150
 151 /*
 152  * Setup the initial page tables.  We only setup the barest
 153  * amount which are required to get the kernel running, which
 154  * generally means mapping in the kernel code.
 155  *
 156  * r8 = phys_offset, r9 = cpuid, r10 = procinfo
 157  *
 158  * Returns:
 159  *  r0, r3, r5-r7 corrupted
 160  *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
 161  */
 162 __create_page_tables:
 163         pgtbl   r4, r8                          @ page table address
 164
 165         /*
 166          * Clear the swapper page table
 167          */
 168         mov     r0, r4
 169         mov     r3, #0
 170         add     r6, r0, #PG_DIR_SIZE
 171 1:      str     r3, [r0], #4
 172         str     r3, [r0], #4
 173         str     r3, [r0], #4
 174         str     r3, [r0], #4
 175         teq     r0, r6
 176         bne     1b
 177
 178 #ifdef CONFIG_ARM_LPAE
 179         /*
 180          * Build the PGD table (first level) to point to the PMD table. A PGD
 181          * entry is 64-bit wide.
 182          */
 183         mov     r0, r4
 184         add     r3, r4, #0x1000                 @ first PMD table address
 185         orr     r3, r3, #3                      @ PGD block type
 186         mov     r6, #4                          @ PTRS_PER_PGD
 187         mov     r7, #1 << (55 - 32)             @ L_PGD_SWAPPER
 188 1:
 189 #ifdef CONFIG_CPU_ENDIAN_BE8
 190         str     r7, [r0], #4                    @ set top PGD entry bits
 191         str     r3, [r0], #4                    @ set bottom PGD entry bits
 192 #else
 193         str     r3, [r0], #4                    @ set bottom PGD entry bits
 194         str     r7, [r0], #4                    @ set top PGD entry bits
 195 #endif
 196         add     r3, r3, #0x1000                 @ next PMD table
 197         subs    r6, r6, #1
 198         bne     1b
 199
 200         add     r4, r4, #0x1000                 @ point to the PMD tables
 201 #ifdef CONFIG_CPU_ENDIAN_BE8
 202         add     r4, r4, #4                      @ we only write the bottom word
 203 #endif
 204 #endif
 205
 206         ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
 207
 208         /*
 209          * Create identity mapping to cater for __enable_mmu.
 210          * This identity mapping will be removed by paging_init().
 211          */
 212         adr     r0, __turn_mmu_on_loc
 213         ldmia   r0, {r3, r5, r6}
 214         sub     r0, r0, r3                      @ virt->phys offset
 215         add     r5, r5, r0                      @ phys __turn_mmu_on
 216         add     r6, r6, r0                      @ phys __turn_mmu_on_end
 217         mov     r5, r5, lsr #SECTION_SHIFT
 218         mov     r6, r6, lsr #SECTION_SHIFT
 219
 220 1:      orr     r3, r7, r5, lsl #SECTION_SHIFT  @ flags + kernel base
 221         str     r3, [r4, r5, lsl #PMD_ORDER]    @ identity mapping
 222         cmp     r5, r6
 223         addlo   r5, r5, #1                      @ next section
 224         blo     1b
 225
 226         /*
 227          * Map our RAM from the start to the end of the kernel .bss section.
 228          */
 229         add     r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
 230         ldr     r6, =(_end - 1)
 231         orr     r3, r8, r7
 232         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 233 1:      str     r3, [r0], #1 << PMD_ORDER
 234         add     r3, r3, #1 << SECTION_SHIFT
 235         cmp     r0, r6
 236         bls     1b
 237
 238 #ifdef CONFIG_XIP_KERNEL
 239         /*
 240          * Map the kernel image separately as it is not located in RAM.
 241          */
 242 #define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
 243         mov     r3, pc
 244         mov     r3, r3, lsr #SECTION_SHIFT
 245         orr     r3, r7, r3, lsl #SECTION_SHIFT
 246         add     r0, r4,  #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
 247         str     r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
 248         ldr     r6, =(_edata_loc - 1)
 249         add     r0, r0, #1 << PMD_ORDER
 250         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 251 1:      cmp     r0, r6
 252         add     r3, r3, #1 << SECTION_SHIFT
 253         strls   r3, [r0], #1 << PMD_ORDER
 254         bls     1b
 255 #endif
 256
 257         /*
 258          * Then map boot params address in r2 if specified.
 259          * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
 260          */
 261         mov     r0, r2, lsr #SECTION_SHIFT
 262         movs    r0, r0, lsl #SECTION_SHIFT
 263         subne   r3, r0, r8
 264         addne   r3, r3, #PAGE_OFFSET
 265         addne   r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
 266         orrne   r6, r7, r0
 267         strne   r6, [r3], #1 << PMD_ORDER
 268         addne   r6, r6, #1 << SECTION_SHIFT
 269         strne   r6, [r3]
 270
 271 #if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
 272         sub     r4, r4, #4                      @ Fixup page table pointer
 273                                                 @ for 64-bit descriptors
 274 #endif
 275
 276 #ifdef CONFIG_DEBUG_LL
 277 #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
 278         /*
 279          * Map in IO space for serial debugging.
 280          * This allows debug messages to be output
 281          * via a serial console before paging_init.
 282          */
 283         addruart r7, r3, r0
 284
 285         mov     r3, r3, lsr #SECTION_SHIFT
 286         mov     r3, r3, lsl #PMD_ORDER
 287
 288         add     r0, r4, r3
 289         mov     r3, r7, lsr #SECTION_SHIFT
 290         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 291         orr     r3, r7, r3, lsl #SECTION_SHIFT
 292 #ifdef CONFIG_ARM_LPAE
 293         mov     r7, #1 << (54 - 32)             @ XN
 294 #ifdef CONFIG_CPU_ENDIAN_BE8
 295         str     r7, [r0], #4
 296         str     r3, [r0], #4
 297 #else
 298         str     r3, [r0], #4
 299         str     r7, [r0], #4
 300 #endif
 301 #else
 302         orr     r3, r3, #PMD_SECT_XN
 303         str     r3, [r0], #4
 304 #endif
 305
 306 #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
 307         /* we don't need any serial debugging mappings */
 308         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 309 #endif
 310
 311 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
 312         /*
 313          * If we're using the NetWinder or CATS, we also need to map
 314          * in the 16550-type serial port for the debug messages
 315          */
 316         add     r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
 317         orr     r3, r7, #0x7c000000
 318         str     r3, [r0]
 319 #endif
 320 #ifdef CONFIG_ARCH_RPC
 321         /*
 322          * Map in screen at 0x02000000 & SCREEN2_BASE
 323          * Similar reasons here - for debug.  This is
 324          * only for Acorn RiscPC architectures.
 325          */
 326         add     r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
 327         orr     r3, r7, #0x02000000
 328         str     r3, [r0]
 329         add     r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
 330         str     r3, [r0]
 331 #endif
 332 #endif
 333 #ifdef CONFIG_ARM_LPAE
 334         sub     r4, r4, #0x1000         @ point to the PGD table
 335         mov     r4, r4, lsr #ARCH_PGD_SHIFT
 336 #endif
 337         mov     pc, lr
 338 ENDPROC(__create_page_tables)
 339         .ltorg
 340         .align
 341 __turn_mmu_on_loc:
 342         .long   .
 343         .long   __turn_mmu_on
 344         .long   __turn_mmu_on_end
 345
 346 #if defined(CONFIG_SMP)
 347         .text
 348 ENTRY(secondary_startup)
 349         /*
 350          * Common entry point for secondary CPUs.
 351          *
 352          * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
 353          * the processor type - there is no need to check the machine type
 354          * as it has already been validated by the primary processor.
 355          */
 356
 357  ARM_BE8(setend be)                             @ ensure we are in BE8 mode
 358
 359 #ifdef CONFIG_ARM_VIRT_EXT
 360         bl      __hyp_stub_install_secondary
 361 #endif
 362         safe_svcmode_maskall r9
 363
 364         mrc     p15, 0, r9, c0, c0              @ get processor id
 365         bl      __lookup_processor_type
 366         movs    r10, r5                         @ invalid processor?
 367         moveq   r0, #'p'                        @ yes, error 'p'
 368  THUMB( it      eq )            @ force fixup-able long branch encoding
 369         beq     __error_p
 370
 371         /*
 372          * Use the page tables supplied from  __cpu_up.
 373          */
 374         adr     r4, __secondary_data
 375         ldmia   r4, {r5, r7, r12}               @ address to jump to after
 376         sub     lr, r4, r5                      @ mmu has been enabled
 377         ldr     r4, [r7, lr]                    @ get secondary_data.pgdir
 378         add     r7, r7, #4
 379         ldr     r8, [r7, lr]                    @ get secondary_data.swapper_pg_dir
 380         adr     lr, BSYM(__enable_mmu)          @ return address
 381         mov     r13, r12                        @ __secondary_switched address
 382  ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
 383                                                   @ (return control reg)
 384  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
 385  THUMB( mov     pc, r12                         )
 386 ENDPROC(secondary_startup)
 387
 388         /*
 389          * r6  = &secondary_data
 390          */
 391 ENTRY(__secondary_switched)
 392         ldr     sp, [r7, #4]                    @ get secondary_data.stack
 393         mov     fp, #0
 394         b       secondary_start_kernel
 395 ENDPROC(__secondary_switched)
 396
 397         .align
 398
 399         .type   __secondary_data, %object
 400 __secondary_data:
 401         .long   .
 402         .long   secondary_data
 403         .long   __secondary_switched
 404 #endif /* defined(CONFIG_SMP) */
 405
 406
 407
 408 /*
 409  * Setup common bits before finally enabling the MMU.  Essentially
 410  * this is just loading the page table pointer and domain access
 411  * registers.
 412  *
 413  *  r0  = cp#15 control register
 414  *  r1  = machine ID
 415  *  r2  = atags or dtb pointer
 416  *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
 417  *  r9  = processor ID
 418  *  r13 = *virtual* address to jump to upon completion
 419  */
 420 __enable_mmu:
 421 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
 422         orr     r0, r0, #CR_A
 423 #else
 424         bic     r0, r0, #CR_A
 425 #endif
 426 #ifdef CONFIG_CPU_DCACHE_DISABLE
 427         bic     r0, r0, #CR_C
 428 #endif
 429 #ifdef CONFIG_CPU_BPREDICT_DISABLE
 430         bic     r0, r0, #CR_Z
 431 #endif
 432 #ifdef CONFIG_CPU_ICACHE_DISABLE
 433         bic     r0, r0, #CR_I
 434 #endif
 435 #ifndef CONFIG_ARM_LPAE
 436         mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
 437                       domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
 438                       domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
 439                       domain_val(DOMAIN_IO, DOMAIN_CLIENT))
 440         mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
 441         mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
 442 #endif
 443         b       __turn_mmu_on
 444 ENDPROC(__enable_mmu)
 445
 446 /*
 447  * Enable the MMU.  This completely changes the structure of the visible
 448  * memory space.  You will not be able to trace execution through this.
 449  * If you have an enquiry about this, *please* check the linux-arm-kernel
 450  * mailing list archives BEFORE sending another post to the list.
 451  *
 452  *  r0  = cp#15 control register
 453  *  r1  = machine ID
 454  *  r2  = atags or dtb pointer
 455  *  r9  = processor ID
 456  *  r13 = *virtual* address to jump to upon completion
 457  *
 458  * other registers depend on the function called upon completion
 459  */
 460         .align  5
 461         .pushsection    .idmap.text, "ax"
 462 ENTRY(__turn_mmu_on)
 463         mov     r0, r0
 464         instr_sync
 465         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 466         mrc     p15, 0, r3, c0, c0, 0           @ read id reg
 467         instr_sync
 468         mov     r3, r3
 469         mov     r3, r13
 470         mov     pc, r3
 471 __turn_mmu_on_end:
 472 ENDPROC(__turn_mmu_on)
 473         .popsection
 474
 475
 476 #ifdef CONFIG_SMP_ON_UP
 477         __INIT
 478 __fixup_smp:
 479         and     r3, r9, #0x000f0000     @ architecture version
 480         teq     r3, #0x000f0000         @ CPU ID supported?
 481         bne     __fixup_smp_on_up       @ no, assume UP
 482
 483         bic     r3, r9, #0x00ff0000
 484         bic     r3, r3, #0x0000000f     @ mask 0xff00fff0
 485         mov     r4, #0x41000000
 486         orr     r4, r4, #0x0000b000
 487         orr     r4, r4, #0x00000020     @ val 0x4100b020
 488         teq     r3, r4                  @ ARM 11MPCore?
 489         moveq   pc, lr                  @ yes, assume SMP
 490
 491         mrc     p15, 0, r0, c0, c0, 5   @ read MPIDR
 492         and     r0, r0, #0xc0000000     @ multiprocessing extensions and
 493         teq     r0, #0x80000000         @ not part of a uniprocessor system?
 494         bne    __fixup_smp_on_up        @ no, assume UP
 495
 496         @ Core indicates it is SMP. Check for Aegis SOC where a single
 497         @ Cortex-A9 CPU is present but SMP operations fault.
 498         mov     r4, #0x41000000
 499         orr     r4, r4, #0x0000c000
 500         orr     r4, r4, #0x00000090
 501         teq     r3, r4                  @ Check for ARM Cortex-A9
 502         movne   pc, lr                  @ Not ARM Cortex-A9,
 503
 504         @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the
 505         @ below address check will need to be #ifdef'd or equivalent
 506         @ for the Aegis platform.
 507         mrc     p15, 4, r0, c15, c0     @ get SCU base address
 508         teq     r0, #0x0                @ '0' on actual UP A9 hardware
 509         beq     __fixup_smp_on_up       @ So its an A9 UP
 510         ldr     r0, [r0, #4]            @ read SCU Config
 511 ARM_BE8(rev     r0, r0)                 @ byteswap if big endian
 512         and     r0, r0, #0x3            @ number of CPUs
 513         teq     r0, #0x0                @ is 1?
 514         movne   pc, lr
 515
 516 __fixup_smp_on_up:
 517         adr     r0, 1f
 518         ldmia   r0, {r3 - r5}
 519         sub     r3, r0, r3
 520         add     r4, r4, r3
 521         add     r5, r5, r3
 522         b       __do_fixup_smp_on_up
 523 ENDPROC(__fixup_smp)
 524
 525         .align
 526 1:      .word   .
 527         .word   __smpalt_begin
 528         .word   __smpalt_end
 529
 530         .pushsection .data
 531         .globl  smp_on_up
 532 smp_on_up:
 533         ALT_SMP(.long   1)
 534         ALT_UP(.long    0)
 535         .popsection
 536 #endif
 537
 538         .text
 539 __do_fixup_smp_on_up:
 540         cmp     r4, r5
 541         movhs   pc, lr
 542         ldmia   r4!, {r0, r6}
 543  ARM(   str     r6, [r0, r3]    )
 544  THUMB( add     r0, r0, r3      )
 545 #ifdef __ARMEB__
 546  THUMB( mov     r6, r6, ror #16 )       @ Convert word order for big-endian.
 547 #endif
 548  THUMB( strh    r6, [r0], #2    )       @ For Thumb-2, store as two halfwords
 549  THUMB( mov     r6, r6, lsr #16 )       @ to be robust against misaligned r3.
 550  THUMB( strh    r6, [r0]        )
 551         b       __do_fixup_smp_on_up
 552 ENDPROC(__do_fixup_smp_on_up)
 553
 554 ENTRY(fixup_smp)
 555         stmfd   sp!, {r4 - r6, lr}
 556         mov     r4, r0
 557         add     r5, r0, r1
 558         mov     r3, #0
 559         bl      __do_fixup_smp_on_up
 560         ldmfd   sp!, {r4 - r6, pc}
 561 ENDPROC(fixup_smp)
 562
 563 #ifdef __ARMEB__
 564 #define LOW_OFFSET      0x4
 565 #define HIGH_OFFSET     0x0
 566 #else
 567 #define LOW_OFFSET      0x0
 568 #define HIGH_OFFSET     0x4
 569 #endif
 570
 571 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
 572
 573 /* __fixup_pv_table - patch the stub instructions with the delta between
 574  * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
 575  * can be expressed by an immediate shifter operand. The stub instruction
 576  * has a form of '(add|sub) rd, rn, #imm'.
 577  */
 578         __HEAD
 579 __fixup_pv_table:
 580         adr     r0, 1f
 581         ldmia   r0, {r3-r7}
 582         mvn     ip, #0
 583         subs    r3, r0, r3      @ PHYS_OFFSET - PAGE_OFFSET
 584         add     r4, r4, r3      @ adjust table start address
 585         add     r5, r5, r3      @ adjust table end address
 586         add     r6, r6, r3      @ adjust __pv_phys_offset address
 587         add     r7, r7, r3      @ adjust __pv_offset address
 588         str     r8, [r6, #LOW_OFFSET]   @ save computed PHYS_OFFSET to __pv_phys_offset
 589         strcc   ip, [r7, #HIGH_OFFSET]  @ save to __pv_offset high bits
 590         mov     r6, r3, lsr #24 @ constant for add/sub instructions
 591         teq     r3, r6, lsl #24 @ must be 16MiB aligned
 592 THUMB(  it      ne              @ cross section branch )
 593         bne     __error
 594         str     r3, [r7, #LOW_OFFSET]   @ save to __pv_offset low bits
 595         b       __fixup_a_pv_table
 596 ENDPROC(__fixup_pv_table)
 597
 598         .align
 599 1:      .long   .
 600         .long   __pv_table_begin
 601         .long   __pv_table_end
 602 2:      .long   __pv_phys_offset
 603         .long   __pv_offset
 604
 605         .text
 606 __fixup_a_pv_table:
 607         adr     r0, 3f
 608         ldr     r6, [r0]
 609         add     r6, r6, r3
 610         ldr     r0, [r6, #HIGH_OFFSET]  @ pv_offset high word
 611         ldr     r6, [r6, #LOW_OFFSET]   @ pv_offset low word
 612         mov     r6, r6, lsr #24
 613         cmn     r0, #1
 614 #ifdef CONFIG_THUMB2_KERNEL
 615         moveq   r0, #0x200000   @ set bit 21, mov to mvn instruction
 616         lsls    r6, #24
 617         beq     2f
 618         clz     r7, r6
 619         lsr     r6, #24
 620         lsl     r6, r7
 621         bic     r6, #0x0080
 622         lsrs    r7, #1
 623         orrcs   r6, #0x0080
 624         orr     r6, r6, r7, lsl #12
 625         orr     r6, #0x4000
 626         b       2f
 627 1:      add     r7, r3
 628         ldrh    ip, [r7, #2]
 629 ARM_BE8(rev16   ip, ip)
 630         tst     ip, #0x4000
 631         and     ip, #0x8f00
 632         orrne   ip, r6  @ mask in offset bits 31-24
 633         orreq   ip, r0  @ mask in offset bits 7-0
 634 ARM_BE8(rev16   ip, ip)
 635         strh    ip, [r7, #2]
 636         bne     2f
 637         ldrh    ip, [r7]
 638 ARM_BE8(rev16   ip, ip)
 639         bic     ip, #0x20
 640         orr     ip, ip, r0, lsr #16
 641 ARM_BE8(rev16   ip, ip)
 642         strh    ip, [r7]
 643 2:      cmp     r4, r5
 644         ldrcc   r7, [r4], #4    @ use branch for delay slot
 645         bcc     1b
 646         bx      lr
 647 #else
 648         moveq   r0, #0x400000   @ set bit 22, mov to mvn instruction
 649         b       2f
 650 1:      ldr     ip, [r7, r3]
 651 #ifdef CONFIG_CPU_ENDIAN_BE8
 652         @ in BE8, we load data in BE, but instructions still in LE
 653         bic     ip, ip, #0xff000000
 654         tst     ip, #0x000f0000 @ check the rotation field
 655         orrne   ip, ip, r6, lsl #24 @ mask in offset bits 31-24
 656         biceq   ip, ip, #0x00004000 @ clear bit 22
 657         orreq   ip, ip, r0, lsl #24 @ mask in offset bits 7-0
 658 #else
 659         bic     ip, ip, #0x000000ff
 660         tst     ip, #0xf00      @ check the rotation field
 661         orrne   ip, ip, r6      @ mask in offset bits 31-24
 662         biceq   ip, ip, #0x400000       @ clear bit 22
 663         orreq   ip, ip, r0      @ mask in offset bits 7-0
 664 #endif
 665         str     ip, [r7, r3]
 666 2:      cmp     r4, r5
 667         ldrcc   r7, [r4], #4    @ use branch for delay slot
 668         bcc     1b
 669         mov     pc, lr
 670 #endif
 671 ENDPROC(__fixup_a_pv_table)
 672
 673         .align
 674 3:      .long __pv_offset
 675
 676 ENTRY(fixup_pv_table)
 677         stmfd   sp!, {r4 - r7, lr}
 678         mov     r3, #0                  @ no offset
 679         mov     r4, r0                  @ r0 = table start
 680         add     r5, r0, r1              @ r1 = table size
 681         bl      __fixup_a_pv_table
 682         ldmfd   sp!, {r4 - r7, pc}
 683 ENDPROC(fixup_pv_table)
 684
 685         .data
 686         .globl  __pv_phys_offset
 687         .type   __pv_phys_offset, %object
 688 __pv_phys_offset:
 689         .quad   0
 690         .size   __pv_phys_offset, . -__pv_phys_offset
 691
 692         .globl  __pv_offset
 693         .type   __pv_offset, %object
 694 __pv_offset:
 695         .quad   0
 696         .size   __pv_offset, . -__pv_offset
 697 #endif
 698
 699 #include "head-common.S"