2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009, 2010 ARM Limited
17 * Author: Will Deacon <will.deacon@arm.com>
21 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
22 * using the CPU's debug registers.
24 #define pr_fmt(fmt) "hw-breakpoint: " fmt
26 #include <linux/errno.h>
27 #include <linux/hardirq.h>
28 #include <linux/perf_event.h>
29 #include <linux/hw_breakpoint.h>
30 #include <linux/smp.h>
32 #include <asm/cacheflush.h>
33 #include <asm/cputype.h>
34 #include <asm/current.h>
35 #include <asm/hw_breakpoint.h>
36 #include <asm/kdebug.h>
37 #include <asm/traps.h>
39 /* Breakpoint currently in use for each BRP. */
40 static DEFINE_PER_CPU(struct perf_event
*, bp_on_reg
[ARM_MAX_BRP
]);
42 /* Watchpoint currently in use for each WRP. */
43 static DEFINE_PER_CPU(struct perf_event
*, wp_on_reg
[ARM_MAX_WRP
]);
45 /* Number of BRP/WRP registers on this CPU. */
46 static int core_num_brps
;
47 static int core_num_wrps
;
49 /* Debug architecture version. */
52 /* Maximum supported watchpoint length. */
53 static u8 max_watchpoint_len
;
55 #define READ_WB_REG_CASE(OP2, M, VAL) \
56 case ((OP2 << 4) + M): \
57 ARM_DBG_READ(c ## M, OP2, VAL); \
60 #define WRITE_WB_REG_CASE(OP2, M, VAL) \
61 case ((OP2 << 4) + M): \
62 ARM_DBG_WRITE(c ## M, OP2, VAL);\
65 #define GEN_READ_WB_REG_CASES(OP2, VAL) \
66 READ_WB_REG_CASE(OP2, 0, VAL); \
67 READ_WB_REG_CASE(OP2, 1, VAL); \
68 READ_WB_REG_CASE(OP2, 2, VAL); \
69 READ_WB_REG_CASE(OP2, 3, VAL); \
70 READ_WB_REG_CASE(OP2, 4, VAL); \
71 READ_WB_REG_CASE(OP2, 5, VAL); \
72 READ_WB_REG_CASE(OP2, 6, VAL); \
73 READ_WB_REG_CASE(OP2, 7, VAL); \
74 READ_WB_REG_CASE(OP2, 8, VAL); \
75 READ_WB_REG_CASE(OP2, 9, VAL); \
76 READ_WB_REG_CASE(OP2, 10, VAL); \
77 READ_WB_REG_CASE(OP2, 11, VAL); \
78 READ_WB_REG_CASE(OP2, 12, VAL); \
79 READ_WB_REG_CASE(OP2, 13, VAL); \
80 READ_WB_REG_CASE(OP2, 14, VAL); \
81 READ_WB_REG_CASE(OP2, 15, VAL)
83 #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
84 WRITE_WB_REG_CASE(OP2, 0, VAL); \
85 WRITE_WB_REG_CASE(OP2, 1, VAL); \
86 WRITE_WB_REG_CASE(OP2, 2, VAL); \
87 WRITE_WB_REG_CASE(OP2, 3, VAL); \
88 WRITE_WB_REG_CASE(OP2, 4, VAL); \
89 WRITE_WB_REG_CASE(OP2, 5, VAL); \
90 WRITE_WB_REG_CASE(OP2, 6, VAL); \
91 WRITE_WB_REG_CASE(OP2, 7, VAL); \
92 WRITE_WB_REG_CASE(OP2, 8, VAL); \
93 WRITE_WB_REG_CASE(OP2, 9, VAL); \
94 WRITE_WB_REG_CASE(OP2, 10, VAL); \
95 WRITE_WB_REG_CASE(OP2, 11, VAL); \
96 WRITE_WB_REG_CASE(OP2, 12, VAL); \
97 WRITE_WB_REG_CASE(OP2, 13, VAL); \
98 WRITE_WB_REG_CASE(OP2, 14, VAL); \
99 WRITE_WB_REG_CASE(OP2, 15, VAL)
101 static u32
read_wb_reg(int n
)
106 GEN_READ_WB_REG_CASES(ARM_OP2_BVR
, val
);
107 GEN_READ_WB_REG_CASES(ARM_OP2_BCR
, val
);
108 GEN_READ_WB_REG_CASES(ARM_OP2_WVR
, val
);
109 GEN_READ_WB_REG_CASES(ARM_OP2_WCR
, val
);
111 pr_warning("attempt to read from unknown breakpoint "
118 static void write_wb_reg(int n
, u32 val
)
121 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR
, val
);
122 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR
, val
);
123 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR
, val
);
124 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR
, val
);
126 pr_warning("attempt to write to unknown breakpoint "
132 /* Determine debug architecture. */
133 static u8
get_debug_arch(void)
137 /* Do we implement the extended CPUID interface? */
138 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
139 pr_warning("CPUID feature registers not supported. "
140 "Assuming v6 debug is present.\n");
141 return ARM_DEBUG_ARCH_V6
;
144 ARM_DBG_READ(c0
, 0, didr
);
145 return (didr
>> 16) & 0xf;
148 u8
arch_get_debug_arch(void)
153 static int debug_arch_supported(void)
155 u8 arch
= get_debug_arch();
157 /* We don't support the memory-mapped interface. */
158 return (arch
>= ARM_DEBUG_ARCH_V6
&& arch
<= ARM_DEBUG_ARCH_V7_ECP14
) ||
159 arch
>= ARM_DEBUG_ARCH_V7_1
;
162 /* Determine number of WRP registers available. */
163 static int get_num_wrp_resources(void)
166 ARM_DBG_READ(c0
, 0, didr
);
167 return ((didr
>> 28) & 0xf) + 1;
170 /* Determine number of BRP registers available. */
171 static int get_num_brp_resources(void)
174 ARM_DBG_READ(c0
, 0, didr
);
175 return ((didr
>> 24) & 0xf) + 1;
178 /* Does this core support mismatch breakpoints? */
179 static int core_has_mismatch_brps(void)
181 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14
&&
182 get_num_brp_resources() > 1);
185 /* Determine number of usable WRPs available. */
186 static int get_num_wrps(void)
189 * On debug architectures prior to 7.1, when a watchpoint fires, the
190 * only way to work out which watchpoint it was is by disassembling
191 * the faulting instruction and working out the address of the memory
194 * Furthermore, we can only do this if the watchpoint was precise
195 * since imprecise watchpoints prevent us from calculating register
198 * Providing we have more than 1 breakpoint register, we only report
199 * a single watchpoint register for the time being. This way, we always
200 * know which watchpoint fired. In the future we can either add a
201 * disassembler and address generation emulator, or we can insert a
202 * check to see if the DFAR is set on watchpoint exception entry
203 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
204 * that it is set on some implementations].
206 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1
)
209 return get_num_wrp_resources();
212 /* Determine number of usable BRPs available. */
213 static int get_num_brps(void)
215 int brps
= get_num_brp_resources();
216 return core_has_mismatch_brps() ? brps
- 1 : brps
;
220 * In order to access the breakpoint/watchpoint control registers,
221 * we must be running in debug monitor mode. Unfortunately, we can
222 * be put into halting debug mode at any time by an external debugger
223 * but there is nothing we can do to prevent that.
225 static int enable_monitor_mode(void)
230 ARM_DBG_READ(c1
, 0, dscr
);
232 /* Ensure that halting mode is disabled. */
233 if (WARN_ONCE(dscr
& ARM_DSCR_HDBGEN
,
234 "halting debug mode enabled. Unable to access hardware resources.\n")) {
239 /* If monitor mode is already enabled, just return. */
240 if (dscr
& ARM_DSCR_MDBGEN
)
243 /* Write to the corresponding DSCR. */
244 switch (get_debug_arch()) {
245 case ARM_DEBUG_ARCH_V6
:
246 case ARM_DEBUG_ARCH_V6_1
:
247 ARM_DBG_WRITE(c1
, 0, (dscr
| ARM_DSCR_MDBGEN
));
249 case ARM_DEBUG_ARCH_V7_ECP14
:
250 case ARM_DEBUG_ARCH_V7_1
:
251 ARM_DBG_WRITE(c2
, 2, (dscr
| ARM_DSCR_MDBGEN
));
258 /* Check that the write made it through. */
259 ARM_DBG_READ(c1
, 0, dscr
);
260 if (!(dscr
& ARM_DSCR_MDBGEN
))
267 int hw_breakpoint_slots(int type
)
269 if (!debug_arch_supported())
273 * We can be called early, so don't rely on
274 * our static variables being initialised.
278 return get_num_brps();
280 return get_num_wrps();
282 pr_warning("unknown slot type: %d\n", type
);
288 * Check if 8-bit byte-address select is available.
289 * This clobbers WRP 0.
291 static u8
get_max_wp_len(void)
294 struct arch_hw_breakpoint_ctrl ctrl
;
297 if (debug_arch
< ARM_DEBUG_ARCH_V7_ECP14
)
300 memset(&ctrl
, 0, sizeof(ctrl
));
301 ctrl
.len
= ARM_BREAKPOINT_LEN_8
;
302 ctrl_reg
= encode_ctrl_reg(ctrl
);
304 write_wb_reg(ARM_BASE_WVR
, 0);
305 write_wb_reg(ARM_BASE_WCR
, ctrl_reg
);
306 if ((read_wb_reg(ARM_BASE_WCR
) & ctrl_reg
) == ctrl_reg
)
313 u8
arch_get_max_wp_len(void)
315 return max_watchpoint_len
;
319 * Install a perf counter breakpoint.
321 int arch_install_hw_breakpoint(struct perf_event
*bp
)
323 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
324 struct perf_event
**slot
, **slots
;
325 int i
, max_slots
, ctrl_base
, val_base
, ret
= 0;
328 /* Ensure that we are in monitor mode and halting mode is disabled. */
329 ret
= enable_monitor_mode();
333 addr
= info
->address
;
334 ctrl
= encode_ctrl_reg(info
->ctrl
) | 0x1;
336 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
) {
338 ctrl_base
= ARM_BASE_BCR
;
339 val_base
= ARM_BASE_BVR
;
340 slots
= (struct perf_event
**)__get_cpu_var(bp_on_reg
);
341 max_slots
= core_num_brps
;
344 ctrl_base
= ARM_BASE_WCR
;
345 val_base
= ARM_BASE_WVR
;
346 slots
= (struct perf_event
**)__get_cpu_var(wp_on_reg
);
347 max_slots
= core_num_wrps
;
350 for (i
= 0; i
< max_slots
; ++i
) {
359 if (WARN_ONCE(i
== max_slots
, "Can't find any breakpoint slot\n")) {
364 /* Override the breakpoint data with the step data. */
365 if (info
->step_ctrl
.enabled
) {
366 addr
= info
->trigger
& ~0x3;
367 ctrl
= encode_ctrl_reg(info
->step_ctrl
);
368 if (info
->ctrl
.type
!= ARM_BREAKPOINT_EXECUTE
) {
370 ctrl_base
= ARM_BASE_BCR
+ core_num_brps
;
371 val_base
= ARM_BASE_BVR
+ core_num_brps
;
375 /* Setup the address register. */
376 write_wb_reg(val_base
+ i
, addr
);
378 /* Setup the control register. */
379 write_wb_reg(ctrl_base
+ i
, ctrl
);
385 void arch_uninstall_hw_breakpoint(struct perf_event
*bp
)
387 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
388 struct perf_event
**slot
, **slots
;
389 int i
, max_slots
, base
;
391 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
) {
394 slots
= (struct perf_event
**)__get_cpu_var(bp_on_reg
);
395 max_slots
= core_num_brps
;
399 slots
= (struct perf_event
**)__get_cpu_var(wp_on_reg
);
400 max_slots
= core_num_wrps
;
403 /* Remove the breakpoint. */
404 for (i
= 0; i
< max_slots
; ++i
) {
413 if (WARN_ONCE(i
== max_slots
, "Can't find any breakpoint slot\n"))
416 /* Ensure that we disable the mismatch breakpoint. */
417 if (info
->ctrl
.type
!= ARM_BREAKPOINT_EXECUTE
&&
418 info
->step_ctrl
.enabled
) {
420 base
= ARM_BASE_BCR
+ core_num_brps
;
423 /* Reset the control register. */
424 write_wb_reg(base
+ i
, 0);
427 static int get_hbp_len(u8 hbp_len
)
429 unsigned int len_in_bytes
= 0;
432 case ARM_BREAKPOINT_LEN_1
:
435 case ARM_BREAKPOINT_LEN_2
:
438 case ARM_BREAKPOINT_LEN_4
:
441 case ARM_BREAKPOINT_LEN_8
:
450 * Check whether bp virtual address is in kernel space.
452 int arch_check_bp_in_kernelspace(struct perf_event
*bp
)
456 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
459 len
= get_hbp_len(info
->ctrl
.len
);
461 return (va
>= TASK_SIZE
) && ((va
+ len
- 1) >= TASK_SIZE
);
465 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
466 * Hopefully this will disappear when ptrace can bypass the conversion
467 * to generic breakpoint descriptions.
469 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl
,
470 int *gen_len
, int *gen_type
)
474 case ARM_BREAKPOINT_EXECUTE
:
475 *gen_type
= HW_BREAKPOINT_X
;
477 case ARM_BREAKPOINT_LOAD
:
478 *gen_type
= HW_BREAKPOINT_R
;
480 case ARM_BREAKPOINT_STORE
:
481 *gen_type
= HW_BREAKPOINT_W
;
483 case ARM_BREAKPOINT_LOAD
| ARM_BREAKPOINT_STORE
:
484 *gen_type
= HW_BREAKPOINT_RW
;
492 case ARM_BREAKPOINT_LEN_1
:
493 *gen_len
= HW_BREAKPOINT_LEN_1
;
495 case ARM_BREAKPOINT_LEN_2
:
496 *gen_len
= HW_BREAKPOINT_LEN_2
;
498 case ARM_BREAKPOINT_LEN_4
:
499 *gen_len
= HW_BREAKPOINT_LEN_4
;
501 case ARM_BREAKPOINT_LEN_8
:
502 *gen_len
= HW_BREAKPOINT_LEN_8
;
512 * Construct an arch_hw_breakpoint from a perf_event.
514 static int arch_build_bp_info(struct perf_event
*bp
)
516 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
519 switch (bp
->attr
.bp_type
) {
520 case HW_BREAKPOINT_X
:
521 info
->ctrl
.type
= ARM_BREAKPOINT_EXECUTE
;
523 case HW_BREAKPOINT_R
:
524 info
->ctrl
.type
= ARM_BREAKPOINT_LOAD
;
526 case HW_BREAKPOINT_W
:
527 info
->ctrl
.type
= ARM_BREAKPOINT_STORE
;
529 case HW_BREAKPOINT_RW
:
530 info
->ctrl
.type
= ARM_BREAKPOINT_LOAD
| ARM_BREAKPOINT_STORE
;
537 switch (bp
->attr
.bp_len
) {
538 case HW_BREAKPOINT_LEN_1
:
539 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_1
;
541 case HW_BREAKPOINT_LEN_2
:
542 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_2
;
544 case HW_BREAKPOINT_LEN_4
:
545 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_4
;
547 case HW_BREAKPOINT_LEN_8
:
548 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_8
;
549 if ((info
->ctrl
.type
!= ARM_BREAKPOINT_EXECUTE
)
550 && max_watchpoint_len
>= 8)
557 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
558 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
559 * by the hardware and must be aligned to the appropriate number of
562 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
&&
563 info
->ctrl
.len
!= ARM_BREAKPOINT_LEN_2
&&
564 info
->ctrl
.len
!= ARM_BREAKPOINT_LEN_4
)
568 info
->address
= bp
->attr
.bp_addr
;
571 info
->ctrl
.privilege
= ARM_BREAKPOINT_USER
;
572 if (arch_check_bp_in_kernelspace(bp
))
573 info
->ctrl
.privilege
|= ARM_BREAKPOINT_PRIV
;
576 info
->ctrl
.enabled
= !bp
->attr
.disabled
;
579 info
->ctrl
.mismatch
= 0;
585 * Validate the arch-specific HW Breakpoint register settings.
587 int arch_validate_hwbkpt_settings(struct perf_event
*bp
)
589 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
591 u32 offset
, alignment_mask
= 0x3;
593 /* Build the arch_hw_breakpoint. */
594 ret
= arch_build_bp_info(bp
);
598 /* Check address alignment. */
599 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_8
)
600 alignment_mask
= 0x7;
601 offset
= info
->address
& alignment_mask
;
607 /* Allow single byte watchpoint. */
608 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_1
)
611 /* Allow halfword watchpoints and breakpoints. */
612 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_2
)
619 info
->address
&= ~alignment_mask
;
620 info
->ctrl
.len
<<= offset
;
623 * Currently we rely on an overflow handler to take
624 * care of single-stepping the breakpoint when it fires.
625 * In the case of userspace breakpoints on a core with V7 debug,
626 * we can use the mismatch feature as a poor-man's hardware
627 * single-step, but this only works for per-task breakpoints.
629 if (!bp
->overflow_handler
&& (arch_check_bp_in_kernelspace(bp
) ||
630 !core_has_mismatch_brps() || !bp
->hw
.bp_target
)) {
631 pr_warning("overflow handler required but none found\n");
639 * Enable/disable single-stepping over the breakpoint bp at address addr.
641 static void enable_single_step(struct perf_event
*bp
, u32 addr
)
643 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
645 arch_uninstall_hw_breakpoint(bp
);
646 info
->step_ctrl
.mismatch
= 1;
647 info
->step_ctrl
.len
= ARM_BREAKPOINT_LEN_4
;
648 info
->step_ctrl
.type
= ARM_BREAKPOINT_EXECUTE
;
649 info
->step_ctrl
.privilege
= info
->ctrl
.privilege
;
650 info
->step_ctrl
.enabled
= 1;
651 info
->trigger
= addr
;
652 arch_install_hw_breakpoint(bp
);
655 static void disable_single_step(struct perf_event
*bp
)
657 arch_uninstall_hw_breakpoint(bp
);
658 counter_arch_bp(bp
)->step_ctrl
.enabled
= 0;
659 arch_install_hw_breakpoint(bp
);
662 static void watchpoint_handler(unsigned long addr
, unsigned int fsr
,
663 struct pt_regs
*regs
)
666 u32 val
, ctrl_reg
, alignment_mask
;
667 struct perf_event
*wp
, **slots
;
668 struct arch_hw_breakpoint
*info
;
669 struct arch_hw_breakpoint_ctrl ctrl
;
671 slots
= (struct perf_event
**)__get_cpu_var(wp_on_reg
);
673 for (i
= 0; i
< core_num_wrps
; ++i
) {
681 info
= counter_arch_bp(wp
);
683 * The DFAR is an unknown value on debug architectures prior
684 * to 7.1. Since we only allow a single watchpoint on these
685 * older CPUs, we can set the trigger to the lowest possible
688 if (debug_arch
< ARM_DEBUG_ARCH_V7_1
) {
690 info
->trigger
= wp
->attr
.bp_addr
;
692 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_8
)
693 alignment_mask
= 0x7;
695 alignment_mask
= 0x3;
697 /* Check if the watchpoint value matches. */
698 val
= read_wb_reg(ARM_BASE_WVR
+ i
);
699 if (val
!= (addr
& ~alignment_mask
))
702 /* Possible match, check the byte address select. */
703 ctrl_reg
= read_wb_reg(ARM_BASE_WCR
+ i
);
704 decode_ctrl_reg(ctrl_reg
, &ctrl
);
705 if (!((1 << (addr
& alignment_mask
)) & ctrl
.len
))
708 /* Check that the access type matches. */
709 access
= (fsr
& ARM_FSR_ACCESS_MASK
) ? HW_BREAKPOINT_W
:
711 if (!(access
& hw_breakpoint_type(wp
)))
714 /* We have a winner. */
715 info
->trigger
= addr
;
718 pr_debug("watchpoint fired: address = 0x%x\n", info
->trigger
);
719 perf_bp_event(wp
, regs
);
722 * If no overflow handler is present, insert a temporary
723 * mismatch breakpoint so we can single-step over the
724 * watchpoint trigger.
726 if (!wp
->overflow_handler
)
727 enable_single_step(wp
, instruction_pointer(regs
));
734 static void watchpoint_single_step_handler(unsigned long pc
)
737 struct perf_event
*wp
, **slots
;
738 struct arch_hw_breakpoint
*info
;
740 slots
= (struct perf_event
**)__get_cpu_var(wp_on_reg
);
742 for (i
= 0; i
< core_num_wrps
; ++i
) {
750 info
= counter_arch_bp(wp
);
751 if (!info
->step_ctrl
.enabled
)
755 * Restore the original watchpoint if we've completed the
758 if (info
->trigger
!= pc
)
759 disable_single_step(wp
);
766 static void breakpoint_handler(unsigned long unknown
, struct pt_regs
*regs
)
769 u32 ctrl_reg
, val
, addr
;
770 struct perf_event
*bp
, **slots
;
771 struct arch_hw_breakpoint
*info
;
772 struct arch_hw_breakpoint_ctrl ctrl
;
774 slots
= (struct perf_event
**)__get_cpu_var(bp_on_reg
);
776 /* The exception entry code places the amended lr in the PC. */
779 /* Check the currently installed breakpoints first. */
780 for (i
= 0; i
< core_num_brps
; ++i
) {
788 info
= counter_arch_bp(bp
);
790 /* Check if the breakpoint value matches. */
791 val
= read_wb_reg(ARM_BASE_BVR
+ i
);
792 if (val
!= (addr
& ~0x3))
795 /* Possible match, check the byte address select to confirm. */
796 ctrl_reg
= read_wb_reg(ARM_BASE_BCR
+ i
);
797 decode_ctrl_reg(ctrl_reg
, &ctrl
);
798 if ((1 << (addr
& 0x3)) & ctrl
.len
) {
799 info
->trigger
= addr
;
800 pr_debug("breakpoint fired: address = 0x%x\n", addr
);
801 perf_bp_event(bp
, regs
);
802 if (!bp
->overflow_handler
)
803 enable_single_step(bp
, addr
);
808 /* If we're stepping a breakpoint, it can now be restored. */
809 if (info
->step_ctrl
.enabled
)
810 disable_single_step(bp
);
815 /* Handle any pending watchpoint single-step breakpoints. */
816 watchpoint_single_step_handler(addr
);
820 * Called from either the Data Abort Handler [watchpoint] or the
821 * Prefetch Abort Handler [breakpoint] with interrupts disabled.
823 static int hw_breakpoint_pending(unsigned long addr
, unsigned int fsr
,
824 struct pt_regs
*regs
)
831 if (interrupts_enabled(regs
))
834 /* We only handle watchpoints and hardware breakpoints. */
835 ARM_DBG_READ(c1
, 0, dscr
);
837 /* Perform perf callbacks. */
838 switch (ARM_DSCR_MOE(dscr
)) {
839 case ARM_ENTRY_BREAKPOINT
:
840 breakpoint_handler(addr
, regs
);
842 case ARM_ENTRY_ASYNC_WATCHPOINT
:
843 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
844 case ARM_ENTRY_SYNC_WATCHPOINT
:
845 watchpoint_handler(addr
, fsr
, regs
);
848 ret
= 1; /* Unhandled fault. */
857 * One-time initialisation.
859 static cpumask_t debug_err_mask
;
861 static int debug_reg_trap(struct pt_regs
*regs
, unsigned int instr
)
863 int cpu
= smp_processor_id();
865 pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
868 /* Set the error flag for this CPU and skip the faulting instruction. */
869 cpumask_set_cpu(cpu
, &debug_err_mask
);
870 instruction_pointer(regs
) += 4;
874 static struct undef_hook debug_reg_hook
= {
875 .instr_mask
= 0x0fe80f10,
876 .instr_val
= 0x0e000e10,
877 .fn
= debug_reg_trap
,
880 static void reset_ctrl_regs(void *unused
)
882 int i
, raw_num_brps
, err
= 0, cpu
= smp_processor_id();
886 * v7 debug contains save and restore registers so that debug state
887 * can be maintained across low-power modes without leaving the debug
888 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
889 * the debug registers out of reset, so we must unlock the OS Lock
890 * Access Register to avoid taking undefined instruction exceptions
893 switch (debug_arch
) {
894 case ARM_DEBUG_ARCH_V6
:
895 case ARM_DEBUG_ARCH_V6_1
:
896 /* ARMv6 cores just need to reset the registers. */
898 case ARM_DEBUG_ARCH_V7_ECP14
:
900 * Ensure sticky power-down is clear (i.e. debug logic is
903 asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power
));
904 if ((dbg_power
& 0x1) == 0)
907 case ARM_DEBUG_ARCH_V7_1
:
909 * Ensure the OS double lock is clear.
911 asm volatile("mrc p14, 0, %0, c1, c3, 4" : "=r" (dbg_power
));
912 if ((dbg_power
& 0x1) == 1)
918 pr_warning("CPU %d debug is powered down!\n", cpu
);
919 cpumask_or(&debug_err_mask
, &debug_err_mask
, cpumask_of(cpu
));
924 * Unconditionally clear the lock by writing a value
925 * other than 0xC5ACCE55 to the access register.
927 asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
931 * Clear any configured vector-catch events before
932 * enabling monitor mode.
934 asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
938 if (enable_monitor_mode())
941 /* We must also reset any reserved registers. */
942 raw_num_brps
= get_num_brp_resources();
943 for (i
= 0; i
< raw_num_brps
; ++i
) {
944 write_wb_reg(ARM_BASE_BCR
+ i
, 0UL);
945 write_wb_reg(ARM_BASE_BVR
+ i
, 0UL);
948 for (i
= 0; i
< core_num_wrps
; ++i
) {
949 write_wb_reg(ARM_BASE_WCR
+ i
, 0UL);
950 write_wb_reg(ARM_BASE_WVR
+ i
, 0UL);
954 static int __cpuinit
dbg_reset_notify(struct notifier_block
*self
,
955 unsigned long action
, void *cpu
)
957 if (action
== CPU_ONLINE
)
958 smp_call_function_single((int)cpu
, reset_ctrl_regs
, NULL
, 1);
963 static struct notifier_block __cpuinitdata dbg_reset_nb
= {
964 .notifier_call
= dbg_reset_notify
,
967 static int __init
arch_hw_breakpoint_init(void)
971 debug_arch
= get_debug_arch();
973 if (!debug_arch_supported()) {
974 pr_info("debug architecture 0x%x unsupported.\n", debug_arch
);
978 /* Determine how many BRPs/WRPs are available. */
979 core_num_brps
= get_num_brps();
980 core_num_wrps
= get_num_wrps();
983 * We need to tread carefully here because DBGSWENABLE may be
984 * driven low on this core and there isn't an architected way to
987 register_undef_hook(&debug_reg_hook
);
990 * Reset the breakpoint resources. We assume that a halting
991 * debugger will leave the world in a nice state for us.
993 on_each_cpu(reset_ctrl_regs
, NULL
, 1);
994 unregister_undef_hook(&debug_reg_hook
);
995 if (!cpumask_empty(&debug_err_mask
)) {
1001 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1002 core_num_brps
, core_has_mismatch_brps() ? "(+1 reserved) " :
1005 ARM_DBG_READ(c1
, 0, dscr
);
1006 if (dscr
& ARM_DSCR_HDBGEN
) {
1007 max_watchpoint_len
= 4;
1008 pr_warning("halting debug mode enabled. Assuming maximum watchpoint size of %u bytes.\n",
1009 max_watchpoint_len
);
1011 /* Work out the maximum supported watchpoint length. */
1012 max_watchpoint_len
= get_max_wp_len();
1013 pr_info("maximum watchpoint size is %u bytes.\n",
1014 max_watchpoint_len
);
1017 /* Register debug fault handler. */
1018 hook_fault_code(FAULT_CODE_DEBUG
, hw_breakpoint_pending
, SIGTRAP
,
1019 TRAP_HWBKPT
, "watchpoint debug exception");
1020 hook_ifault_code(FAULT_CODE_DEBUG
, hw_breakpoint_pending
, SIGTRAP
,
1021 TRAP_HWBKPT
, "breakpoint debug exception");
1023 /* Register hotplug notifier. */
1024 register_cpu_notifier(&dbg_reset_nb
);
1027 arch_initcall(arch_hw_breakpoint_init
);
1029 void hw_breakpoint_pmu_read(struct perf_event
*bp
)
1034 * Dummy function to register with die_notifier.
1036 int hw_breakpoint_exceptions_notify(struct notifier_block
*unused
,
1037 unsigned long val
, void *data
)