Merge tag 'for-linus-20150901' of git://git.infradead.org/linux-mtd
[deliverable/linux.git] / arch / arm / kernel / irq.c
1 /*
2 * linux/arch/arm/kernel/irq.c
3 *
4 * Copyright (C) 1992 Linus Torvalds
5 * Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
6 *
7 * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
8 * Dynamic Tick Timer written by Tony Lindgren <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * This file contains the code used by various IRQ handling routines:
16 * asking for different IRQ's should be done through these routines
17 * instead of just grabbing them. Thus setups with different IRQ numbers
18 * shouldn't result in any weird surprises, and installing new handlers
19 * should be easier.
20 *
21 * IRQ's are in fact implemented a bit like signal handlers for the kernel.
22 * Naturally it's not a 1:1 relation, but there are similarities.
23 */
24 #include <linux/kernel_stat.h>
25 #include <linux/signal.h>
26 #include <linux/ioport.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/irqchip.h>
30 #include <linux/random.h>
31 #include <linux/smp.h>
32 #include <linux/init.h>
33 #include <linux/seq_file.h>
34 #include <linux/ratelimit.h>
35 #include <linux/errno.h>
36 #include <linux/list.h>
37 #include <linux/kallsyms.h>
38 #include <linux/proc_fs.h>
39 #include <linux/export.h>
40
41 #include <asm/hardware/cache-l2x0.h>
42 #include <asm/exception.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
46
47 unsigned long irq_err_count;
48
49 int arch_show_interrupts(struct seq_file *p, int prec)
50 {
51 #ifdef CONFIG_FIQ
52 show_fiq_list(p, prec);
53 #endif
54 #ifdef CONFIG_SMP
55 show_ipi_list(p, prec);
56 #endif
57 seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
58 return 0;
59 }
60
61 /*
62 * handle_IRQ handles all hardware IRQ's. Decoded IRQs should
63 * not come via this function. Instead, they should provide their
64 * own 'handler'. Used by platform code implementing C-based 1st
65 * level decoding.
66 */
67 void handle_IRQ(unsigned int irq, struct pt_regs *regs)
68 {
69 __handle_domain_irq(NULL, irq, false, regs);
70 }
71
72 /*
73 * asm_do_IRQ is the interface to be used from assembly code.
74 */
75 asmlinkage void __exception_irq_entry
76 asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
77 {
78 handle_IRQ(irq, regs);
79 }
80
81 void set_irq_flags(unsigned int irq, unsigned int iflags)
82 {
83 unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
84
85 if (irq >= nr_irqs) {
86 pr_err("Trying to set irq flags for IRQ%d\n", irq);
87 return;
88 }
89
90 if (iflags & IRQF_VALID)
91 clr |= IRQ_NOREQUEST;
92 if (iflags & IRQF_PROBE)
93 clr |= IRQ_NOPROBE;
94 if (!(iflags & IRQF_NOAUTOEN))
95 clr |= IRQ_NOAUTOEN;
96 /* Order is clear bits in "clr" then set bits in "set" */
97 irq_modify_status(irq, clr, set & ~clr);
98 }
99 EXPORT_SYMBOL_GPL(set_irq_flags);
100
101 void __init init_IRQ(void)
102 {
103 int ret;
104
105 if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
106 irqchip_init();
107 else
108 machine_desc->init_irq();
109
110 if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
111 (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
112 if (!outer_cache.write_sec)
113 outer_cache.write_sec = machine_desc->l2c_write_sec;
114 ret = l2x0_of_init(machine_desc->l2c_aux_val,
115 machine_desc->l2c_aux_mask);
116 if (ret)
117 pr_err("L2C: failed to init: %d\n", ret);
118 }
119 }
120
121 #ifdef CONFIG_MULTI_IRQ_HANDLER
122 void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
123 {
124 if (handle_arch_irq)
125 return;
126
127 handle_arch_irq = handle_irq;
128 }
129 #endif
130
131 #ifdef CONFIG_SPARSE_IRQ
132 int __init arch_probe_nr_irqs(void)
133 {
134 nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS;
135 return nr_irqs;
136 }
137 #endif
138
139 #ifdef CONFIG_HOTPLUG_CPU
140 static bool migrate_one_irq(struct irq_desc *desc)
141 {
142 struct irq_data *d = irq_desc_get_irq_data(desc);
143 const struct cpumask *affinity = irq_data_get_affinity_mask(d);
144 struct irq_chip *c;
145 bool ret = false;
146
147 /*
148 * If this is a per-CPU interrupt, or the affinity does not
149 * include this CPU, then we have nothing to do.
150 */
151 if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
152 return false;
153
154 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
155 affinity = cpu_online_mask;
156 ret = true;
157 }
158
159 c = irq_data_get_irq_chip(d);
160 if (!c->irq_set_affinity)
161 pr_debug("IRQ%u: unable to set affinity\n", d->irq);
162 else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
163 cpumask_copy(irq_data_get_affinity_mask(d), affinity);
164
165 return ret;
166 }
167
168 /*
169 * The current CPU has been marked offline. Migrate IRQs off this CPU.
170 * If the affinity settings do not allow other CPUs, force them onto any
171 * available CPU.
172 *
173 * Note: we must iterate over all IRQs, whether they have an attached
174 * action structure or not, as we need to get chained interrupts too.
175 */
176 void migrate_irqs(void)
177 {
178 unsigned int i;
179 struct irq_desc *desc;
180 unsigned long flags;
181
182 local_irq_save(flags);
183
184 for_each_irq_desc(i, desc) {
185 bool affinity_broken;
186
187 raw_spin_lock(&desc->lock);
188 affinity_broken = migrate_one_irq(desc);
189 raw_spin_unlock(&desc->lock);
190
191 if (affinity_broken)
192 pr_warn_ratelimited("IRQ%u no longer affine to CPU%u\n",
193 i, smp_processor_id());
194 }
195
196 local_irq_restore(flags);
197 }
198 #endif /* CONFIG_HOTPLUG_CPU */
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