arch/arm/kernel/perf_event.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
  11  * code.
  12  */
  13 #define pr_fmt(fmt) "hw perfevents: " fmt
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/perf_event.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/uaccess.h>
  22
  23 #include <asm/cputype.h>
  24 #include <asm/irq.h>
  25 #include <asm/irq_regs.h>
  26 #include <asm/pmu.h>
  27 #include <asm/stacktrace.h>
  28
  29 /*
  30  * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
  31  * another platform that supports more, we need to increase this to be the
  32  * largest of all platforms.
  33  *
  34  * ARMv7 supports up to 32 events:
  35  *  cycle counter CCNT + 31 events counters CNT0..30.
  36  *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
  37  */
  38 #define ARMPMU_MAX_HWEVENTS             32
  39
  40 /* The events for a given CPU. */
  41 struct cpu_hw_events {
  42         /*
  43          * The events that are active on the CPU for the given index.
  44          */
  45         struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
  46
  47         /*
  48          * A 1 bit for an index indicates that the counter is being used for
  49          * an event. A 0 means that the counter can be used.
  50          */
  51         unsigned long           used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
  52
  53         /*
  54          * Hardware lock to serialize accesses to PMU registers. Needed for the
  55          * read/modify/write sequences.
  56          */
  57         raw_spinlock_t          pmu_lock;
  58 };
  59 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
  60
  61 struct arm_pmu {
  62         enum arm_perf_pmu_ids id;
  63         cpumask_t       active_irqs;
  64         const char      *name;
  65         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
  66         void            (*enable)(struct hw_perf_event *evt, int idx);
  67         void            (*disable)(struct hw_perf_event *evt, int idx);
  68         int             (*get_event_idx)(struct cpu_hw_events *cpuc,
  69                                          struct hw_perf_event *hwc);
  70         int             (*set_event_filter)(struct hw_perf_event *evt,
  71                                             struct perf_event_attr *attr);
  72         u32             (*read_counter)(int idx);
  73         void            (*write_counter)(int idx, u32 val);
  74         void            (*start)(void);
  75         void            (*stop)(void);
  76         void            (*reset)(void *);
  77         const unsigned  (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
  78                                     [PERF_COUNT_HW_CACHE_OP_MAX]
  79                                     [PERF_COUNT_HW_CACHE_RESULT_MAX];
  80         const unsigned  (*event_map)[PERF_COUNT_HW_MAX];
  81         u32             raw_event_mask;
  82         int             num_events;
  83         atomic_t        active_events;
  84         struct mutex    reserve_mutex;
  85         u64             max_period;
  86         struct platform_device  *plat_device;
  87         struct cpu_hw_events    *(*get_hw_events)(void);
  88 };
  89
  90 /* Set at runtime when we know what CPU type we are. */
  91 static struct arm_pmu *armpmu;
  92
  93 enum arm_perf_pmu_ids
  94 armpmu_get_pmu_id(void)
  95 {
  96         int id = -ENODEV;
  97
  98         if (armpmu != NULL)
  99                 id = armpmu->id;
 100
 101         return id;
 102 }
 103 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
 104
 105 int
 106 armpmu_get_max_events(void)
 107 {
 108         int max_events = 0;
 109
 110         if (armpmu != NULL)
 111                 max_events = armpmu->num_events;
 112
 113         return max_events;
 114 }
 115 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
 116
 117 int perf_num_counters(void)
 118 {
 119         return armpmu_get_max_events();
 120 }
 121 EXPORT_SYMBOL_GPL(perf_num_counters);
 122
 123 #define HW_OP_UNSUPPORTED               0xFFFF
 124
 125 #define C(_x) \
 126         PERF_COUNT_HW_CACHE_##_x
 127
 128 #define CACHE_OP_UNSUPPORTED            0xFFFF
 129
 130 static int
 131 armpmu_map_cache_event(u64 config)
 132 {
 133         unsigned int cache_type, cache_op, cache_result, ret;
 134
 135         cache_type = (config >>  0) & 0xff;
 136         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 137                 return -EINVAL;
 138
 139         cache_op = (config >>  8) & 0xff;
 140         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 141                 return -EINVAL;
 142
 143         cache_result = (config >> 16) & 0xff;
 144         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 145                 return -EINVAL;
 146
 147         ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
 148
 149         if (ret == CACHE_OP_UNSUPPORTED)
 150                 return -ENOENT;
 151
 152         return ret;
 153 }
 154
 155 static int
 156 armpmu_map_event(u64 config)
 157 {
 158         int mapping = (*armpmu->event_map)[config];
 159         return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
 160 }
 161
 162 static int
 163 armpmu_map_raw_event(u64 config)
 164 {
 165         return (int)(config & armpmu->raw_event_mask);
 166 }
 167
 168 static int
 169 armpmu_event_set_period(struct perf_event *event,
 170                         struct hw_perf_event *hwc,
 171                         int idx)
 172 {
 173         s64 left = local64_read(&hwc->period_left);
 174         s64 period = hwc->sample_period;
 175         int ret = 0;
 176
 177         if (unlikely(left <= -period)) {
 178                 left = period;
 179                 local64_set(&hwc->period_left, left);
 180                 hwc->last_period = period;
 181                 ret = 1;
 182         }
 183
 184         if (unlikely(left <= 0)) {
 185                 left += period;
 186                 local64_set(&hwc->period_left, left);
 187                 hwc->last_period = period;
 188                 ret = 1;
 189         }
 190
 191         if (left > (s64)armpmu->max_period)
 192                 left = armpmu->max_period;
 193
 194         local64_set(&hwc->prev_count, (u64)-left);
 195
 196         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
 197
 198         perf_event_update_userpage(event);
 199
 200         return ret;
 201 }
 202
 203 static u64
 204 armpmu_event_update(struct perf_event *event,
 205                     struct hw_perf_event *hwc,
 206                     int idx, int overflow)
 207 {
 208         u64 delta, prev_raw_count, new_raw_count;
 209
 210 again:
 211         prev_raw_count = local64_read(&hwc->prev_count);
 212         new_raw_count = armpmu->read_counter(idx);
 213
 214         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 215                              new_raw_count) != prev_raw_count)
 216                 goto again;
 217
 218         new_raw_count &= armpmu->max_period;
 219         prev_raw_count &= armpmu->max_period;
 220
 221         if (overflow)
 222                 delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
 223         else
 224                 delta = new_raw_count - prev_raw_count;
 225
 226         local64_add(delta, &event->count);
 227         local64_sub(delta, &hwc->period_left);
 228
 229         return new_raw_count;
 230 }
 231
 232 static void
 233 armpmu_read(struct perf_event *event)
 234 {
 235         struct hw_perf_event *hwc = &event->hw;
 236
 237         /* Don't read disabled counters! */
 238         if (hwc->idx < 0)
 239                 return;
 240
 241         armpmu_event_update(event, hwc, hwc->idx, 0);
 242 }
 243
 244 static void
 245 armpmu_stop(struct perf_event *event, int flags)
 246 {
 247         struct hw_perf_event *hwc = &event->hw;
 248
 249         /*
 250          * ARM pmu always has to update the counter, so ignore
 251          * PERF_EF_UPDATE, see comments in armpmu_start().
 252          */
 253         if (!(hwc->state & PERF_HES_STOPPED)) {
 254                 armpmu->disable(hwc, hwc->idx);
 255                 barrier(); /* why? */
 256                 armpmu_event_update(event, hwc, hwc->idx, 0);
 257                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 258         }
 259 }
 260
 261 static void
 262 armpmu_start(struct perf_event *event, int flags)
 263 {
 264         struct hw_perf_event *hwc = &event->hw;
 265
 266         /*
 267          * ARM pmu always has to reprogram the period, so ignore
 268          * PERF_EF_RELOAD, see the comment below.
 269          */
 270         if (flags & PERF_EF_RELOAD)
 271                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 272
 273         hwc->state = 0;
 274         /*
 275          * Set the period again. Some counters can't be stopped, so when we
 276          * were stopped we simply disabled the IRQ source and the counter
 277          * may have been left counting. If we don't do this step then we may
 278          * get an interrupt too soon or *way* too late if the overflow has
 279          * happened since disabling.
 280          */
 281         armpmu_event_set_period(event, hwc, hwc->idx);
 282         armpmu->enable(hwc, hwc->idx);
 283 }
 284
 285 static void
 286 armpmu_del(struct perf_event *event, int flags)
 287 {
 288         struct cpu_hw_events *cpuc = armpmu->get_hw_events();
 289         struct hw_perf_event *hwc = &event->hw;
 290         int idx = hwc->idx;
 291
 292         WARN_ON(idx < 0);
 293
 294         armpmu_stop(event, PERF_EF_UPDATE);
 295         cpuc->events[idx] = NULL;
 296         clear_bit(idx, cpuc->used_mask);
 297
 298         perf_event_update_userpage(event);
 299 }
 300
 301 static int
 302 armpmu_add(struct perf_event *event, int flags)
 303 {
 304         struct cpu_hw_events *cpuc = armpmu->get_hw_events();
 305         struct hw_perf_event *hwc = &event->hw;
 306         int idx;
 307         int err = 0;
 308
 309         perf_pmu_disable(event->pmu);
 310
 311         /* If we don't have a space for the counter then finish early. */
 312         idx = armpmu->get_event_idx(cpuc, hwc);
 313         if (idx < 0) {
 314                 err = idx;
 315                 goto out;
 316         }
 317
 318         /*
 319          * If there is an event in the counter we are going to use then make
 320          * sure it is disabled.
 321          */
 322         event->hw.idx = idx;
 323         armpmu->disable(hwc, idx);
 324         cpuc->events[idx] = event;
 325
 326         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 327         if (flags & PERF_EF_START)
 328                 armpmu_start(event, PERF_EF_RELOAD);
 329
 330         /* Propagate our changes to the userspace mapping. */
 331         perf_event_update_userpage(event);
 332
 333 out:
 334         perf_pmu_enable(event->pmu);
 335         return err;
 336 }
 337
 338 static struct pmu pmu;
 339
 340 static int
 341 validate_event(struct cpu_hw_events *cpuc,
 342                struct perf_event *event)
 343 {
 344         struct hw_perf_event fake_event = event->hw;
 345         struct pmu *leader_pmu = event->group_leader->pmu;
 346
 347         if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
 348                 return 1;
 349
 350         return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
 351 }
 352
 353 static int
 354 validate_group(struct perf_event *event)
 355 {
 356         struct perf_event *sibling, *leader = event->group_leader;
 357         struct cpu_hw_events fake_pmu;
 358
 359         memset(&fake_pmu, 0, sizeof(fake_pmu));
 360
 361         if (!validate_event(&fake_pmu, leader))
 362                 return -ENOSPC;
 363
 364         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 365                 if (!validate_event(&fake_pmu, sibling))
 366                         return -ENOSPC;
 367         }
 368
 369         if (!validate_event(&fake_pmu, event))
 370                 return -ENOSPC;
 371
 372         return 0;
 373 }
 374
 375 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
 376 {
 377         struct platform_device *plat_device = armpmu->plat_device;
 378         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 379
 380         return plat->handle_irq(irq, dev, armpmu->handle_irq);
 381 }
 382
 383 static void
 384 armpmu_release_hardware(void)
 385 {
 386         int i, irq, irqs;
 387         struct platform_device *pmu_device = armpmu->plat_device;
 388
 389         irqs = min(pmu_device->num_resources, num_possible_cpus());
 390
 391         for (i = 0; i < irqs; ++i) {
 392                 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
 393                         continue;
 394                 irq = platform_get_irq(pmu_device, i);
 395                 if (irq >= 0)
 396                         free_irq(irq, NULL);
 397         }
 398
 399         release_pmu(ARM_PMU_DEVICE_CPU);
 400 }
 401
 402 static int
 403 armpmu_reserve_hardware(void)
 404 {
 405         struct arm_pmu_platdata *plat;
 406         irq_handler_t handle_irq;
 407         int i, err, irq, irqs;
 408         struct platform_device *pmu_device = armpmu->plat_device;
 409
 410         err = reserve_pmu(ARM_PMU_DEVICE_CPU);
 411         if (err) {
 412                 pr_warning("unable to reserve pmu\n");
 413                 return err;
 414         }
 415
 416         plat = dev_get_platdata(&pmu_device->dev);
 417         if (plat && plat->handle_irq)
 418                 handle_irq = armpmu_platform_irq;
 419         else
 420                 handle_irq = armpmu->handle_irq;
 421
 422         irqs = min(pmu_device->num_resources, num_possible_cpus());
 423         if (irqs < 1) {
 424                 pr_err("no irqs for PMUs defined\n");
 425                 return -ENODEV;
 426         }
 427
 428         for (i = 0; i < irqs; ++i) {
 429                 err = 0;
 430                 irq = platform_get_irq(pmu_device, i);
 431                 if (irq < 0)
 432                         continue;
 433
 434                 /*
 435                  * If we have a single PMU interrupt that we can't shift,
 436                  * assume that we're running on a uniprocessor machine and
 437                  * continue. Otherwise, continue without this interrupt.
 438                  */
 439                 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
 440                         pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
 441                                     irq, i);
 442                         continue;
 443                 }
 444
 445                 err = request_irq(irq, handle_irq,
 446                                   IRQF_DISABLED | IRQF_NOBALANCING,
 447                                   "arm-pmu", NULL);
 448                 if (err) {
 449                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
 450                                 irq);
 451                         armpmu_release_hardware();
 452                         return err;
 453                 }
 454
 455                 cpumask_set_cpu(i, &armpmu->active_irqs);
 456         }
 457
 458         return 0;
 459 }
 460
 461 static void
 462 hw_perf_event_destroy(struct perf_event *event)
 463 {
 464         atomic_t *active_events  = &armpmu->active_events;
 465         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 466
 467         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 468                 armpmu_release_hardware();
 469                 mutex_unlock(pmu_reserve_mutex);
 470         }
 471 }
 472
 473 static int
 474 event_requires_mode_exclusion(struct perf_event_attr *attr)
 475 {
 476         return attr->exclude_idle || attr->exclude_user ||
 477                attr->exclude_kernel || attr->exclude_hv;
 478 }
 479
 480 static int
 481 __hw_perf_event_init(struct perf_event *event)
 482 {
 483         struct hw_perf_event *hwc = &event->hw;
 484         int mapping, err;
 485
 486         /* Decode the generic type into an ARM event identifier. */
 487         if (PERF_TYPE_HARDWARE == event->attr.type) {
 488                 mapping = armpmu_map_event(event->attr.config);
 489         } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
 490                 mapping = armpmu_map_cache_event(event->attr.config);
 491         } else if (PERF_TYPE_RAW == event->attr.type) {
 492                 mapping = armpmu_map_raw_event(event->attr.config);
 493         } else {
 494                 pr_debug("event type %x not supported\n", event->attr.type);
 495                 return -EOPNOTSUPP;
 496         }
 497
 498         if (mapping < 0) {
 499                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 500                          event->attr.config);
 501                 return mapping;
 502         }
 503
 504         /*
 505          * We don't assign an index until we actually place the event onto
 506          * hardware. Use -1 to signify that we haven't decided where to put it
 507          * yet. For SMP systems, each core has it's own PMU so we can't do any
 508          * clever allocation or constraints checking at this point.
 509          */
 510         hwc->idx                = -1;
 511         hwc->config_base        = 0;
 512         hwc->config             = 0;
 513         hwc->event_base         = 0;
 514
 515         /*
 516          * Check whether we need to exclude the counter from certain modes.
 517          */
 518         if ((!armpmu->set_event_filter ||
 519              armpmu->set_event_filter(hwc, &event->attr)) &&
 520              event_requires_mode_exclusion(&event->attr)) {
 521                 pr_debug("ARM performance counters do not support "
 522                          "mode exclusion\n");
 523                 return -EPERM;
 524         }
 525
 526         /*
 527          * Store the event encoding into the config_base field.
 528          */
 529         hwc->config_base            |= (unsigned long)mapping;
 530
 531         if (!hwc->sample_period) {
 532                 hwc->sample_period  = armpmu->max_period;
 533                 hwc->last_period    = hwc->sample_period;
 534                 local64_set(&hwc->period_left, hwc->sample_period);
 535         }
 536
 537         err = 0;
 538         if (event->group_leader != event) {
 539                 err = validate_group(event);
 540                 if (err)
 541                         return -EINVAL;
 542         }
 543
 544         return err;
 545 }
 546
 547 static int armpmu_event_init(struct perf_event *event)
 548 {
 549         int err = 0;
 550         atomic_t *active_events = &armpmu->active_events;
 551
 552         switch (event->attr.type) {
 553         case PERF_TYPE_RAW:
 554         case PERF_TYPE_HARDWARE:
 555         case PERF_TYPE_HW_CACHE:
 556                 break;
 557
 558         default:
 559                 return -ENOENT;
 560         }
 561
 562         event->destroy = hw_perf_event_destroy;
 563
 564         if (!atomic_inc_not_zero(active_events)) {
 565                 mutex_lock(&armpmu->reserve_mutex);
 566                 if (atomic_read(active_events) == 0)
 567                         err = armpmu_reserve_hardware();
 568
 569                 if (!err)
 570                         atomic_inc(active_events);
 571                 mutex_unlock(&armpmu->reserve_mutex);
 572         }
 573
 574         if (err)
 575                 return err;
 576
 577         err = __hw_perf_event_init(event);
 578         if (err)
 579                 hw_perf_event_destroy(event);
 580
 581         return err;
 582 }
 583
 584 static void armpmu_enable(struct pmu *pmu)
 585 {
 586         /* Enable all of the perf events on hardware. */
 587         int idx, enabled = 0;
 588         struct cpu_hw_events *cpuc = armpmu->get_hw_events();
 589
 590         for (idx = 0; idx < armpmu->num_events; ++idx) {
 591                 struct perf_event *event = cpuc->events[idx];
 592
 593                 if (!event)
 594                         continue;
 595
 596                 armpmu->enable(&event->hw, idx);
 597                 enabled = 1;
 598         }
 599
 600         if (enabled)
 601                 armpmu->start();
 602 }
 603
 604 static void armpmu_disable(struct pmu *pmu)
 605 {
 606         armpmu->stop();
 607 }
 608
 609 static struct pmu pmu = {
 610         .pmu_enable     = armpmu_enable,
 611         .pmu_disable    = armpmu_disable,
 612         .event_init     = armpmu_event_init,
 613         .add            = armpmu_add,
 614         .del            = armpmu_del,
 615         .start          = armpmu_start,
 616         .stop           = armpmu_stop,
 617         .read           = armpmu_read,
 618 };
 619
 620 static void __init armpmu_init(struct arm_pmu *armpmu)
 621 {
 622         atomic_set(&armpmu->active_events, 0);
 623         mutex_init(&armpmu->reserve_mutex);
 624 }
 625
 626 /* Include the PMU-specific implementations. */
 627 #include "perf_event_xscale.c"
 628 #include "perf_event_v6.c"
 629 #include "perf_event_v7.c"
 630
 631 /*
 632  * Ensure the PMU has sane values out of reset.
 633  * This requires SMP to be available, so exists as a separate initcall.
 634  */
 635 static int __init
 636 armpmu_reset(void)
 637 {
 638         if (armpmu && armpmu->reset)
 639                 return on_each_cpu(armpmu->reset, NULL, 1);
 640         return 0;
 641 }
 642 arch_initcall(armpmu_reset);
 643
 644 /*
 645  * PMU platform driver and devicetree bindings.
 646  */
 647 static struct of_device_id armpmu_of_device_ids[] = {
 648         {.compatible = "arm,cortex-a9-pmu"},
 649         {.compatible = "arm,cortex-a8-pmu"},
 650         {.compatible = "arm,arm1136-pmu"},
 651         {.compatible = "arm,arm1176-pmu"},
 652         {},
 653 };
 654
 655 static struct platform_device_id armpmu_plat_device_ids[] = {
 656         {.name = "arm-pmu"},
 657         {},
 658 };
 659
 660 static int __devinit armpmu_device_probe(struct platform_device *pdev)
 661 {
 662         armpmu->plat_device = pdev;
 663         return 0;
 664 }
 665
 666 static struct platform_driver armpmu_driver = {
 667         .driver         = {
 668                 .name   = "arm-pmu",
 669                 .of_match_table = armpmu_of_device_ids,
 670         },
 671         .probe          = armpmu_device_probe,
 672         .id_table       = armpmu_plat_device_ids,
 673 };
 674
 675 static int __init register_pmu_driver(void)
 676 {
 677         return platform_driver_register(&armpmu_driver);
 678 }
 679 device_initcall(register_pmu_driver);
 680
 681 static struct cpu_hw_events *armpmu_get_cpu_events(void)
 682 {
 683         return &__get_cpu_var(cpu_hw_events);
 684 }
 685
 686 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
 687 {
 688         int cpu;
 689         for_each_possible_cpu(cpu) {
 690                 struct cpu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
 691                 raw_spin_lock_init(&events->pmu_lock);
 692         }
 693         armpmu->get_hw_events = armpmu_get_cpu_events;
 694 }
 695
 696 /*
 697  * CPU PMU identification and registration.
 698  */
 699 static int __init
 700 init_hw_perf_events(void)
 701 {
 702         unsigned long cpuid = read_cpuid_id();
 703         unsigned long implementor = (cpuid & 0xFF000000) >> 24;
 704         unsigned long part_number = (cpuid & 0xFFF0);
 705
 706         /* ARM Ltd CPUs. */
 707         if (0x41 == implementor) {
 708                 switch (part_number) {
 709                 case 0xB360:    /* ARM1136 */
 710                 case 0xB560:    /* ARM1156 */
 711                 case 0xB760:    /* ARM1176 */
 712                         armpmu = armv6pmu_init();
 713                         break;
 714                 case 0xB020:    /* ARM11mpcore */
 715                         armpmu = armv6mpcore_pmu_init();
 716                         break;
 717                 case 0xC080:    /* Cortex-A8 */
 718                         armpmu = armv7_a8_pmu_init();
 719                         break;
 720                 case 0xC090:    /* Cortex-A9 */
 721                         armpmu = armv7_a9_pmu_init();
 722                         break;
 723                 case 0xC050:    /* Cortex-A5 */
 724                         armpmu = armv7_a5_pmu_init();
 725                         break;
 726                 case 0xC0F0:    /* Cortex-A15 */
 727                         armpmu = armv7_a15_pmu_init();
 728                         break;
 729                 }
 730         /* Intel CPUs [xscale]. */
 731         } else if (0x69 == implementor) {
 732                 part_number = (cpuid >> 13) & 0x7;
 733                 switch (part_number) {
 734                 case 1:
 735                         armpmu = xscale1pmu_init();
 736                         break;
 737                 case 2:
 738                         armpmu = xscale2pmu_init();
 739                         break;
 740                 }
 741         }
 742
 743         if (armpmu) {
 744                 pr_info("enabled with %s PMU driver, %d counters available\n",
 745                         armpmu->name, armpmu->num_events);
 746                 cpu_pmu_init(armpmu);
 747                 armpmu_init(armpmu);
 748                 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
 749         } else {
 750                 pr_info("no hardware support available\n");
 751         }
 752
 753         return 0;
 754 }
 755 early_initcall(init_hw_perf_events);
 756
 757 /*
 758  * Callchain handling code.
 759  */
 760
 761 /*
 762  * The registers we're interested in are at the end of the variable
 763  * length saved register structure. The fp points at the end of this
 764  * structure so the address of this struct is:
 765  * (struct frame_tail *)(xxx->fp)-1
 766  *
 767  * This code has been adapted from the ARM OProfile support.
 768  */
 769 struct frame_tail {
 770         struct frame_tail __user *fp;
 771         unsigned long sp;
 772         unsigned long lr;
 773 } __attribute__((packed));
 774
 775 /*
 776  * Get the return address for a single stackframe and return a pointer to the
 777  * next frame tail.
 778  */
 779 static struct frame_tail __user *
 780 user_backtrace(struct frame_tail __user *tail,
 781                struct perf_callchain_entry *entry)
 782 {
 783         struct frame_tail buftail;
 784
 785         /* Also check accessibility of one struct frame_tail beyond */
 786         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
 787                 return NULL;
 788         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
 789                 return NULL;
 790
 791         perf_callchain_store(entry, buftail.lr);
 792
 793         /*
 794          * Frame pointers should strictly progress back up the stack
 795          * (towards higher addresses).
 796          */
 797         if (tail + 1 >= buftail.fp)
 798                 return NULL;
 799
 800         return buftail.fp - 1;
 801 }
 802
 803 void
 804 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 805 {
 806         struct frame_tail __user *tail;
 807
 808
 809         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 810
 811         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
 812                tail && !((unsigned long)tail & 0x3))
 813                 tail = user_backtrace(tail, entry);
 814 }
 815
 816 /*
 817  * Gets called by walk_stackframe() for every stackframe. This will be called
 818  * whist unwinding the stackframe and is like a subroutine return so we use
 819  * the PC.
 820  */
 821 static int
 822 callchain_trace(struct stackframe *fr,
 823                 void *data)
 824 {
 825         struct perf_callchain_entry *entry = data;
 826         perf_callchain_store(entry, fr->pc);
 827         return 0;
 828 }
 829
 830 void
 831 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 832 {
 833         struct stackframe fr;
 834
 835         fr.fp = regs->ARM_fp;
 836         fr.sp = regs->ARM_sp;
 837         fr.lr = regs->ARM_lr;
 838         fr.pc = regs->ARM_pc;
 839         walk_stackframe(&fr, callchain_trace, entry);
 840 }